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- [[File:Myriadrf1-1.jpg|center|550px|Myriad-RF 1, top]] The Myriad–RF 1 board is a multi-band, multi-standard RF module, based on the [http://www.l ...3 KB (425 words) - 21:52, 15 September 2015
- ...face to the development kit. The following sections describe the Myriad-RF 1's on-board connections.. ===Myriad-RF 1 Board Connections=== ...10 KB (1,475 words) - 16:01, 15 September 2015
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- ...and the [[#Zipper Interface Board#|Zipper Interface Board]]. The Myriad-RF 1 communicates with one of these two boards via the [[#RFDIO Interface|Radio ===Myriad-RF 1=== ...3 KB (363 words) - 10:36, 22 December 2016
- === Version 1=== * One connector for the [[Reference_Development_Kit#Myriad-RF 1|Myriad-RF 1 reference board]] ...2 KB (277 words) - 13:02, 23 January 2016
- # Add a buffer to allow J4 to be used as 1-pps output # Support external 1-pps GPS locking. ...827 bytes (131 words) - 15:56, 15 September 2015
- [[File:Myriadrf1-1.jpg|center|550px|Myriad-RF 1, top]] The Myriad–RF 1 board is a multi-band, multi-standard RF module, based on the [http://www.l ...3 KB (425 words) - 21:52, 15 September 2015
- [[File:DE0-Nano-Interface-Board-1.jpg|center|550px|DE0-Nano Interface Board, top]] ...ce]]. The DE0-Nano Interface Board acts as a motherboard for the Myriad-RF 1 and the DE0-Nano FPGA Development System, mating the two together with a hi ...3 KB (397 words) - 16:02, 15 September 2015
- |1 - Ignore timestamp, transmit as soon as possible. Prior synchronised packet |1 - TX received packet with obsolete timestamp. ...6 KB (761 words) - 16:03, 31 May 2016
- ...ent). Standard FPGA JTAG connector has 10 pins in 2x5 configuration with 0.1" (2.54mm) pitch. Standard JTAG connector is too large for such a small PCB * JTAG connector on the board edge (Pitch 0.1", 7 pin) (unpopulated) ...3 KB (373 words) - 12:49, 10 April 2018
- Phase noise at 300MHz LO frequency is as shown in Figure 1. [[File:LimeSDR-Mini_v1.2_PN_300.png|thumb|center|640px|Figure 1. Phase noise at 300MHz LO frequency ]] ...1,016 bytes (153 words) - 14:34, 3 June 2019
- [[File:Zipper-1.jpg|center|550px|Zipper Interface Board, top]] ...[[Reference Development Kit]]. The combination of the Zipper and Myriad-RF 1 boards provides a low-cost universal radio development platform, based on t ...2 KB (253 words) - 16:05, 15 September 2015
- ...nnector FX10A-80P. For more information on standalone use, see [[Myriad-RF 1 Connections]]. |J1 || Myriad-RF 1 to HSMC and Pin Header || Connects the Myriad-RF 1 board with HSMC and the Pin Header via the FX10A-80P standard connector. ...6 KB (951 words) - 16:05, 15 September 2015
- ...bfb5aeb3f. From this revision you can disable DFU (global variable ''NODFU=1'') or set to only downloading mode (preventing reading current firmware ove |'''NODFU=1''' ...1 KB (171 words) - 14:37, 27 May 2015
- # Connect GNSS antenna to J4 SMA connector (see Figure 1). ...hardware_description#Power_Distribution 3.8 Power Distribution] and Figure 1 for other power options). ...4 KB (590 words) - 13:25, 11 April 2019
- ...ltration in the following equation <nowiki>FilteredVal = (FILTER_EXP_ALPHA-1)*(FilteredVal/FILTER_EXP_ALPHA) + (1pps_count);</nowiki> where FILTER_EXP_A ## If 1pps_count doesn't have less than 1% margin of `FilteredVal/FILTER_EXP_ALPHA` it will not be used and this valu ...2 KB (263 words) - 15:59, 15 September 2015
- ...yriad-RF 1]] to the USB3 bus. The combination of the DigiRED and Myriad-RF 1 boards provides a low-cost receiver platform, based on the flexible, multi- Apart from the [[Myriad-RF 1]] board which provides the radio interface, the RASDR device uses a board t ...3 KB (444 words) - 21:10, 15 September 2015
- * When idle, ''SCK'' is high, i.e. '''CPOL=1'''. Data is read on the clock's rising edge (low->high transition), i.e. '' # Set ''nReset'' to 1. ...2 KB (202 words) - 15:58, 15 September 2015
- SetLPF(1.5e6). // Set LPF to 1 MHz ...nNormalized(0.2). // Set gain to 0.2 in Normalized value (0 -> 1) ...5 KB (559 words) - 04:09, 3 January 2019
- | Power Output<sup>1</sup>|| up to 0 dBm <sup>1</sup> LTE modulated output ...2 KB (359 words) - 13:34, 6 September 2019
- * FPGA_GPIO 1 : TX (from computer to Stream board) Error: JTAG tap: or1200.cpu expected 1 of 1: 0x020b30dd (mfg: 0x06e, part: 0x20b3, ver: 0x0) ...3 KB (523 words) - 16:18, 15 September 2015
- 1. Launch Lime Suite GUI (LimeSuiteGUI.exe on Windows or just ‘LimeSuiteGUI 1. In LimeSuite GUI click the ‘Open’ button ...7 KB (1,038 words) - 15:38, 21 February 2018
- ** 1.2-5.5V IO on J2 * <span style="background:#00ff00">J2 Level shifted interface (1.2-5.5V)</span> ...5 KB (671 words) - 08:14, 21 February 2018