Packet structure
The total packet size is 4096 bytes. A packet consists of two main parts: the header and the payload. The header contains receiver and transmitter status flags and the packet timestamp. The timestamp is a 64-bit samples counter used to synchronise received and transmitted signals. The counter is incremented with each sample after the receiver is enabled. The timestamp can be reset to 0 by using SMPL_NR_CLR bit; packet streaming should be disabled when resetting the timestamp. The payload contains RF sample data, the data format and ordering depending on the number of active channels and each sample's bit count.
| Byte Index |
Bits |
Description
|
| 0 |
15-12 |
Reserved
|
| 4 |
Disable timestamp synchronisation for this packet. Gets OR'ed with SPI_SYNCH_DIS.
|
| 0 - Synchronise packet transmission with timestamp (for transmitting only).
|
| 1 - Ignore timestamp, transmit as soon as possible. Prior synchronised packets existing in FIFO can delay transmission of unsynchronised packets.
|
| 3 |
TX packet dropped:
|
| 0 - TX is working normally.
|
| 1 - TX received packet with obsolete timestamp.
|
| 2-0 |
FPGA RX FIFO fill status:
|
| 0 - from 0% to 12.5%
|
| 1 - from 12.5% to 25%
|
| 2 - from 25% to 37.5%
|
| 3 - from 37.5% to 50%
|
| 4 - from 50% to 62.5%
|
| 5 - from 62.5% to 75%
|
| 6 - from 75% to 87.5%
|
| 7 - from 87.5% to 100%
|
| 1-7 |
15-0 |
Reserved
|
| 8-15 |
15-0 |
Timestamp: 64-bit sample counter, stored in Big Endian format.
|
| When receiving: timestamp when the first sample in the payload was received.
|
| When transmitting: timestamp when the first sample in the payload should be transmitted.
|
Payload structure
| Byte Index |
Bits |
Description
|
| 16-3095 |
15-0 |
RF sample data: sample format and ordering depends on the Streaming configuration
|
Streaming configuration
The streaming configuration should be set before initiating data streaming. The protocol configuration is set by writing to board SPI registers. An address marked DNU means Do Not Use; the register bit is unsupported in the device.
Configuration registers
| Address |
Default value |
Bits |
Name |
Description |
LimeSDR-USB 1v2
|
| 0x0000 |
|
15-0 |
Board ID |
|
000E
|
| 0x0001 |
|
15-0 |
GW function |
|
1
|
| 0x0002 |
|
15-0 |
GW revision |
|
|
| 0x0003 |
00F0 |
15-8 |
Reserved |
|
|
| 7-4 |
GW_TEST_RES |
Read-only, returns inverted bits from GW_TEST. |
|
| 3-0 |
GW_TEST |
Vlue to test GW SPI. |
|
| 0x0004 |
0000 |
15-0 |
PHASE_REG_SEL |
Value for phase shift in direct clocking mode. |
|
| 0x0005 |
0000 |
15-0 |
DRCT_CLK_EN |
Each bit enables the clock to be a direct clock source: 1 - Enabled, 0 - Disabled. |
|
| [n] - nth clock |
|
| [1] - Second clock |
RX clk
|
| [0] - First clock |
TX clk
|
| 0x0006 |
0000 |
15-11 |
Reserved |
|
|
| 10 |
LOAD_PH_REG |
"1" loads phase shift value from PHASE_REG_SEL to phase shift module. |
|
| 9-5 |
CNT_IND |
Clock counter selection |
|
| 4-0 |
CLK_IND |
Clock selection |
0 - TX clk, 1 - RX clk
|
| 0x0007 |
0003 |
15-0 |
CH_EN |
MIMO channel enable. Each bit means: 1 - Enabled, 0 - Disabled. |
|
| [n] - nth channel |
|
| [1] - Channel 1 |
|
| [0] - Channel 0 |
|
| 0x0008 |
0102 |
15-11 |
Reserved |
|
|
| 10 |
Reserved |
|
DNU
|
| 9 |
SYNCH_DIS |
Packet synchronisation using timestamps: |
|
| 0 - Enabled |
|
| 1 - Disabled |
|
| 8 |
MIMO_INT_EN |
|
|
| 7-2 |
Reserved |
|
|
| 1-0 |
SMPL_WIDTH |
"10" - 12-bit |
|
| "01" - 14-bit |
|
| "00" - 16-bit |
|
| 0x0009 |
0003 |
15-2 |
Reserved |
|
|
| 1 |
TXPCT_LOSS_CLR |
Rising edge clears flag regarding RX packet dropping. |
|
| 0 |
SMPL_NR_CLR |
Reset timestamp: RX and TX should be stopped when resetting. |
|
| 1 - |
|
| 0 - Normal operation |
|
| 0x000A |
0000 |
15-3 |
Reserved |
|
|
| 2 |
STREAM_LOAD |
|
DNU
|
| 1 |
TX_EN |
|
|
| 0 |
RX_EN |
|
|
12-bit compressed samples
When using 12-bit compressed sample configuration, the packet payload has the following structure. Bytes are indexed from the start of the payload.
| Byte index |
Bits |
Description
|
| 0 |
7-0 |
ch0_I0[7:0]
|
| 1 |
7-4 |
ch0_Q0[3:0]
|
| 3-0 |
ch0_I0[11:8]
|
| 2 |
7-0 |
ch0_Q0[11:4]
|
| 3 |
7-0 |
ch1_I1[7:0]
|
| 4 |
7-4 |
ch1_Q1[3:0]
|
| 3-0 |
ch1_I1[11:8]
|
| 5 |
7-0 |
ch1_Q1[11:4]
|
| ... |
... |
...
|
16-bit compressed samples
When using 16-bit compressed sample configuration, the packet payload has the following structure. Bytes are indexed from the start of the payload.
| Byte index |
Bits |
Description
|
| 0 |
7-0 |
ch0_I0[7:0]
|
| 1 |
7-0 |
ch0_I0[15:8]
|
| 2 |
7-0 |
ch0_Q0[7:0]
|
| 3 |
7-0 |
ch0_Q0[15:0]
|
| 4 |
7-0 |
ch1_I1[7:0]
|
| 5 |
7-0 |
ch1_I1[15:8]
|
| 6 |
7-0 |
ch1_Q1[7:0]
|
| 7 |
7-0 |
ch1_Q1[15:8]
|
| ... |
... |
...
|
Document version
Based on Stream Protocol Datasheet, Version 05r00.
Changes since document generation:
- Minor typographical and grammatical modifications.
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