LMS6002 Pmod: Difference between revisions
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* JTAG headers for programming the FPGA | * JTAG headers for programming the FPGA | ||
* One connector for the [[Reference_Development_Kit#Myriad-RF 1|Myriad-RF 1 reference board]] | * One connector for the [[Reference_Development_Kit#Myriad-RF 1|Myriad-RF 1 reference board]] | ||
=== Relevant Documentation === | |||
* [http://www.latticesemi.com/view_document?document_id=49312 Ice40 LP/HX Family Datasheet] | |||
{{Community}} | {{Community}} | ||
Revision as of 11:36, 23 January 2016
About
The LMS6022 Pmod is a project to explore the usage of an LMS6002 chip over Digilent's Pmod interface.
The Pmod interface is a very simple interface:
- It has eight I/O pins, plus 3.3V and GND
- The speed is limited to some medium speed around 25-50 MHz
To exchange I/Q samples with the LMS6002 it is therefore necessary to multiplex and serialize the data, which limits the overall capabilities to a few MSamples/s. The actual pin level protocol is yet undecided and we will explore it with the final design.
To make the protocol between the Pmod host board and the LMS6002 configurable and to be as flexible as possible, the Pmod will employ a small ICE40 FPGA from Lattice. This can be programmed with the entire open source tool flow of Clifford Wolf (Project IceStorm).
Version 1
In the first version, the board will not have the actual LMS6002, but instead use the connector for the reference board.
The following components are on the board:
- One ICE40 FPGA
- One PCB mounted Pmod connector
- One breakout Pmod connector
- JTAG headers for programming the FPGA
- One connector for the Myriad-RF 1 reference board
Relevant Documentation
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