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Showing below up to 250 results in range #1 to #250.
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1-ClockTamer-kit.jpg 864 × 504; 73 KB
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2-ClockTamer-CMOS.jpg 576 × 360; 44 KB
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3-ClockTamer-halfLVDS.jpg 576 × 360; 46 KB
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4-ClockTamer-with-power.jpg 792 × 504; 52 KB
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5-clock-connected.jpg 720 × 576; 101 KB
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6-power-connected.jpg 648 × 504; 103 KB
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659x-Digired-Block-Diagram.jpg 659 × 399; 83 KB
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7-fan-connected.jpg 720 × 504; 105 KB
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ADF4002 configuration window.png 1,186 × 728; 269 KB
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Adpd-implementation-on-limesdr-qpcie-board-block-diagram.png 1,692 × 890; 158 KB
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Adpd-indirect-learning-architecture-block-diagram.png 1,481 × 725; 60 KB
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Adpd-test-case-1-acpr-with-adpd.png 1,032 × 776; 37 KB
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Adpd-test-case-1-acpr-without-adpd.png 1,032 × 776; 37 KB
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Adpd-test-case-1-evm-with-adpd.png 1,032 × 776; 52 KB
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Adpd-test-case-1-evm-without-adpd.png 1,032 × 776; 53 KB
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Adpd-test-case-1-pa-output-spectrum.png 1,032 × 776; 35 KB
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Adpd-test-case-1-signals-after-training.png 1,302 × 876; 47 KB
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Adpd-test-case-1-signals-before-training.png 1,302 × 876; 50 KB
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Adpd-test-case-2-acpr-with-adpd.png 518 × 329; 7 KB
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Adpd-test-case-2-acpr-without-adpd.png 517 × 333; 7 KB
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Apple logo.jpg 107 × 80; 1 KB
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Asr2300-Tutorial1.png 160 × 116; 32 KB
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Asr2300-Tutorial2.png 160 × 116; 24 KB
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Blackhat-logo.png 100 × 43; 5 KB
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Board related controls.png 767 × 430; 111 KB
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Board related controls temperature section.png 799 × 449; 122 KB
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Build logo.png 100 × 96; 13 KB
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Calibrated Rx Spectrum.png 836 × 452; 75 KB
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Calibrated Tx output.png 730 × 618; 96 KB
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ClockTamer-1.1-top-small.jpg 319 × 200; 35 KB
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ClockTamer-1.1-top.jpg 1,997 × 1,251; 464 KB
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ClockTamer-1.2-GPS-back-small.jpg 300 × 200; 36 KB
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ClockTamer-1.2-PCB-bottom.png 1,708 × 683; 57 KB
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ClockTamer-1.2-PCB-top.png 1,708 × 683; 153 KB
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ClockTamer-1.2-all-top-small.jpg 300 × 200; 40 KB
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ClockTamer-1.2-all-top.jpg 2,519 × 1,680; 661 KB
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ClockTamer-1.2-back-small.jpg 300 × 200; 36 KB
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ClockTamer-1.2-back.jpg 2,789 × 1,859; 579 KB
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ClockTamer-1.2-phase-noise.png 640 × 480; 21 KB
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ClockTamer-1.2-top-small.jpg 300 × 200; 43 KB
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ClockTamer-1.2-top.jpg 1,024 × 683; 159 KB
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ClockTamer-xgps.png 651 × 731; 68 KB
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ClockTamerCurrent-limiting-resistor.jpg 576 × 432; 56 KB
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ClockTamerSide.jpg 1,024 × 682; 61 KB
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ClockTamerSide crop.jpg 393 × 353; 24 KB
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ClockTamerTop.jpg 1,024 × 682; 104 KB
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ClockTamerTop crop.jpg 364 × 353; 27 KB
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ClockTamer top cable 2.jpg 1,024 × 682; 143 KB
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Clocktamer-nSS.png 292 × 165; 90 KB
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Clocktamer cmos at usrp.png 800 × 539; 36 KB
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Clocktamer lvds at usrp.png 800 × 539; 37 KB
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Close WX GUI Button GnuRadio.png 743 × 504; 61 KB
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DC offset block control.png 1,185 × 708; 242 KB
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DE0-Nano-1.jpg 470 × 345; 74 KB
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DE0-Nano-Connections.jpg 622 × 530; 54 KB
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DE0-Nano-Interface-Board-1.jpg 587 × 530; 157 KB
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DE0-Nano-Interface-Board-Schematics-1.png 2,480 × 3,508; 144 KB
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DE0-Nano-Interface-Board-Schematics-2.png 2,480 × 3,508; 222 KB
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DE0-Nano-Interface-Board-Schematics-3.png 2,480 × 3,508; 194 KB
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DE0-Nano-Interface-Board-Schematics-4.png 2,480 × 3,508; 171 KB
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DE0-Nano-Interface-Board-Schematics-5.png 2,480 × 3,508; 65 KB
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DE0-Nano-Interface-Board-Schematics-6.png 2,480 × 3,508; 88 KB
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DE0-Nano-J2.jpg 444 × 886; 61 KB
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DE0-Nano-J4.jpg 439 × 343; 15 KB
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DE0-Nano-J6.jpg 640 × 394; 18 KB
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DE0-Nano-J7.jpg 254 × 280; 6 KB
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DE0-Nano-J8-J9.jpg 454 × 534; 12 KB
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DE0-Nano-JA1.jpg 927 × 873; 127 KB
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DE0interfaceboard-Assembled-1.jpg 337 × 302; 57 KB
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DVB-T transmitter example.png 1,263 × 516; 121 KB
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Digired-clock-generator.png 616 × 899; 56 KB
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Digired-connectors.png 616 × 899; 62 KB
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Digired-digital-interface.png 616 × 899; 38 KB
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Digired-power-supply.png 616 × 899; 51 KB
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Digired-usb3-interface.png 617 × 899; 50 KB
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Documentation Tab GnuRadio.png 500 × 528; 44 KB
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Enable DC corrector in RxTSP.png 1,185 × 709; 259 KB
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Enable the test NCO.png 1,187 × 706; 243 KB
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Example.png 384 × 190; 25 KB
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FFTviewer Controls.png 679 × 476; 80 KB
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FFTviewer window in operation.png 712 × 791; 130 KB
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FM Receiver Example GnuRadio.png 1,183 × 491; 93 KB
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FM Transmitter Example GnuRadio.png 888 × 495; 70 KB
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FREEBSD Logo Horiz Pos RGB.png 570 × 164; 33 KB
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FX3 after custom firmware is downloaded.png 701 × 610; 161 KB
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FX3 programing options.png 893 × 261; 61 KB
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Figure 10 Lime-GPSDO board power distribution block diagram.png 677 × 183; 10 KB
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Figure 11 LimeSDR-QPCIe v1.2 Dedicated FAN mounting space.png 433 × 432; 226 KB
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Figure 12 LimeSDR-QPCIe v1.2 board clock distribution block diagram.png 1,457 × 1,186; 85 KB
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Figure 13 LimeSDR-QPCIe v1.2 board power distribution block diagrams.png 3,473 × 1,643; 536 KB
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Figure 14 LimeSDR-QPCIe v1.2 board power ICs on TOP side.png 763 × 471; 475 KB
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Figure 15 LimeSDR-QPCIe v1.2 board power ICs on BOTTOM side.png 767 × 473; 505 KB
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Figure 1 Lime-GPSDO top side components and connectors.png 2,247 × 1,237; 815 KB
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Figure 2 Bottom side components.png 1,243 × 832; 351 KB
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Figure 3 Lime-GPSDO Development Board Block Diagram.png 869 × 373; 20 KB
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Figure 4 Time pulse output selection.png 1,455 × 904; 95 KB
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Figure 5 Power rail selection for pin 10 of J12 connector.png 1,252 × 911; 96 KB
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Figure 6 Communication interfaces.png 868 × 362; 15 KB
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Figure 7 FAN control temperature hysteresis.png 536 × 275; 5 KB
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Figure 8 Lime-GPSDO board clock distribution block diagram.png 793 × 410; 16 KB
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Figure 9 LimeSDR-QPCIe v1.2 indication LEDs.png 463 × 382; 120 KB
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Figure 9 SMA connector J6 source selection.png 1,336 × 759; 70 KB
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Freebsd-128-128.png 132 × 128; 36 KB
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Freebsd-logo.png 178 × 175; 32 KB
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GFSK loopback example.png 990 × 481; 105 KB
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Git logo.png 155 × 80; 4 KB
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Gpredict 1 768w.jpg 768 × 656; 164 KB
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Grc xmit only.jpg 781 × 246; 39 KB
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IQ Corrector block control.png 1,186 × 708; 243 KB
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KiCAD footprints.png 700 × 478; 321 KB
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Kill Flow Graph Button GnuRadio.png 141 × 36; 4 KB
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LMS6002D-Baseband-Data-Interface.png 1,324 × 1,149; 121 KB
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LMS6002D-DQFN120-Package-Top-View.png 1,386 × 1,298; 153 KB
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LMS6002D-Digital-IQ-Interface-Supplies.png 1,146 × 1,196; 155 KB
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LMS6002D-Frame-Sync-Polarity-Interleave-Modes.png 2,262 × 1,210; 166 KB
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LMS6002D-Functional-Block-Diagram.png 3,149 × 2,425; 475 KB
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LMS6002D-LPF-Amplitude-Response-1.png 706 × 546; 34 KB
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LMS6002D-LPF-Amplitude-Response-2.png 706 × 546; 34 KB
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LMS6002D-PLL-Architecture.png 1,927 × 1,446; 106 KB
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LMS6002D-PLL-Reference-Clock-Input-Buffer-AC-Coupled.png 1,820 × 1,734; 95 KB
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LMS6002D-PLL-Reference-Clock-Input-Buffer-DC-Coupled.png 1,820 × 1,734; 95 KB
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LMS6002D-RX-Data-Interface-Signals.png 2,338 × 1,637; 151 KB
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LMS6002D-RX-Data-Interface.png 1,909 × 1,533; 192 KB
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LMS6002D-RX-Gain-Control-Architecture.png 1,581 × 602; 109 KB
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LMS6002D-SPI-Read-Cycle-3-Wire.png 4,916 × 909; 200 KB
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LMS6002D-SPI-Read-Cycle-4-Wire.png 4,927 × 1,271; 230 KB
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LMS6002D-SPI-Supplies.png 1,157 × 972; 115 KB
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LMS6002D-SPI-Write-Cycle.png 4,916 × 881; 189 KB
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LMS6002D-TX-Data-Interface.png 1,743 × 1,481; 190 KB
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LMS6002D-TX-Gain-Control-Architecture.png 1,575 × 550; 91 KB
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LMS6002D-TX-IQ-Interface-Signals.png 2,327 × 1,700; 150 KB
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LMS6002D-Typical-Application-Circuit-RF-Part.png 683 × 730; 41 KB
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LMS6002D FAQ Ramp Rate.png 639 × 397; 37 KB
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LMS6002D FAQ VCO Frequency Range.png 1,399 × 743; 29 KB
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LMS6002Dr2-DC-Offset-Calibration-LPF-Tuning-Module.png 427 × 650; 19 KB
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LMS6002Dr2-Envelop-Pick-Detector.png 1,868 × 2,699; 146 KB
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LMS6002Dr2-General-DC-Calibration.png 382 × 780; 20 KB
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LMS6002Dr2-IQ-Gain-Correction.png 223 × 184; 5 KB
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LMS6002Dr2-IQ-Phase-Correction.png 340 × 252; 7 KB
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LMS6002Dr2-LPF-Bandwidth-Tuning.png 521 × 620; 26 KB
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LMS6002Dr2-Loopback-Test.png 3,000 × 1,898; 539 KB
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LMS6002Dr2-PLL-Control.png 2,572 × 1,705; 201 KB
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LMS6002Dr2-RX-I-Q-DC-Level-Correction.png 265 × 207; 6 KB
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LMS6002Dr2-RXFE-Control.png 3,000 × 2,619; 590 KB
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LMS6002Dr2-RXVGA2-Control.png 2,517 × 1,696; 292 KB
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LMS6002Dr2-RXVGA2-DC-Offset-Calibration.png 793 × 627; 45 KB
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LMS6002Dr2-TXRF-Control.png 3,465 × 2,678; 444 KB
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LMS6002Dr2-TXRX-LPF-Control.png 1,390 × 1,110; 158 KB
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LMS6002Dr2-TXRX-LPF-DC-Offset-Calibration.png 424 × 760; 25 KB
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LMS6002Dr2-VCO-Capacitance-Selection.png 2,287 × 1,659; 178 KB
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LMS6002Dr2-VCO-VCOCAP-Code-Selection-Algorithm-General.png 401 × 535; 17 KB
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LMS6002Dr2-VCO-VCOCAP-Code-Selection-Algorithm-VCO-Selection.png 410 × 650; 20 KB
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LMS6002Dr2-VCO-VCOCAP-Code-Selection-Algorithm-VCOCAP-Selection.png 926 × 582; 39 KB
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LMS7002M-1024w.jpg 1,024 × 682; 95 KB
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LMS7002Mr3Cal Analog filter tuning.jpg 688 × 701; 39 KB
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LMS7002Mr3Cal Analog filter tuning.png 796 × 813; 30 KB
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LMS7002Mr3Cal RX spectral tones.jpg 688 × 701; 23 KB
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LMS7002Mr3Cal RX spectral tones.png 688 × 701; 12 KB
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LMS7002Mr3Cal TX spectral tones.jpg 688 × 701; 25 KB
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LMS7002Mr3Cal TX spectral tones.png 699 × 713; 14 KB
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LMS Suite FFTviewer.png 931 × 676; 74 KB
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LMS Suite LMS6002RxPLL.png 892 × 601; 76 KB
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LTE5MHz 6MHz.gif 1,020 × 767; 59 KB
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Lime-GPSDO Getting started Figure 1 Basic setup.png 3,587 × 911; 1.01 MB
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Lime-GPSDO Getting started Figure 2 Board status indication.png 2,074 × 879; 744 KB
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Lime-GPSDO Getting started Figure 4 VCOCXO tune state log.png 661 × 344; 16 KB
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Lime-GPSDO Getting started Figure 5 PPB vs Time, 1s measuring period.png 999 × 340; 112 KB
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Lime-GPSDO v1.0.png 2,120 × 1,411; 2.53 MB
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LimeMicrosystems 167x70.jpg 167 × 70; 5 KB
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LimeNET-Micro 2.1 Communication interfaces.png 3,500 × 1,968; 286 KB
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LimeNET-Micro 2.1 Development Board Block Diagram.png 3,000 × 2,879; 106 KB
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LimeNET-Micro 2.1 FAN control temperature hysteresis.png 1,730 × 835; 23 KB
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LimeNET-Micro 2.1 Fan connection to J8 header.png 4,420 × 2,085; 5.28 MB
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LimeNET-Micro 2.1 LMS7002M RF path.png 3,000 × 887; 44 KB
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LimeNET-Micro 2.1 Lime-GPSDO board clock distribution block diagram.png 3,500 × 2,027; 75 KB
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LimeNET-Micro 2.1 Power rail selection for pin 10 of J5 connector.png 827 × 620; 101 KB
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LimeNET-Micro 2.1 board power distribution block diagram.png 3,500 × 1,630; 64 KB
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LimeNET-Micro 2.1 internal USB subsystem.png 3,000 × 1,282; 276 KB
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LimeNET-Micro Bottom side components.png 3,500 × 1,942; 2.31 MB
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LimeNET-Micro SODIMM adapter Figure 2.png 969 × 383; 130 KB
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LimeNET-Micro SODIMM adapter Figure 3.png 765 × 233; 241 KB
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LimeNET-Micro SODIMM adapter Figure 4.jpg 5,005 × 3,753; 1.97 MB
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LimeNET-Micro top side components and connectors.png 3,500 × 2,208; 2.29 MB
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LimeNET-Micro v2.1 diagrams v05 LED indicators of RJ45 (J9) connector.png 8,835 × 2,345; 2.14 MB
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LimeNET-Micro v2.1 diagrams v05 USB2 Host.png 2,041 × 976; 847 KB
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LimeSDR-CORE SDR 1v1 schematic r0.PDF ; 5.41 MB
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LimeSDR-ExtIO CMake Configuration.png 624 × 501; 109 KB
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LimeSDR-ExtIO CMake configuration example.png 1,425 × 650; 79 KB
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LimeSDR-ExtIO HDSDR ExtIO button.png 505 × 367; 47 KB
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LimeSDR-ExtIO HDSDR RF gain slider.png 491 × 365; 45 KB
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LimeSDR-ExtIO HDSDR sampling rate settings.png 503 × 365; 45 KB
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LimeSDR-ExtIO Include directories paths.png 571 × 444; 18 KB
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LimeSDR-ExtIO Library directory paths.png 571 × 444; 24 KB
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LimeSDR-ExtIO Main dialog panel.png 445 × 298; 14 KB
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LimeSDR-ExtIO RX gain control architecture.png 800 × 301; 56 KB
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LimeSDR-ExtIO build configuration.png 457 × 106; 41 KB
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LimeSDR-ExtIO cmake configuration.png 693 × 649; 41 KB
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LimeSDR-FX3-Firmware-RAM.jpg 690 × 593; 163 KB
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LimeSDR-Micro v2.1 FPGA JTAG pinheaders.png 1,246 × 427; 79 KB
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LimeSDR-Micro v2.1 LED indicators of RJ45 (J9) connector.png 3,500 × 929; 339 KB
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LimeSDR-Micro v2.1 board.png 3,000 × 1,992; 6.26 MB
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LimeSDR-Mini FPGA JTAG adapter.png 3,776 × 2,494; 680 KB
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LimeSDR-Mini FPGA JTAG adapter (edge).jpg 3,777 × 2,494; 551 KB
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LimeSDR-Mini GNU Radio Tx Power, Gain v dBm.png 1,164 × 644; 175 KB
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LimeSDR-Mini GNU Radio Tx Power, dBm v MHz.png 1,146 × 746; 190 KB
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LimeSDR-Mini GNU Radio Tx Power Data.png 1,218 × 537; 79 KB
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LimeSDR-Mini JTAG apapter photo 1.jpg 3,840 × 1,936; 983 KB
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LimeSDR-Mini JTAG apapter photo 2.jpg 3,840 × 2,040; 1.23 MB
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LimeSDR-Mini JTAG apapter photo 3.jpg 3,840 × 2,576; 1.56 MB
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LimeSDR-Mini SDRangel Demo 768w.jpg 768 × 432; 89 KB
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LimeSDR-Mini drivers control panel.png 941 × 761; 272 KB
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LimeSDR-Mini drivers device manager.png 328 × 470; 41 KB
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LimeSDR-Mini drivers device manager update.png 381 × 473; 48 KB
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LimeSDR-Mini drivers device manager updated.png 670 × 580; 123 KB
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LimeSDR-Mini drivers finished.png 580 × 466; 56 KB
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LimeSDR-Mini drivers progress.png 555 × 444; 46 KB
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LimeSDR-Mini drivers search.png 787 × 577; 115 KB
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LimeSDR-Mini drivers security.png 785 × 311; 75 KB
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LimeSDR-Mini drivers start.png 574 × 769; 372 KB
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LimeSDR-Mini drivers update.png 624 × 456; 83 KB
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LimeSDR-Mini v1.1.png 1,612 × 696; 482 KB
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LimeSDR-Mini v1.1 LEDs.png 1,046 × 679; 636 KB
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LimeSDR-Mini v1.1 LSI.png 1,002 × 617; 57 KB
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LimeSDR-Mini v1.1 block.png 1,733 × 1,073; 69 KB
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LimeSDR-Mini v1.1 bot componens.png 1,181 × 595; 557 KB
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LimeSDR-Mini v1.1 clock.png 865 × 523; 29 KB
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LimeSDR-Mini v1.1 power.png 977 × 500; 29 KB
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LimeSDR-Mini v1.1 top componens.png 954 × 524; 293 KB
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LimeSDR-Mini v1.2.png 1,533 × 612; 449 KB
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LimeSDR-Mini v1.2 LEDs.png 1,712 × 1,145; 1.42 MB
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LimeSDR-Mini v1.2 LSI.png 2,505 × 1,545; 164 KB
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LimeSDR-Mini v1.2 PN 1000.png 1,032 × 776; 94 KB
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LimeSDR-Mini v1.2 PN 2140.png 1,032 × 776; 94 KB
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LimeSDR-Mini v1.2 PN 2665.png 1,032 × 776; 92 KB
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LimeSDR-Mini v1.2 PN 300.png 1,032 × 776; 94 KB
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LimeSDR-Mini v1.2 block.png 1,733 × 1,073; 69 KB
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LimeSDR-Mini v1.2 bot componens.png 1,905 × 962; 1.14 MB
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LimeSDR-Mini v1.2 clock.png 2,165 × 1,308; 96 KB
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LimeSDR-Mini v1.2 power.png 2,735 × 1,343; 115 KB
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LimeSDR-Mini v1.2 top componens.png 2,385 × 1,345; 1.25 MB
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LimeSDR-PCIe FPGA adding files.png 624 × 412; 142 KB
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LimeSDR-PCIe FPGA adding prog file.png 479 × 305; 39 KB
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LimeSDR-PCIe FPGA core generation.png 624 × 632; 102 KB
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LimeSDR-PCIe FPGA create IP core.png 624 × 399; 45 KB
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LimeSDR-PCIe FPGA download status.png 624 × 401; 35 KB
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LimeSDR-PCIe FPGA file editing.png 624 × 624; 95 KB
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LimeSDR-PCIe FPGA project compilation.png 624 × 173; 42 KB