User contributions for Ghalfacree
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2 June 2016
- 21:1421:14, 2 June 2016 diff hist +48 N File:Lms7002m-calibration-digital-filtering-step-c.png LMS7002M calibration, digital filtering step (c) current
- 21:1021:10, 2 June 2016 diff hist +48 N File:Lms7002m-calibration-digital-filtering-step-b.png LMS7002M calibration, digital filtering step (b) current
- 21:1021:10, 2 June 2016 diff hist +48 N File:Lms7002m-calibration-digital-filtering-step-a.png LMS7002M calibration, digital filtering step (a) current
- 21:0321:03, 2 June 2016 diff hist +57 N File:Lms7002m-calibration-iq-imbalance-spectral-tones.png LMS7002M calibration, IQ imbalance spectral tones example current
- 20:4820:48, 2 June 2016 diff hist +38 N File:Lms7002m-calibration-pass-band.png LMS7002M calibration, pass-band tuning current
- 20:4020:40, 2 June 2016 diff hist +28 N File:Lms7002m-calibration-vcocap.png LMS7002M calibration, VCOCAP current
- 20:3020:30, 2 June 2016 diff hist +33 N File:Lms7002m-clock-generation.png LMS7002M clock generation diagram current
- 20:2320:23, 2 June 2016 diff hist +51 N File:Lms7002m-mcu-connections.png LMS7002M on-chip microcontroller connection diagram current
- 20:2120:21, 2 June 2016 diff hist +29 N File:Lms7002m-spi-supplies.png LMS7002M SPI supplies diagram current
- 20:0720:07, 2 June 2016 diff hist +46 N File:Lms7002m-spi-read-cycle-3-wire-timing.png LMS7002M SPI read cycle, 3-wire timing diagram current
- 20:0720:07, 2 June 2016 diff hist +48 N File:Lms7002m-spi-read-cycle-4-wire-timing.png LMS7002M SPI read cycle, 4-wire (default) timing current
- 20:0620:06, 2 June 2016 diff hist +39 N File:Lms7002m-spi-write-cycle-timing.png LMS7002M SPI write cycle timing diagram current
- 17:2717:27, 2 June 2016 diff hist +47 N File:Lms7002m-digital-iq-interface-supplies.png LMS7002M digital IQ interface supplies diagram. current
- 17:2317:23, 2 June 2016 diff hist +68 N File:Lms7002m-limelight-trxiq-sdr-transmit-data-path.png LMS7002M LimeLight TRXIQ SDR mode transmit data path timing diagram. current
- 17:2217:22, 2 June 2016 diff hist +67 N File:Lms7002m-limelight-trxiq-sdr-receive-data-path.png LMS7002M LimeLight TRXIQ SDR mode receive data path timing diagram. current
- 17:2217:22, 2 June 2016 diff hist +68 N File:Lms7002m-limelight-trxiq-ddr-transmit-data-path.png LMS7002M LimeLight TRXIQ DDR mode transmit data path timing diagram. current
- 17:2117:21, 2 June 2016 diff hist +67 N File:Lms7002m-limelight-trxiq-ddr-receive-data-path.png LMS7002M LimeLight TRXIQ DDR mode receive data path timing diagram. current
- 17:2017:20, 2 June 2016 diff hist +68 N File:Lms7002m-limelight-jesd207-receive-burst-finish.png LMS7002M LimeLight JESD207 mode receive burst finish timing diagram. current
- 17:1917:19, 2 June 2016 diff hist +67 N File:Lms7002m-limelight-jesd207-receive-burst-start.png LMS7002M LimeLight JESD207 mode receive burst start timing diagram. current
- 17:1817:18, 2 June 2016 diff hist +69 N File:Lms7002m-limelight-jesd207-transmit-burst-finish.png LMS7002M LimeLight JESD207 mode transmit burst finish timing diagram. current