Uploads by Ghalfacree
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This special page shows all uploaded files.
| Date | Name | Thumbnail | Size | Description | Versions |
|---|---|---|---|---|---|
| 14:53, 6 October 2015 | LMS6002Dr2-VCO-VCOCAP-Code-Selection-Algorithm-General.png (file) |  |
17 KB | Clearer image. | 2 |
| 14:52, 6 October 2015 | LMS6002Dr2-LPF-Bandwidth-Tuning.png (file) |  |
26 KB | Clearer image. | 2 |
| 14:52, 6 October 2015 | LMS6002Dr2-RXVGA2-DC-Offset-Calibration.png (file) |  |
45 KB | Clearer image. | 2 |
| 14:52, 6 October 2015 | LMS6002Dr2-TXRX-LPF-DC-Offset-Calibration.png (file) |  |
25 KB | Clearer image. | 2 |
| 14:51, 6 October 2015 | LMS6002Dr2-DC-Offset-Calibration-LPF-Tuning-Module.png (file) |  |
19 KB | Higher resolution version. | 2 |
| 14:41, 6 October 2015 | LMS6002Dr2-RXFE-Control.png (file) |  |
590 KB | Higher resolution copy, attempt two. | 3 |
| 14:39, 6 October 2015 | LMS6002Dr2-RXVGA2-Control.png (file) |  |
292 KB | Higher resolution copy. | 2 |
| 14:38, 6 October 2015 | LMS6002Dr2-TXRF-Control.png (file) |  |
444 KB | Higher resolution copy. | 2 |
| 14:38, 6 October 2015 | LMS6002Dr2-TXRX-LPF-Control.png (file) |  |
158 KB | Higher resolution copy. | 2 |
| 14:37, 6 October 2015 | LMS6002Dr2-PLL-Control.png (file) |  |
201 KB | Higher resolution copy. | 2 |
| 14:36, 6 October 2015 | LMS6002Dr2-VCO-Capacitance-Selection.png (file) |  |
178 KB | Higher resolution copy. | 5 |
| 14:36, 6 October 2015 | LMS6002Dr2-Envelop-Pick-Detector.png (file) |  |
146 KB | Higher resolution copy. | 2 |
| 14:35, 6 October 2015 | LMS6002Dr2-Loopback-Test.png (file) |  |
539 KB | Higher resolution copy - attempt three. | 6 |
| 10:05, 1 October 2015 | LMS6002D-Typical-Application-Circuit-RF-Part.png (file) |  |
41 KB | Higher-resolution version. | 2 |
| 10:05, 1 October 2015 | LMS6002D-DQFN120-Package-Top-View.png (file) |  |
153 KB | Higher-resolution version. | 2 |
| 10:05, 1 October 2015 | LMS6002D-SPI-Supplies.png (file) |  |
115 KB | Higher-resolution version. | 2 |
| 10:04, 1 October 2015 | LMS6002D-Digital-IQ-Interface-Supplies.png (file) |  |
155 KB | Higher-resolution version. | 2 |
| 10:04, 1 October 2015 | LMS6002D-RX-Data-Interface-Signals.png (file) |  |
151 KB | Higher-resolution version. | 2 |
| 10:03, 1 October 2015 | LMS6002D-RX-Data-Interface.png (file) |  |
192 KB | Higher-resolution version. | 2 |
| 10:03, 1 October 2015 | LMS6002D-TX-IQ-Interface-Signals.png (file) |  |
150 KB | Higher-resolution version. | 2 |
| 10:03, 1 October 2015 | LMS6002D-TX-Data-Interface.png (file) |  |
190 KB | Higher-resolution version. | 2 |
| 10:02, 1 October 2015 | LMS6002D-Frame-Sync-Polarity-Interleave-Modes.png (file) |  |
166 KB | Higher-resolution version. | 2 |
| 10:02, 1 October 2015 | LMS6002D-Baseband-Data-Interface.png (file) |  |
121 KB | Higher-resolution version. | 2 |
| 10:01, 1 October 2015 | LMS6002D-LPF-Amplitude-Response-2.png (file) |  |
34 KB | Higher-resolution version. | 2 |
| 10:01, 1 October 2015 | LMS6002D-LPF-Amplitude-Response-1.png (file) |  |
34 KB | Higher-resolution version. | 2 |
| 10:01, 1 October 2015 | LMS6002D-PLL-Reference-Clock-Input-Buffer-AC-Coupled.png (file) |  |
95 KB | Higher-resolution version. | 2 |
| 10:00, 1 October 2015 | LMS6002D-PLL-Reference-Clock-Input-Buffer-DC-Coupled.png (file) |  |
95 KB | Higher-resolution version. | 2 |
| 10:00, 1 October 2015 | LMS6002D-PLL-Architecture.png (file) |  |
106 KB | Higher-resolution version. | 2 |
| 09:59, 1 October 2015 | LMS6002D-RX-Gain-Control-Architecture.png (file) |  |
109 KB | Higher-resolution version. | 2 |
| 09:59, 1 October 2015 | LMS6002D-TX-Gain-Control-Architecture.png (file) |  |
91 KB | Higher-resolution version. | 2 |
| 09:59, 1 October 2015 | LMS6002D-Functional-Block-Diagram.png (file) |  |
475 KB | Higher-resolution version. | 2 |
| 09:57, 1 October 2015 | LMS6002D-SPI-Read-Cycle-3-Wire.png (file) |  |
200 KB | Higher-resolution version. | 2 |
| 09:56, 1 October 2015 | LMS6002D-SPI-Read-Cycle-4-Wire.png (file) |  |
230 KB | Higher-resolution version. | 4 |
| 09:54, 1 October 2015 | LMS6002D-SPI-Write-Cycle.png (file) |  |
189 KB | Higher-resolution version. | 2 |
| 17:20, 22 July 2015 | Myriad-RF-IF-Block-Diagram.png (file) |  |
148 KB | STREAM Board Myriad-RF Interface Block Diagram. | 1 |
| 16:58, 22 July 2015 | STREAM-OpenRISC-Block-Diagram.png (file) |  |
67 KB | Block diagram for the STREAM OpenRISC project. | 1 |
| 16:29, 22 July 2015 | STREAM-Board-GPIF-II.jpg (file) |  |
20 KB | STREAM Board GPIF II-related connections between FX3 and FPGA. | 1 |
| 15:35, 22 July 2015 | STREAM-Schematics-15.png (file) |  |
721 KB | STREAM Schematics Page 15, FPGA Banks 1-4. | 1 |
| 15:34, 22 July 2015 | STREAM-Schematics-14.png (file) |  |
467 KB | STREAM Schematics Page 14, FMC and Myriad-RF Connectors. | 1 |
| 15:34, 22 July 2015 | STREAM-Schematics-13.png (file) |  |
318 KB | STREAM Schematics Page 13, FPGA Power Distribution. | 1 |
| 15:33, 22 July 2015 | STREAM-Schematics-12.png (file) |  |
205 KB | STREAM Schematics Page 12, Clocks Block Diagram. | 1 |
| 15:33, 22 July 2015 | STREAM-Schematics-11.png (file) |  |
350 KB | STREAM Schematics Page 11, Board Power Supply 2. | 1 |
| 15:32, 22 July 2015 | STREAM-Schematics-10.png (file) |  |
264 KB | STREAM Schematics Page 10, Board Power Supply 1. | 1 |
| 15:32, 22 July 2015 | STREAM-Schematics-9.png (file) |  |
237 KB | STREAM Schematics Page 9, USB 3.0 Power Supply. | 1 |
| 15:31, 22 July 2015 | STREAM-Schematics-8.png (file) |  |
248 KB | STREAM Schematics Page 8, Clocks. | 1 |
| 15:31, 22 July 2015 | STREAM-Schematics-7.png (file) |  |
402 KB | STREAM Schematics Page 7, Ethernet. | 1 |
| 15:30, 22 July 2015 | STREAM-Schematics-6.png (file) |  |
436 KB | STREAM Schematics Page 6, Peripherals. | 1 |
| 15:29, 22 July 2015 | STREAM-Schematics-5.png (file) |  |
296 KB | STREAM Schematics Page 5, USB 2.0 Host. | 1 |
| 15:29, 22 July 2015 | STREAM-Schematics-4.png (file) |  |
613 KB | STREAM Schematics Page 4, USB 3.0 Device (FX3). | 1 |
| 15:28, 22 July 2015 | STREAM-Schematics-3.png (file) |  |
571 KB | STREAM Schematics Page 3, SDRAM. | 1 |
