LimeSDR-PCIe v1.2 hardware description
Draft
Introduction
LimeSDR-PCIe is low-cost software defined radio board based on Lime LMS7002M Field Programmable Radio Frequency (FPRF) transceiver and Altera Cyclone IV GX PFGA, through which apps can be programmed to support any type of wireless standard, e.g. UMTS, LTE, LoRa, GPS, WiFi, Zigbee, RFID, Digital Broadcasting, Radar and many more.
Complete Development Kit Package
The LimeSDR-PCIe v1.2 board from full package showed in Figure 1.
Development kit content:
- LimeSDR-PCIe v1.2 board
- USB stick containing following files:
- Doc/ - Documentation files for LimeSDR-PCIe
- Drivers/ - Windows drivers for LimeSDR-PCIe
- Gateware/ - FPGA gateware related files for LimeSDR-PCIe v1.2
- Gui/ - LimeSuiteGUI software and related files
LimeSDR-PCIe Board Key Features
The LimeSDR-PCIe development board provides a hardware platform for developing and prototyping high-performance and logic-intensive digital and RF designs using Altera’s Cyclone IV GX FPGA and Lime Microsystems transceiver.
LimeSDR-PCIe board features:
- RF transceiver:
- Lime Microsystems LMS7002M
- FPGA Features
- Cyclone IV GX (EP4CGX30CF23C7N) device in 484-pin FBGA
- 29’440 logic elements
- 1080 Kbits embedded memory
- 80 embedded 18x18 multipliers
- 4 general and 2 multipurpose PLLs
- 4 high-speed transceivers
- PCIe (PIPE) hard IP block
- FPGA Configuration
- JTAG mode configuration
- Active serial mode configuration
- Possibility to update FPGA gateware by using PCIe interface
- Memory Devices
- 2x 1Gbit (64M x 16) dual channel DDR2 SDRAM
- 4Mbit flash for FPGA data
- 64Mbit flash for FPGA gateware
- 128Kb (16K x 8) EEPROM for LMS MCU firmware and 512Kb (64K x 8) LMS MCU data
- Connections
- PCI Express x4 (4 lanes)
- Coaxial RF (U.FL) connectors
- FPGA GPIO 2x8 (3.3V) headers
- FPGA and JTAG connector
- DC (12V) power jack and pinheader
- FAN (12V) connector
- Clock System
- 30.72MHz ±250 ppb onboard VCTCXO
- Possibility to lock VCTCXO to external clock or tune VCTCXO by onboard DAC
- Programmable clock generator for the FPGA reference clock input or LMS PLLs
- 100 MHz and 2x 50MHz crystal oscillators for FPGA
- Board Size 68,9mm x 136,85mm
For more information on the following topics, refer to the respective documents:
- Cyclone IV device family, refer to Cyclone IV Device Handbook [link]
- LMS7002M transceiver resources [link
LimeSDR-PCIe board overview
LimeSDR-PCIe board version 1.2 picture with highlighted major connections and components presented in Figure 1 and Figure 2. There are three connector types – data and debugging (PCIe, FPGA GPIO and JTAG), power (DC jack - optional) and high frequency (RF and reference clock). LimeSDR-PCIe board version 1.2 picture with highlighted components on top presented in Figure 1.
LimeSDR-PCIe board version 1.2 picture with highlighted components on bottom presented in Figure 2
Board components description listed in the Table 1.
| Featured Devices | ||
|---|---|---|
| Board reference | Type | Description |
| IC1 | FPRF | Field programmable RF transceiver LMS7002M |
| IC8 | FPGA | Altera Cyclone IV GX (EP4CGX30CF23C7N) device in 484-pin FBGA |
| Miscellaneous devices onboard | ||
| IC14 | IC | Temperature sensor LM75 |
| IC4, IC5, IC6, IC7 | IC | SPDT Switch |
| Configuration, Status and Setup Elements | ||
| J11 | JTAG chain pinheader | FPGA programming pinheader for Altera USB-Blaster download cable, 0.1” pitch |
| LEDS1 or LED1, LED4 | Red-green status LEDs | User defined FPGA indication dual colour (red – green) LEDs. LEDS1 if two TH LEDs with standoff or two SMD LEDs are populated. |
| LED5-LED8 | Green status LEDs | User defined FPGA indication green LEDs (LED3-LED6). |
| LED9 | Green status LEDs | Power indication |
| General User Input/Output | ||
| J12, J13 | Pinheader | 8 + 8 FPGA GPIOs, 0.05” pitch |
| J14 | Pinheader | 12V fan connection pinheader, 0.1” pitch |
| J18 | Pinheader | 12V internal power rail. Can be used to power external devices. |
| SW1 | Switch | 4 pole switch |
| Memory Devices | ||
| Board Reference | Type | Description |
| IC11, IC12 | DDR2 memory | 1Gbit (64M x 16) DDR2 SDRAM with a 16-bit data bus |
| IC2, IC3 | EEPROM | 128K (16K x 8) and 512K (64K x 8) EEPROMs for LMS7002 MCU firmware and data |
| IC15 | EEPROM | 128K (16K x 8) EEPROM for FPGA data |
| IC9, IC10 | Flash memory | 64Mbit Flash for FPGA configuration (only one is soldered). |
| Communication Ports | ||
| P1 | PCIe connector | PCI Express x4 connector |
| Clock Circuitry | ||
| XO1, XO2 | VCTCXO | Voltage Controlled, Temperature Compensated Crystal Oscillator (30.72MHz, only one is soldered). |
| IC20 | IC | Programmable clock generator (Si5351C) for the FPGA reference clock input and RF boards |
| IC19 | IC | Phase detector (ADF4002) |
| J15 | U.FL connector | RF connector for reference clock output |
| J16 | U.FL connector | RF connector for external reference clock input |
| IC18 | IC | DAC for TCXO (XO1 or XO2) frequency tuning |
| Power Supply | ||
| J17 | DC input jack | External 12V DC power supply (Optional) |
| J18 | Pinheader | External 12V DC power supply and internal main power rail |
LMS7002M based connectivity
All LMS7002M RF transceiver signals are connected to FPGA Bank 8 (power rail: VDIO_LMS_FPGA; voltage: 2.5V-default or 3.3V). The interface and control signals are described below:
- Digital Interface Signals: LMS7002 is using data bus LMS_DIQ1_D[11:0] and LMS_DIQ2_D[11:0], LMS_ENABLE_IQSEL1 and LMS_ENABLE_IQSEL2, LMS_FCLK1 and LMS_FCLK2, LMS_MCLK1 and LMS_MCLK2 signals to transfer data to/from FPGA. Indexes 1 and 2 indicate transceiver digital data PORT-1 or PORT-2. Any of these ports can be used to transmit or receive data. By default PORT-1 is selected as transmit port and PORT-2 is selected as receiver port. The FCLK# is input clock and MCLK# is output clock for LMS7002M transceiver. TXNRX signals sets ports directions. For LMS7002M interface timing details refer to LMS7002M transceiver datasheet page 12-13. [link].
- SPI Interface: LMS7002M transceiver is configured via 4-wire SPI interface; FPGA_SPI0_SCLK, FPGA_SPI0_MOSI, FPGA_SPI0_MISO, FPGA_SPI0_LMS_SS.
- I2C Interface: used access EEPROM memories for LMS7002M MCU firmware and data. I2C interface is using LMS_I2C_SCL, LMS_I2C_SDA signals.
- Control Signals: these signals are used for optional functionality:
- LMS_RXEN, LMS_TXEN – receiver and transmitter enable/disable signals.
- LMS_RESET – LMS7002M reset.
| Chip pin (IC1) | Chip reference (IC1) | Schematic signal name | FPGA pin | FPGA I/O standard | Comment |
|---|---|---|---|---|---|
| AM24 | xoscin_rx | RxPLL_CLK | - | 2.5V (3.3V) | Connected to 30.72 MHz clock |
| E5 | xoscin_tx | TxPLL_CLK | - | 2.5V (3.3V) | Connected to 30.72 MHz clock |
| E27 | RESET | LMS_RESET | A1 | 2.5V (3.3V) | |
| U29 | TXEN | LMS_TXEN | A7 | 2.5V (3.3V) | |
| D28 | SEN | FPGA_SPI0_LMS_SS | B1 | 2.5V (3.3V) | SPI interface |
| C29 | SCLK | FPGA_SPI0_SCLK | B3 | 2.5V (3.3V) | SPI interface |
| F30 | SDIO | FPGA_SPI0_MOSI | C1 | 2.5V (3.3V) | SPI interface |
| F28 | SDO | FPGA_SPI0_MISO | A3 | 2.5V (3.3V) | SPI interface |
| D26 | SDA | LMS_I2C_SDA | A2 (via R46) | 2.5V (3.3V) | Connected to EEPROMS |
| C27 | SCL | LMS_I2C_SCL | G11 (via R51) | 2.5V (3.3V) | Connected to EEPROMS |
| AB34 | MCLK1 | LMS_MCLK1 | K10 | 2.5V (3.3V) | |
| AA33 | FCLK1 | LMS_FCLK1 | H9 | 2.5V (3.3V) | |
| V32 | TXNRX1 | LMS_TXNRX1 | C3 | 2.5V (3.3V) | |
| V34 | RXEN | LMS_RXEN | C2 | 2.5V (3.3V) | |
| Y32 | ENABLE_IQSEL1 | LMS_ENABLE_IQSEL1 | D6 | 2.5V (3.3V) | |
| AG31 | DIQ1_D0 | LMS_DIQ1_D0 | D9 | 2.5V (3.3V) | |
| AF30 | DIQ1_D1 | LMS_DIQ1_D1 | B7 | 2.5V (3.3V) | |
| AF34 | DIQ1_D2 | LMS_DIQ1_D2 | H8 | 2.5V (3.3V) | |
| AE31 | DIQ1_D3 | LMS_DIQ1_D3 | C8 | 2.5V (3.3V) | |
| AD30 | DIQ1_D4 | LMS_DIQ1_D4 | C7 | 2.5V (3.3V) | |
| AC29 | DIQ1_D5 | LMS_DIQ1_D5 | C9 | 2.5V (3.3V) | |
| AE33 | DIQ1_D6 | LMS_DIQ1_D6 | H7 | 2.5V (3.3V) | |
| AD32 | DIQ1_D7 | LMS_DIQ1_D7 | G8 | 2.5V (3.3V) | |
| AC31 | DIQ1_D8 | LMS_DIQ1_D8 | E8 | 2.5V (3.3V) | |
| AC33 | DIQ1_D9 | LMS_DIQ1_D9 | G7 | 2.5V (3.3V) | |
| AB30 | DIQ1_D10 | LMS_DIQ1_D10 | F8 | 2.5V (3.3V) | |
| AB32 | DIQ1_D11 | LMS_DIQ1_D11 | E6 | 2.5V (3.3V) | |
| U33 | CORE_LDO_EN | LMS_CORE_LDO_EN | C4 | 2.5V (3.3V) | |
| P34 | MCLK2 | LMS_MCLK2 | M8 | 2.5V (3.3V) | |
| R29 | FCLK2 | LMS_FCLK2 | C5 | 2.5V (3.3V) | |
| U31 | TXNRX2 | LMS_TXNRX2 | A4 | 2.5V (3.3V) | |
| R33 | ENABLE_IQSEL2 | LMS_ENABLE_IQSEL2 | B6 | 2.5V (3.3V) | |
| H30 | DIQ2_D0 | LMS_DIQ2_D0 | G6 | 2.5V (3.3V) | |
| J31 | DIQ2_D1 | LMS_DIQ2_D1 | E5 | 2.5V (3.3V) | |
| K30 | DIQ2_D2 | LMS_DIQ2_D2 | A8 | 2.5V (3.3V) | |
| K32 | DIQ2_D3 | LMS_DIQ2_D3 | D7 | 2.5V (3.3V) | |
| L31 | DIQ2_D4 | LMS_DIQ2_D4 | D8 | 2.5V (3.3V) | |
| K34 | DIQ2_D5 | LMS_DIQ2_D5 | F6 | 2.5V (3.3V) | |
| M30 | DIQ2_D6 | LMS_DIQ2_D6 | C6 | 2.5V (3.3V) | |
| M32 | DIQ2_D7 | LMS_DIQ2_D7 | D4 | 2.5V (3.3V) | |
| N31 | DIQ2_D8 | LMS_DIQ2_D8 | A5 | 2.5V (3.3V) | |
| N33 | DIQ2_D9 | LMS_DIQ2_D9 | D5 | 2.5V (3.3V) | |
| P30 | DIQ2_D10 | LMS_DIQ2_D10 | B4 | 2.5V (3.3V) | |
| P32 | DIQ2_D11 | LMS_DIQ2_D11 | A6 | 2.5V (3.3V) |
PCI Express connector
For data transfer LimeSDR–PCIe board has PCI express connector with four lanes. PCI express interface is implemented in FPGA. Pin connection and corresponding signal names are listed in Table 4.
| Connector pin | Schematic signal name | FPGA pin | I/O standard | Comment |
|---|---|---|---|---|
| B5 | PCIE_SMCLK | A10 | 3.3V | |
| B6 | PCIE_SMDAT | B10 | 3.3V | |
| B11 | PCIE_WAKEn | G12 | 3.3V | Signal is disconnected with not fitted R100 resistor |
| B14 | PCIE_HSO0_P | Y2 | 1.5-V PCML | |
| B15 | PCIE_HSO0_N | Y1 | 1.5-V PCML | |
| B19 | PCIE_HSO1_P | T2 | 1.5-V PCML | |
| B20 | PCIE_HSO1_N | T1 | 1.5-V PCML | |
| B23 | PCIE_HSO2_P | M2 | 1.5-V PCML | |
| B24 | PCIE_HSO2_N | M1 | 1.5-V PCML | |
| B27 | PCIE_HSO3_P | H2 | 1.5-V PCML | |
| B28 | PCIE_HSO3_N | H1 | 1.5-V PCML | |
| A11 | PCIE_PERSTn | H12 | 3.3V | |
| A13 | PCIE_REFCLK_P | M11 | HCSL | |
| A14 | PCIE_REFCLK_N | N11 | HCSL | |
| A16 | PCIE_HSI0_P | V2 | 1.5-V PCML | AC coupled |
| A17 | PCIE_HSI0_N | V1 | 1.5-V PCML | AC coupled |
| A21 | PCIE_HSI1_P | P2 | 1.5-V PCML | AC coupled |
| A22 | PCIE_HSI1_N | P1 | 1.5-V PCML | AC coupled |
| A25 | PCIE_HSI2_P | K2 | 1.5-V PCML | AC coupled |
| A26 | PCIE_HSI2_N | K1 | 1.5-V PCML | AC coupled |
| A29 | PCIE_HSI3_P | F2 | 1.5-V PCML | AC coupled |
| A30 | PCIE_HSI3_N | F1 | 1.5-V PCML | AC coupled |
SDRAM
LimeSDR-PCIe board has two 128MB (16bit bus) DDR2 SDRAM ICs (AS4C64M16D2-25BCN [link]) connected to double data rate pins on Cyclone IV GX 1.8V Bank 3, 4 and 5. RAM chips (IC11, IC12) are connected to separate memory controllers so RAM chips works in dual channel mode. The memory can be used for data manipulation at high data rates between transceiver and FPGA. Pin connection and corresponding signal names are listed in Table 5 and Table 6.
TBD
Low speed interfaces
LimeSDR-PCIe board low speed interfaces is presented in Figure 4. More detailed information is provided in the following sections.
Figure 4 low speed interfaces block diagram
Indication LEDs
LimeSDR-PCIe board comes with 6 indication LEDs which can be controlled from FPGA. By default, two of them (FPGA_LED1 and FPGA_LED2) are trough-hole dual colour LEDs and are mounted on the back edge of the board using right-angle plastic holder. The remaining four LEDs (FPGA_LED3 to FPGA_LED6) are SMD single green colour LEDs. There is one SMD single green colour LED named VDD3P3_PWR which is hardwired to VCC3P3 power rail and lit up whenever the board is powered on.
TBD
SPI interfaces
LimeSDR-PCIe board has four SPI interfaces with their own slave devices:
- Flash for FPGA gateware: Flash memory (IC9 or IC10) is used to store FPGA gateware.
I2C interfaces
Board has two independent I2C interfaces: FPGA_I2C and LMS_I2C.
- FPGA_I2C: this interface has several slave devices temperature sensor, EEPROM and clock generator. Information for slave devices are provided in Table 12, signal connectivity information is in Table 13.
FPGA Switch
4 poles slide switch SW1 is connected to FPGA. Each switch line has external pull up resistors. When switch is in position “On”, it pulls down the line.
RF loopback control
LimeSDR-PCIe v1.2 board contains RF loopback switches (IC4, IC5, IC6, IC7) for LMS7002M which are controlled from FPGA. By using loopback switches RF path TX1_2 can be connected to RX1_H and TX2_2 to RX2_H.
FPGA GPIO connectors
There are J12 and J13 connectors (pinheaders) there 8 + 8 FPGA GPIOs are connected (3.3V IO compatible) with GND and power pins (3.3V). In Table 18 are listed connector J12 pins and in Table 19 are listed connector J13 pins, corresponding FPGA pins and other information.
Board temperature control
LimeSDR-PCIe has integrated temperature sensor which can control FAN to keep board in operating temperature range. FAN must be connected to J14 (0.1” pitch) connector. FAN control voltage is 12V. Fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C. FAN control temperature range is set by FPGA.
Clock Distribution
LimeSDR-PCIe board clock distribution block diagram is presented in Figure 8.
Power Distribution
LimeSDR-PCIe board power distribution block diagram is presented in Figure 9.