LimeSDR-QPCIe v1.2 hardware description: Difference between revisions
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Revision as of 07:28, 1 August 2018
Introduction
LimeSDR-QPCIe is low-cost software defined radio board based on Lime LMS7002M Field Programmable Radio Frequency (FPRF) transceiver and Altera Cyclone V PFGA, through which apps can be programmed to support any type of wireless standard, e.g. UMTS, LTE, LoRa, GPS, WiFi, Zigbee, RFID, Digital Broadcastimng, Radar and many more.
LimeSDR-QPCIe Board Key Features
The LimeSDR-QPCIe development board provides a hardware platform for developing and prototyping high-performance and logic-intensive digital and RF designs using Altera’s Cyclone V FPGA and Lime Microsystems transceiver.
For more information on the following topics, refer to the respective documents:
- Cyclone V device family, refer to Cyclone V Device support resources link
- LMS7002M transceiver resources link
LimeSDR-QPCIe v1.2 board features:
- USB Interface
- Cypress FX3 Super Speed USB 3rd generation controller
- FPGA Features
- Cyclone V, 5CGXFC7D7F31C8N device in 896-pin FBGA package
- 150’000 logic elements
- 6860 Kbits embedded memory
- 312 embedded 18x18 multipliers
- 7 PLLs
- 9 Transceivers (2.5Gbps)
- PCIe Hard IP Blocks
- 2 Hard Memory Controllers
- FPGA Configuration
- JTAG mode configuration
- Active serial mode configuration
- Possibility to update FPGA gateware by using FX3 (USB)
- Possibility to update FPGA gateware by using PCIe interface.
- RF
- 2x LMS7002M, FPRF transceivers
- Onboard RSSI measurement circuits
- Onboard loopback control switches
- DACs and ADCs
- 2x DAC5672A, dual, 14-bit, Digital-To-Analog converters
- 1x ADS424, Dual-Channel, 14-bit, Analog-To-Digital converter
- Memory Devices
- 4 x 2Gbit DDR3 SDRAM (128M x 16)
- 4Mbit flash for FX3 firmware
- 128Mbit flash for FPGA gateware
- 2 x 128Kbit and 2 x 512Kbit EEPROMs for LMS MCU firmware, LMS MCU data
- 1 x 128K EEPROM for FX3 or FPGA data
- Connections
- microUSB3.0 (type B) connector
- PCIe x4 edge connector (Gen1)
- Coaxial RF (U.FL) connectors
- 2x PMOD header (0.1” pitch)
- FPGA (0.1” pitch) and FX3 (0.05” pitch) JTAG connectors
- 12V DC power jack and pinheader
- LVDS connector (0.05” pitch)
- Fan connector (12V/5V)
- PCIe 6-pin power connector
- Holder for coin cell CR1220 battery
- Clock System
- 30.72MHz VCTCXO (precision: ±1 ppm initial, ±4 ppm stable).
- Possibility to lock VCTCXO to external clock using ADF4002 or tune VCTCXO by onboard DAC (AD5662)
- Programmable clock generator for the FPGA reference clock input or LMS PLLs
- VCTCXO clock output for external device synchronization.
- 1x 100 MHz, 4 x 125MHz crystal oscillators for FPGA
- Miscellaneous devices
- LM75 Digital temperature sensor with 2-Wire Interface.
- DS3231 real-time clock.
- M0578-A3 GPS/GNSS module receiver
- Board Size 190mm x 106.7mm (7.48” x 4.20”)
LimeSDR-QPCIe Board Overview
LimeSDR-QPCIe board version 1.2 picture with highlighted major connectors presented in Figure 2. There are three connector types – data and debugging (PCIe, USB3.0, PMOD, LVDS and JTAG), power (DC jack and external supply pinheaders) and high frequency (RF and reference clock).
Board components description listed in the Table 1.
| Featured Devices | ||
|---|---|---|
| Board Reference | Type | Description |
| IC1, IC2 | FPRF | Field programmable RF transceivers LMS7002M |
| IC8 | FPGA | Altera Cyclone V GX, 5CGXFC7D7F31C8N, 896-BGA |
| IC13 | USB3.0 microcontroller | Cypress FX3 Supper Speed USB 3rd generation controller CYUSB3013 |
| Miscellaneous devices on board | ||
| IC7, IC8 | IC | 8-bit shift registers 74HC595BQ,115 |
| IC9, IC49 | IC | Bidirectional voltage shifters SN74AVC4T774RSVR |
| IC10, IC11, IC12, IC13, IC14, IC15, IC16, IC17 | IC | 100MHz – 3 GHz SPDT RF switches SKY13323-378LF |
| IC18, IC20, IC23, IC25, IC26, IC28 | IC | 12-bit ADCs MAX11108AVB+T |
| IC19, IC24, IC27 | IC | 1MHz–10GHz dual log detector/controller ADL5519 |
| IC22 | IC | SP4T RF switch PE42442A-Z |
| IC31 | IC | 4 parallel 2:1 switches TS3A5018PWR |
| IC37 | IC | 14-bit 2-channel ADC ADS4246IRGCT |
| IC38 | IC | Dual differential amplifier ADA4930 |
| IC39, IC56 | IC | Differential line drivers SN65LVDS1DBVR |
| IC40, IC41 | IC | Dual differential DACs DAC5672AIPFB |
| IC44, IC45 | IC | Bidirectional 8-channel voltage translators FXLA108BQX |
| IC47 | IC | Temperature sensor LM75 |
| IC48 | IC | GPS receiver module M10578-A3 |
| IC50 | IC | Real time clock (RTC) DS3231S# |
| BATT1 | Holder | Holder for coin cell CR1220 battery |
| ESD26 | TVS | USB3.0 ESD protection TVS diode |
| ESD1, ESD2, ESD3, ESD4, ESD5, ESD6, ESD7, ESD8, ESD9, ESD10, ESD11, ESD12, ESD13, ESD14, ESD15, ESD16, ESD17, ESD18, ESD19, ESD20, ESD21, ESD22, ESD23, ESD24, ESD25 | TVS | RF connector ESD protection TVS diodes |
| Configuration, Status and Setup Components | ||
| R56, R57, R58, R59 | 0 Ohm resistor | Board BOM version BOM_VER[3:0]. Default BOM_VER=0 (all resistors populated). |
| R160, R161, R163, R164, R166, R167, R168, R169, R171, R172 | 0 Ohm resistor | FPGA (IC8) MSEL[3:0]. Default mode: Active Serial Standard configuration. |
| [R268, R271, R275, R279], [R269, R273, R277, R281] | 0 Ohm resistor | DAC#1 differential channels TX1_BB_I/Q connection selection to either LMS7002M #1 or LMS7002M #2. Default populated group is [R268, R271, R275, R279]. Resistor groups are defined in [] brackets. |
| [R270, R274, R278, R282], [R272, R276, R280, R283] | 0 Ohm resistor | DAC#2 differential channels TX2_BB_I/Q connection selection to either LMS7002M #1 or LMS7002M #2. Default populated group is [R270, R274, R278, R282]. Resistor groups are defined in [] brackets. |
| R364, R379, R384 and their respective power connecting resistors R365, R380, R382 | 0 Ohm resistor | Clock buffer (IC52) CLKin0 (pin 13) clock source selection. R364 and R365 are populated by default. |
| R368, R372, R374 | 0 Ohm resistor | Clock buffer (IC52) CLKin1 (pin 28) clock source selection. R374 is populated by default. |
| R375 | 0 Ohm resistor | Clock buffer (IC52) source (CLKin0 or CLKin1) selection. If unpopulated, clock source is CLKin0 (default). If populated, clock source is CLKin1. |
| R302, R305, R307 | 10 kOhm resistor | USB3.0 microcontroller (IC13) boot configuration (PMODE0[2:0]) resistors. Default mode: SPI boot, On Failure - USB Boot |
| R294, R296, R298 | 10 kOhm resistor | USB3.0 microcontroller (IC13) crystal/clock frequency selection (FSLC[2:0]) resistors. Default mode: 19.2MHz crystal |
| J28, R313 | Pin header, 0 Ohm resistor | USB3.0 microcontroller (IC13) boot source (Flash memory or USB), 0.1” pitch jumper or 0402 0R resistor. In normal operation jumper or resistor must be placed. |
| J29 | JTAG chain pin header | USB3.0 microcontroller (IC13) debugging pin header, 0.05” pitch |
| SW1 | Push-button | USB3.0 microcontroller reset button |
| J26 | JTAG chain pin header | FPGA programming pin header for Altera USB-Blaster download cable, 0.1” pitch |
| LED1 | Green status LED | FPGA configuration done LED |
| LED2-LED5 | Green status LEDs | User defined general purpose green LEDs |
| LED6 | Red-green status LED | User defined general purpose dual colour LED |
| General User Input/Output | ||
| J31, J32 | Connector 0.1” | PMOD connectors |
| SW2 | Switch | 4-bit FPGA switch |
| J33 | Pin header | Board cooling fan pin header, 0.1” |
| Memory Devices | ||
| IC3, IC5, IC51 | EEPROM | 128Kbit (16K x 8) EEPROM, LMS7002 MCU firmware and general purpose memory |
| IC4, IC6 | EEPROM | 512Kbit (64K x 8) EEPROM, connected to main I2C bus |
| IC30 | Flash memory | 128Mbit (16M x 8) Flash for FPGA configuration (unpopulated) |
| IC32 | Flash memory | 128Mbit (16M x 8) Flash for FPGA configuration |
| IC33, IC34, IC35, IC36 | DDR3 memory | 2Gbit (128M x 16) DDR3 SDRAM |
| Communication Ports | ||
| J27 | USB3.0 connector | microUSB3.0 (type B) connector |
| P1 | PCIe connector | PCI Express (Gen1) x4 connector |
| Clock Circuitry | ||
| XO1 | VCOCXO | 10MHz voltage- and oven-controlled crystal oscillator |
| XO2, XO3 | VCTCXO | 30.72MHz voltage-controlled crystal oscillator |
| XO4 | VCTCXO | 40MHz voltage-controlled crystal oscillator |
| IC57 | IC | Programmable clock generator for the FPGA reference clock input and RF boards |
| IC53 | IC | ADF4002 phase detector |
| IC54 | IC | 16-bit DAC for VCTCXO/VCOCXO frequency tuning |
| IC52 | IC | Clock buffer |
| IC55 | IC | Clock buffer |
| J36 | U.FL connector | Reference clock input |
| J35 | U.FL connector | Reference clock output |
| XO5 | Crystal oscillator | 100MHz single-ended FPGA clock |
| XO6 | Crystal oscillator | 125MHz single-ended FPGA clock |
| XO7 | Crystal oscillator | 125MHz differential FPGA-DDR clock |
| XO8 | Crystal oscillator | 125MHz differential FPGA-DDR clock |
| XO9 | Crystal oscillator | 125MHz differential FPGA clock for PCIe REFCLK1 |
| IC56 | IC | Single-ended to differential clock converter. Clock source is IC57 pin 9. Connected to FPGA PCIe REFCLK2 and LVDS connector J30. |
| Power Supply | ||
| J37 | DC input jack | External 12V DC power supply |
| J38 | Header | 6-pin PCIe power connector, 0.165” pitch |
| J39 | Pin header | External 12V DC power supply and main internal power rail |
LimeSDR-QPCIe board version 1.2 picture with highlighted top components are presented in Figure 3.
LimeSDR-QPCIe board version 1.2 picture with highlighted bottom components is presented in Figure 4.
LimeSDR-QPCIe Board Architecture
The heart of the LimeSDR-QPCIe board is Altera Cyclone V GX FPGA. Its main function is to transfer digital data between the PC through an edge PCIE and a USB3.0 connector. The block diagram for LimeSDR-QPCIe board is presented in the Figure 5.
FPGA configuration
FPGA is set to use x1 Active Serial (AS) configuration scheme. In this scheme if valid configuration file exists in FLASH memory (IC30 or IC32) it is automatically loaded after power is applied to the board. In Table 2 it is listed resistor setup for Active Serial (AS) configuration mode select.
| Schematic signal name | Logic level | 0R Resistor setup | |
|---|---|---|---|
| MSEL0 | H | R160 (NF) | R161 (Fit) |
| MSEL1 | H | R163 (NF) | R164 (Fit) |
| MSEL2 | L | R166 (Fit) | R167 (NF) |
| MSEL3 | L | R168 (Fit) | R169 (NF) |
| MSEL4 | H | R171 (NF) | R172 (Fit) |
There are two options which allows to change configuration file in FLASH memory:
- USB 3.0 controller – CYUSB3013 (IC42) has access to configuration memory. With valid firmware and software, gateware for FPGA can be uploaded into FLASH memory (IC30 or IC32) by using USB3.0 cable. IC42 can initiate FPGA reconfiguration. For signal interconnect details see chapter 2.2.2.3 USB 3.0 Controller.
- JTAG Header – 10pin connector (J26) provides access to FPGA JTAG chain. By using external download cable such as USB-Blaster and Quartus II Programmer software FLASH memory (IC30 or IC32) can be reprogrammed. JTAG connections are listed in Table 3.
| Connector pin | Schematic signal name | FPGA pin (IC29) | Comment |
|---|---|---|---|
| 1 | FPGA_JTAG_TCK | AC7 | R170 Pull-Down resistor |
| 2 | VCC2P5 | - | |
| 3 | FPGA_JTAG_TDO | W9 | |
| 4 | VCC2P5 | - | |
| 5 | FPGA_JTAG_TMS | V7 | R162 Pull-Up resistor |
| 6 | - | - | |
| 7 | - | - | |
| 8 | - | - | |
| 9 | FPGA_JTAG_TDI | U7 | R165 Pull-Up resistor |
| 10 | GND | - |
Main components
This chapter describes main components mounted on LimeSDR-QPCIe v1.2 board.
LMS7002M RF transceiver
There are two LMS7002M field programmable RF transceiver ICs (LMS7002M#1 - IC1 and LMS7002M#1 - IC2), interface signals can be acknowledged by corresponding names LMSx_*, where x can be 1 or 2. For example LMS1_* signals belongs to IC1 and LMS2_* belongs to IC2.
In the following manner interface and control signals are described below:
- Digital Interface Signals: LMS7002 is using data bus LMSx_DIQ1_D[11:0] and LMSx_DIQ2_D[11:0], LMSx_ENABLE_IQSEL1 and LMSx_ENABLE_IQSEL2, LMSx_FCLK1 and LMSx_FCLK2, LMSx_MCLK1 and LMSx_MCLK2 signals to transfer data to/from FPGA. Indexes 1 and 2 indicate transceiver digital data PORT-1 or PORT-2. Any of these ports can be used to transmit or receive data. By default, PORT-1 is selected as receive port and PORT-2 is selected as transmit port. The FCLK# is input clock and MCLK# is output clock for LMS7002M transceiver. TXNRX signals sets ports directions. For LMS7002M interface timing details refer to LMS7002M transceiver datasheet page 12-13 [1].
- LMS Control Signals: these signals are used for optional functionality:
- LMSx_RXEN, LMSx_TXEN – receiver and transmitter enable/disable signals.
- LMS_RESET – LMS7002M reset signal.
- SPI Interface: LMS7002M transceiver is configured via 4-wire SPI interface; FPGA_SPI0_SCLK, FPGA_SPI0_MOSI, FPGA_SPI0_MISO_LMSx, FPGA_SPI0_LMSx_SS. The SPI interface controlled from FPGA.
- LMS I2C Interface: LMS EEPROM are connected to this interface. The signals LMSx_I2C_SCL, LMSx_I2C_DATA is not connected to FPGA
The Table 4 and Table 5below lists RF transceiver respectively LMS7002#1 and LMS7002#2 pins, schematic signal names, FPGA interconnections and I/O standard.
| Chip pin (IC1) | Chip reference (IC1) | Schematic signal name | FPGA pin | FPGA I/O standard | Comments |
|---|---|---|---|---|---|
| AM24 | xoscin_rx | LMS1_RxPLL_CLK | NC | 3.3V | Connected to 30.72 MHz clock |
| P34 | MCLK2 | LMS1_MCLK2 | U21 | 2.5V/3.3V | |
| R29 | FCLK2 | LMS1_FCLK2 | Y22 | 2.5V/3.3V | |
| U31 | TXNRX2 | LMS1_TXNRX2 | U26 | 2.5V/3.3V | |
| V34 | RXEN | LMS1_RXEN | Y26 | 2.5V/3.3V | |
| R33 | ENABLE_IQSEL2 | LMS1_ENABLE_IQSEL2 | AA26 | 2.5V/3.3V | |
| H30 | DIQ2_D0 | LMS1_DIQ2_D0 | AC27 | 2.5V/3.3V | |
| J31 | DIQ2_D1 | LMS1_DIQ2_D1 | AB27 | 2.5V/3.3V | |
| K30 | DIQ2_D2 | LMS1_DIQ2_D2 | Y21 | 2.5V/3.3V | |
| K32 | DIQ2_D3 | LMS1_DIQ2_D3 | AA29 | 2.5V/3.3V | |
| L31 | DIQ2_D4 | LMS1_DIQ2_D4 | Y28 | 2.5V/3.3V | |
| K34 | DIQ2_D5 | LMS1_DIQ2_D5 | AC26 | 2.5V/3.3V | |
| M30 | DIQ2_D6 | LMS1_DIQ2_D6 | W27 | 2.5V/3.3V | |
| M32 | DIQ2_D7 | LMS1_DIQ2_D7 | AA25 | 2.5V/3.3V | |
| N31 | DIQ2_D8 | LMS1_DIQ2_D8 | V26 | 2.5V/3.3V | |
| N33 | DIQ2_D9 | LMS1_DIQ2_D9 | AH29 | 2.5V/3.3V | |
| P30 | DIQ2_D10 | LMS1_DIQ2_D10 | V27 | 2.5V/3.3V | |
| P32 | DIQ2_D11 | LMS1_DIQ2_D11 | W28 | 2.5V/3.3V | |
| E5 | xoscin_tx | LMS1_TxPLL_CLK | NC | 3.3V | Connected to 30.72 MHz clock |
| AB34 | MCLK1 | LMS1_MCLK1 | U22 | 2.5V/3.3V | |
| AA33 | FCLK1 | LMS1_FCLK1 | Y30 | 2.5V/3.3V | |
| V32 | TXNRX1 | LMS1_TXNRX1 | U27 | 2.5V/3.3V | |
| U29 | TXEN | LMS1_TXEN | V21 | 2.5V/3.3V | |
| Y32 | ENABLE_IQSEL1 | LMS1_ENABLE_IQSEL1 | U28 | 2.5V/3.3V | |
| AG31 | DIQ1_D0 | LMS1_DIQ1_D0 | T28 | 2.5V/3.3V | |
| AF30 | DIQ1_D1 | LMS1_DIQ1_D1 | Y23 | 2.5V/3.3V | |
| AF34 | DIQ1_D2 | LMS1_DIQ1_D2 | AB28 | 2.5V/3.3V | |
| AE31 | DIQ1_D3 | LMS1_DIQ1_D3 | T29 | 2.5V/3.3V | |
| AD30 | DIQ1_D4 | LMS1_DIQ1_D4 | AA23 | 2.5V/3.3V | |
| AC29 | DIQ1_D5 | LMS1_DIQ1_D5 | V22 | 2.5V/3.3V | |
| AE33 | DIQ1_D6 | LMS1_DIQ1_D6 | V24 | 2.5V/3.3V | |
| AD32 | DIQ1_D7 | LMS1_DIQ1_D7 | Y27 | 2.5V/3.3V | |
| AC31 | DIQ1_D8 | LMS1_DIQ1_D8 | AC24 | 2.5V/3.3V | |
| AC33 | DIQ1_D9 | LMS1_DIQ1_D9 | V25 | 2.5V/3.3V | |
| AB30 | DIQ1_D10 | LMS1_DIQ1_D10 | W22 | 2.5V/3.3V | |
| AB32 | DIQ1_D11 | LMS1_DIQ1_D11 | AA24 | 2.5V/3.3V | |
| U33 | CORE_LDO_EN | LMS1_CORE_LDO_EN | Y25 | 2.5V/3.3V | |
| E27 | RESET | LMS1_RESET | L21 | 2.5V/3.3V | |
| D28 | SEN | FPGA_SPI0_LMS1_SS | V29 | 2.5V/3.3V | SPI interface |
| C29 | SCLK | FPGA_SPI0_SCLK | T25 | 2.5V/3.3V | SPI interface |
| F30 | SDIO | FPGA_SPI0_MOSI | R26 | 2.5V/3.3V | SPI interface |
| F28 | SDO | FPGA_SPI0_MISO_LMS1 | R30 | 2.5V/3.3V | SPI interface |
| D26 | SDA | LMS1_I2C_SDA | - | 2.5V | Connected to EEPROM |
| C27 | SCL | LMS1_I2C_SCL | - | 2.5V | Connected to EEPROM |
| Chip pin (IC2) | Chip reference (IC2) | Schematic signal name | FPGA pin | FPGA I/O standard | Comments |
|---|---|---|---|---|---|
| P34 | MCLK2 | LMS2_MCLK2 | U23 | 2.5V/3.3V | |
| R29 | FCLK2 | LMS2_FCLK2 | AC29 | 2.5V/3.3V | |
| U31 | TXNRX2 | LMS2_TXNRX2 | AC30 | 2.5V/3.3V | |
| V34 | RXEN | LMS2_RXEN | AE25 | 2.5V/3.3V | |
| R33 | ENABLE_IQSEL2 | LMS2_ENABLE_IQSEL2 | AF25 | 2.5V/3.3V | |
| H30 | DIQ2_D0 | LMS2_DIQ2_D0 | AA28 | 2.5V/3.3V | |
| J31 | DIQ2_D1 | LMS2_DIQ2_D1 | AJ30 | 2.5V/3.3V | |
| K30 | DIQ2_D2 | LMS2_DIQ2_D2 | AB29 | 2.5V/3.3V | |
| K32 | DIQ2_D3 | LMS2_DIQ2_D3 | AD24 | 2.5V/3.3V | |
| L31 | DIQ2_D4 | LMS2_DIQ2_D4 | AG28 | 2.5V/3.3V | |
| K34 | DIQ2_D5 | LMS2_DIQ2_D5 | AG27 | 2.5V/3.3V | |
| M30 | DIQ2_D6 | LMS2_DIQ2_D6 | AB26 | 2.5V/3.3V | |
| M32 | DIQ2_D7 | LMS2_DIQ2_D7 | AF24 | 2.5V/3.3V | |
| N31 | DIQ2_D8 | LMS2_DIQ2_D8 | AH30 | 2.5V/3.3V | |
| N33 | DIQ2_D9 | LMS2_DIQ2_D9 | AE23 | 2.5V/3.3V | |
| P30 | DIQ2_D10 | LMS2_DIQ2_D10 | AG29 | 2.5V/3.3V | |
| P32 | DIQ2_D11 | LMS2_DIQ2_D11 | AE26 | 2.5V/3.3V | |
| E5 | xoscin_tx | LMS2_TxPLL_CLK | NC | 3.3V | Connected to 30.72 MHz clock |
| AB34 | MCLK1 | LMS2_MCLK1 | T24 | 2.5V/3.3V | |
| AA33 | FCLK1 | LMS2_FCLK1 | W30 | 2.5V/3.3V | |
| V32 | TXNRX1 | LMS2_TXNRX1 | AF28 | 2.5V/3.3V | |
| U29 | TXEN | LMS2_TXEN | AD27 | 2.5V/3.3V | |
| Y32 | ENABLE_IQSEL1 | LMS2_ENABLE_IQSEL1 | AF29 | 2.5V/3.3V | |
| AG31 | DIQ1_D0 | LMS2_DIQ1_D0 | AD25 | 2.5V/3.3V | |
| AF30 | DIQ1_D1 | LMS2_DIQ1_D1 | AD29 | 2.5V/3.3V | |
| AF34 | DIQ1_D2 | LMS2_DIQ1_D2 | AH27 | 2.5V/3.3V | |
| AE31 | DIQ1_D3 | LMS2_DIQ1_D3 | AE30 | 2.5V/3.3V | |
| AD30 | DIQ1_D4 | LMS2_DIQ1_D4 | AE28 | 2.5V/3.3V | |
| AC29 | DIQ1_D5 | LMS2_DIQ1_D5 | AD30 | 2.5V/3.3V | |
| AE33 | DIQ1_D6 | LMS2_DIQ1_D6 | AJ28 | 2.5V/3.3V | |
| AD32 | DIQ1_D7 | LMS2_DIQ1_D7 | AF26 | 2.5V/3.3V | |
| AC31 | DIQ1_D8 | LMS2_DIQ1_D8 | AE27 | 2.5V/3.3V | |
| AC33 | DIQ1_D9 | LMS2_DIQ1_D9 | AJ29 | 2.5V/3.3V | |
| AB30 | DIQ1_D10 | LMS2_DIQ1_D10 | AD28 | 2.5V/3.3V | |
| AB32 | DIQ1_D11 | LMS2_DIQ1_D11 | AF30 | 2.5V/3.3V | |
| U33 | CORE_LDO_EN | LMS2_CORE_LDO_EN | AD23 | 2.5V/3.3V | |
| E27 | RESET | LMS2_RESET | AA30 | 2.5V/3.3V | |
| D28 | SEN | FPGA_SPI0_LMS2_SS | U29 | 2.5V/3.3V | SPI interface |
| C29 | SCLK | FPGA_SPI0_SCLK | T25 | 2.5V/3.3V | SPI interface |
| F30 | SDIO | FPGA_SPI0_MOSI | R26 | 2.5V/3.3V | SPI interface |
| F28 | SDO | FPGA_SPI0_MISO_LMS2 | V30 | 2.5V/3.3V | SPI interface |
| D26 | SDA | LMS2_I2C_SDA | - | 2.5V | Connected to EEPROM |
| C27 | SCL | LMS2_I2C_SCL | - | 2.5V | Connected to EEPROM |
SDRAM
LimeSDR-QPCIe board has four 2Gb DDR3 SDRAM memory ICs (AS4C128M16D3B-12BCN [link]) which are connected to Cyclone V GX FPGA. The memory can be used for data manipulation at high data rates between transceiver and FPGA. There are two independent DDR3 SDRAM interfaces:
- DDR3 TOP – this is 32bit data interface which consist of two x16 memory devices (IC33 AND IC34) with a single address and command bus. Interface is connected to FPGA Bank 7A and 8A and uses hard memory controller. Error! Reference source not found. lists DDR3 TOP interface pins.
- DDR3 BOT – this is 32bit data interface which consist of two x16 memory devices (IC35 AND IC36) with a single address and command bus. Interface is connected to FPGA Bank 3B and 4A and uses hard memory controller. lists DDR3 BOT interface pins.
Following Table 6 lists signal and pin information for DDR3 TOP interface and Table 7 for the DDR3 BOT interface.
| RAM reference | RAM pin | Schematic signal name | FPGA pin (IC29) | FPGA I/O standard | Comments |
|---|---|---|---|---|---|
| Address bus (IC33 and IC34 shared signals) | |||||
| A0 | N3 | DDR3_TOP_A0 | B11 | SSTL-15 Class I | Active termination |
| A1 | P7 | DDR3_TOP_A1 | A11 | SSTL-15 Class I | Active termination |
| A2 | P3 | DDR3_TOP_A2 | F9 | SSTL-15 Class I | Active termination |
| A3 | N2 | DDR3_TOP_A3 | E10 | SSTL-15 Class I | Active termination |
| A4 | P8 | DDR3_TOP_A4 | F16 | SSTL-15 Class I | Active termination |
| A5 | P2 | DDR3_TOP_A5 | E16 | SSTL-15 Class I | Active termination |
| A6 | R8 | DDR3_TOP_A6 | D9 | SSTL-15 Class I | Active termination |
| A7 | R2 | DDR3_TOP_A7 | C10 | SSTL-15 Class I | Active termination |
| A8 | T8 | DDR3_TOP_A8 | E12 | SSTL-15 Class I | Active termination |
| A9 | R3 | DDR3_TOP_A9 | D13 | SSTL-15 Class I | Active termination |
| A10/AP | L7 | DDR3_TOP_A10 | B7 | SSTL-15 Class I | Active termination |
| A11 | R7 | DDR3_TOP_A11 | A8 | SSTL-15 Class I | Active termination |
| A12/BC# | N7 | DDR3_TOP_A12 | B6 | SSTL-15 Class I | Active termination |
| A13 | T3 | DDR3_TOP_A13 | A6 | SSTL-15 Class I | Active termination |
| Bank address bus (IC33 and IC34 shared signals) | |||||
| BA0 | M2 | DDR3_TOP_BA0 | A10 | SSTL-15 Class I | Active termination |
| BA1 | N8 | DDR3_TOP_BA1 | F15 | SSTL-15 Class I | Active termination |
| BA2 | M3 | DDR3_TOP_BA2 | E15 | SSTL-15 Class I | Active termination |
| Data bus [0:15] (IC33) | |||||
| DQ0 | E3 | DDR3_TOP_DQ0 | C15 | SSTL-15 Class I | |
| DQ1 | F7 | DDR3_TOP_DQ1 | C16 | SSTL-15 Class I | |
| DQ2 | F2 | DDR3_TOP_DQ2 | C11 | SSTL-15 Class I | |
| DQ3 | F8 | DDR3_TOP_DQ3 | A13 | SSTL-15 Class I | |
| DQ4 | H3 | DDR3_TOP_DQ4 | D17 | SSTL-15 Class I | |
| DQ5 | H8 | DDR3_TOP_DQ5 | E17 | SSTL-15 Class I | |
| DQ6 | G2 | DDR3_TOP_DQ6 | D12 | SSTL-15 Class I | |
| DQ7 | H7 | DDR3_TOP_DQ7 | A14 | SSTL-15 Class I | |
| DQ8 | D7 | DDR3_TOP_DQ8 | B17 | SSTL-15 Class I | |
| DQ9 | C3 | DDR3_TOP_DQ9 | C17 | SSTL-15 Class I | |
| DQ10 | C8 | DDR3_TOP_DQ10 | A16 | SSTL-15 Class I | |
| DQ11 | C2 | DDR3_TOP_DQ11 | C14 | SSTL-15 Class I | |
| DQ12 | A7 | DDR3_TOP_DQ12 | F18 | SSTL-15 Class I | |
| DQ13 | A2 | DDR3_TOP_DQ13 | G18 | SSTL-15 Class I | |
| DQ14 | B8 | DDR3_TOP_DQ14 | B18 | SSTL-15 Class I | |
| DQ15 | A3 | DDR3_TOP_DQ15 | A19 | SSTL-15 Class I | |
| Data bus [16:31] (IC34) | |||||
| DQ0 | E3 | DDR3_TOP_DQ16 | D18 | SSTL-15 Class I | |
| DQ1 | F7 | DDR3_TOP_DQ17 | D19 | SSTL-15 Class I | |
| DQ2 | F2 | DDR3_TOP_DQ18 | A21 | SSTL-15 Class I | |
| DQ3 | F8 | DDR3_TOP_DQ19 | B21 | SSTL-15 Class I | |
| DQ4 | H3 | DDR3_TOP_DQ20 | E18 | SSTL-15 Class I | |
| DQ5 | H8 | DDR3_TOP_DQ21 | F19 | SSTL-15 Class I | |
| DQ6 | G2 | DDR3_TOP_DQ22 | B23 | SSTL-15 Class I | |
| DQ7 | H7 | DDR3_TOP_DQ23 | B24 | SSTL-15 Class I | |
| DQ8 | D7 | DDR3_TOP_DQ24 | C19 | SSTL-15 Class I | |
| DQ9 | C3 | DDR3_TOP_DQ25 | D20 | SSTL-15 Class I | |
| DQ10 | C8 | DDR3_TOP_DQ26 | A25 | SSTL-15 Class I | |
| DQ11 | C2 | DDR3_TOP_DQ27 | D22 | SSTL-15 Class I | |
| DQ12 | A7 | DDR3_TOP_DQ28 | C20 | SSTL-15 Class I | |
| DQ13 | A2 | DDR3_TOP_DQ29 | C21 | SSTL-15 Class I | |
| DQ14 | B8 | DDR3_TOP_DQ30 | D23 | SSTL-15 Class I | |
| DQ15 | A3 | DDR3_TOP_DQ31 | C25 | SSTL-15 Class I | |
| Data mask[0:1] (IC33) | |||||
| LDM | E7 | DDR3_TOP_DM0 | B14 | SSTL-15 Class I | |
| UDM | D3 | DDR3_TOP_DM1 | B19 | SSTL-15 Class I | |
| Data mask[2:3] (IC34) | |||||
| LDM | E7 | DDR3_TOP_DM2 | C24 | SSTL-15 Class I | |
| UDM | D3 | DDR3_TOP_DM3 | D25 | SSTL-15 Class I | |
| Data strobe[0:1] (IC33) | |||||
| LDQS | G3 | DDR3_TOP_DQS0_P | K17 | Differential 1.5-V SSTL Class I | |
| LDQS# | F3 | DDR3_TOP_DQS0_N | J17 | Differential 1.5-V SSTL Class I | |
| UDQS | C7 | DDR3_TOP_DQS1_P | K16 | Differential 1.5-V SSTL Class I | |
| UDQS# | B7 | DDR3_TOP_DQS1_N | L16 | Differential 1.5-V SSTL Class I | |
| Data strobe[2:3] (IC34) | |||||
| LDQS | G3 | DDR3_TOP_DQS2_P | L18 | Differential 1.5-V SSTL Class I | |
| LDQS# | F3 | DDR3_TOP_DQS2_N | K18 | Differential 1.5-V SSTL Class I | |
| UDQS | C7 | DDR3_TOP_DQS3_P | K20 | Differential 1.5-V SSTL Class I | |
| UDQS# | B7 | DDR3_TOP_DQS3_N | J19 | Differential 1.5-V SSTL Class I | |
| Memory clock (IC33 and IC34 shared signals) | |||||
| CK# | K7 | DDR3_TOP_CK_N | M8 | Differential 1.5-V SSTL Class I | |
| CK | J7 | DDR3_TOP_CK_P | M9 | Differential 1.5-V SSTL Class I | |
| Control signals(IC33 and IC34 shared signals) | |||||
| CKE | K9 | DDR3_TOP_CKE | A18 | SSTL-15 Class I | |
| WE# | L3 | DDR3_TOP_WEn | C7 | SSTL-15 Class I | Active termination |
| CAS# | K3 | DDR3_TOP_CASn | C9 | SSTL-15 Class I | Active termination |
| RAS# | J3 | DDR3_TOP_RASn | B8 | SSTL-15 Class I | Active termination |
| CS# | L2 | DDR3_TOP_CSn | J15 | SSTL-15 Class I | Active termination |
| ODT | K1 | DDR3_TOP_ODT | B13 | SSTL-15 Class I | Active termination |
| RESET# | T2 | DDR3_TOP_RESETn | B22 | 1.5V | Active termination |
| VREF (IC33 and IC34 shared signals) | |||||
| VREFDQ | H1 | VREF_DDR3_TOP | - | ||
| VREFCA | M8 | VREF_DDR3_TOP | - | ||
| Memory ZQ impedance calibration (IC33) | |||||
| ZQ | L8 | DDR3_TOP_RZQ0 | - | ||
| Memory ZQ impedance calibration (IC34) | |||||
| ZQ | L8 | DDR3_TOP_RZQ1 | - | ||
| FPGA OCT calibration pin | |||||
| - | - | OCT_RZQIN1 | B12 | SSTL-15 | |
| RAM reference | RAM pin | Schematic signal name | FPGA pin (IC29) | FPGA I/O standard | Comments |
|---|---|---|---|---|---|
| Address bus (IC35 and IC36 shared signals) | |||||
| A0 | N3 | DDR3_BOT_A0 | AJ12 | SSTL-15 Class I | Active termination |
| A1 | P7 | DDR3_BOT_A1 | AK12 | SSTL-15 Class I | Active termination |
| A2 | P3 | DDR3_BOT_A2 | AH11 | SSTL-15 Class I | Active termination |
| A3 | N2 | DDR3_BOT_A3 | AH12 | SSTL-15 Class I | Active termination |
| A4 | P8 | DDR3_BOT_A4 | AG13 | SSTL-15 Class I | Active termination |
| A5 | P2 | DDR3_BOT_A5 | AG14 | SSTL-15 Class I | Active termination |
| A6 | R8 | DDR3_BOT_A6 | AK10 | SSTL-15 Class I | Active termination |
| A7 | R2 | DDR3_BOT_A7 | AK11 | SSTL-15 Class I | Active termination |
| A8 | T8 | DDR3_BOT_A8 | AF11 | SSTL-15 Class I | Active termination |
| A9 | R3 | DDR3_BOT_A9 | AG11 | SSTL-15 Class I | Active termination |
| A10/AP | L7 | DDR3_BOT_A10 | AJ8 | SSTL-15 Class I | Active termination |
| A11 | R7 | DDR3_BOT_A11 | AK8 | SSTL-15 Class I | Active termination |
| A12/BC# | N7 | DDR3_BOT_A12 | AJ7 | SSTL-15 Class I | Active termination |
| A13 | T3 | DDR3_BOT_A13 | AK7 | SSTL-15 Class I | Active termination |
| Bank address bus (IC35 and IC36 shared signals) | |||||
| BA0 | M2 | DDR3_BOT_BA0 | AH9 | SSTL-15 Class I | Active termination |
| BA1 | N8 | DDR3_BOT_BA1 | AH10 | SSTL-15 Class I | Active termination |
| BA2 | M3 | DDR3_BOT_BA2 | AJ10 | SSTL-15 Class I | Active termination |
| Data bus [0:15] (IC35) | |||||
| DQ0 | E3 | DDR3_BOT_DQ0 | AF15 | SSTL-15 Class I | |
| DQ1 | F7 | DDR3_BOT_DQ1 | AE16 | SSTL-15 Class I | |
| DQ2 | F2 | DDR3_BOT_DQ2 | AJ14 | SSTL-15 Class I | |
| DQ3 | F8 | DDR3_BOT_DQ3 | AH15 | SSTL-15 Class I | |
| DQ4 | H3 | DDR3_BOT_DQ4 | AE17 | SSTL-15 Class I | |
| DQ5 | H8 | DDR3_BOT_DQ5 | AD17 | SSTL-15 Class I | |
| DQ6 | G2 | DDR3_BOT_DQ6 | AJ15 | SSTL-15 Class I | |
| DQ7 | H7 | DDR3_BOT_DQ7 | AF14 | SSTL-15 Class I | |
| DQ8 | D7 | DDR3_BOT_DQ8 | AK17 | SSTL-15 Class I | |
| DQ9 | C3 | DDR3_BOT_DQ9 | AK16 | SSTL-15 Class I | |
| DQ10 | C8 | DDR3_BOT_DQ10 | AG17 | SSTL-15 Class I | |
| DQ11 | C2 | DDR3_BOT_DQ11 | AJ18 | SSTL-15 Class I | |
| DQ12 | A7 | DDR3_BOT_DQ12 | AG16 | SSTL-15 Class I | |
| DQ13 | A2 | DDR3_BOT_DQ13 | AF16 | SSTL-15 Class I | |
| DQ14 | B8 | DDR3_BOT_DQ14 | AJ19 | SSTL-15 Class I | |
| DQ15 | A3 | DDR3_BOT_DQ15 | AH20 | SSTL-15 Class I | |
| Data bus [16:31] (IC36) | |||||
| DQ0 | E3 | DDR3_BOT_DQ16 | AE18 | SSTL-15 Class I | |
| DQ1 | F7 | DDR3_BOT_DQ17 | AD18 | SSTL-15 Class I | |
| DQ2 | F2 | DDR3_BOT_DQ18 | AJ20 | SSTL-15 Class I | |
| DQ3 | F8 | DDR3_BOT_DQ19 | AK22 | SSTL-15 Class I | |
| DQ4 | H3 | DDR3_BOT_DQ20 | AF19 | SSTL-15 Class I | |
| DQ5 | H8 | DDR3_BOT_DQ21 | AF18 | SSTL-15 Class I | |
| DQ6 | G2 | DDR3_BOT_DQ22 | AH21 | SSTL-15 Class I | |
| DQ7 | H7 | DDR3_BOT_DQ23 | AK23 | SSTL-15 Class I | |
| DQ8 | D7 | DDR3_BOT_DQ24 | AG19 | SSTL-15 Class I | |
| DQ9 | C3 | DDR3_BOT_DQ25 | AG18 | SSTL-15 Class I | |
| DQ10 | C8 | DDR3_BOT_DQ26 | AH24 | SSTL-15 Class I | |
| DQ11 | C2 | DDR3_BOT_DQ27 | AK25 | SSTL-15 Class I | |
| DQ12 | A7 | DDR3_BOT_DQ28 | AE20 | SSTL-15 Class I | |
| DQ13 | A2 | DDR3_BOT_DQ29 | AD19 | SSTL-15 Class I | |
| DQ14 | B8 | DDR3_BOT_DQ30 | AG24 | SSTL-15 Class I | |
| DQ15 | A3 | DDR3_BOT_DQ31 | AK26 | SSTL-15 Class I | |
| Data mask[0:1] (IC35) | |||||
| LDM | E7 | DDR3_BOT_DM0 | AE15 | SSTL-15 Class I | |
| UDM | D3 | DDR3_BOT_DM1 | AH19 | SSTL-15 Class I | |
| Data mask[2:3] (IC36) | |||||
| LDM | E7 | DDR3_BOT_DM2 | AJ23 | SSTL-15 Class I | |
| UDM | D3 | DDR3_BOT_DM3 | AJ27 | SSTL-15 Class I | |
| Data strobe[0:1] (IC35) | |||||
| LDQS | G3 | DDR3_BOT_DQS0_P | Y16 | Differential 1.5-V SSTL Class I | |
| LDQS# | F3 | DDR3_BOT_DQS0_N | AA16 | Differential 1.5-V SSTL Class I | |
| UDQS | C7 | DDR3_BOT_DQS1_P | Y17 | Differential 1.5-V SSTL Class I | |
| UDQS# | B7 | DDR3_BOT_DQS1_N | Y18 | Differential 1.5-V SSTL Class I | |
| Data strobe[2:3] (IC36) | |||||
| LDQS | G3 | DDR3_BOT_DQS2_P | Y20 | Differential 1.5-V SSTL Class I | |
| LDQS# | F3 | DDR3_BOT_DQS2_N | AA20 | Differential 1.5-V SSTL Class I | |
| UDQS | C7 | DDR3_BOT_DQS3_P | AB19 | Differential 1.5-V SSTL Class I | |
| UDQS# | B7 | DDR3_BOT_DQS3_N | AC19 | Differential 1.5-V SSTL Class I | |
| Memory clock (IC35 and IC36 shared signals) | |||||
| CK# | K7 | DDR3_BOT_CK_N | AA14 | Differential 1.5-V SSTL Class I | |
| CK | J7 | DDR3_BOT_CK_P | Y13 | Differential 1.5-V SSTL Class I | |
| Control signals(IC35 and IC36 shared signals) | |||||
| sCKE | K9 | DDR3_BOT_CKE | AK18 | SSTL-15 Class I | |
| WE# | L3 | DDR3_BOT_WEn | AK5 | SSTL-15 Class I | Active termination |
| CAS# | K3 | DDR3_BOT_CASn | AF9 | SSTL-15 Class I | Active termination |
| RAS# | J3 | DDR3_BOT_RASn | AG9 | SSTL-15 Class I | Active termination |
| CS# | L2 | DDR3_BOT_CSn | Y12 | SSTL-15 Class I | Active termination |
| ODT | K1 | DDR3_BOT_ODT | AH14 | SSTL-15 Class I | Active termination |
| RESET# | T2 | DDR3_BOT_RESETn | AK21 | 1.5V | Active termination |
| VREF (IC35 and IC36 shared signals) | |||||
| VREFDQ | H1 | VREF_DDR3_BOT | - | ||
| VREFCA | M8 | VREF_DDR3_BOT | - | ||
| Memory ZQ impedance calibration (IC35) | |||||
| ZQ | L8 | DDR3_BOT_RZQ0 | - | ||
| Memory ZQ impedance calibration (IC36) | |||||
| ZQ | L8 | DDR3_BOT_RZQ1 | - | ||
| FPGA OCT calibration pin | |||||
| - | - | OCT_RZQIN0 | AK13 | SSTL-15 | |
USB 3.0 Controller
Software can control LimeSDR-QPCIe board via the USB3 microcontroller (CYUSB3013 (FX3) [link]). The data transfer to/from the board, SPI communication, FPGA configuration is done via the USB3 controller. The controller signals description showed below:
- FX3_DQ[15:0] - FX3 16-bit GPIF data interface is connected FPGA.
- FX3_CTL[12:0] - FX3 GPIF interface control signals.
- FX3_PCLK - GPIF interface clock, connected to FPGA.
- FX3_SPI - interface is used to program FX3 firmware flash or FPGA configuration flash memory.
- FX3 I2C - bus is connected to the main I2C bus.
- PMODE[2:0] – boot options, by default boot from SPI and USB boot is enabled. If J28 jumper is present or R313 is soldered FX3 will boot from IC43 flash memory if correct firmware exists.
- SW1 – resets FX3
- J29 – FX3 JTAG programming/debugging pin header.
In the Table 8 are listed USB3.0 controller (FX3) pins, schematic signal name, FPGA interconnections and I/O standard.
| Chip pin (IC42) | Chip pin (IC42) | Schematic signal name | FPGA pin | FPGA I/O standard | Comments |
|---|---|---|---|---|---|
| F10 | GPIO0 | FX3_DQ0 | U12 | 1.8V | |
| F9 | GPIO1 | FX3_DQ1 | U11 | 1.8V | |
| F7 | GPIO2 | FX3_DQ2 | U8 | 1.8V | |
| G10 | GPIO3 | FX3_DQ3 | U9 | 1.8V | |
| G9 | GPIO4 | FX3_DQ4 | T11 | 1.8V | |
| F8 | GPIO5 | FX3_DQ5 | R10 | 1.8V | |
| H10 | GPIO6 | FX3_DQ6 | T10 | 1.8V | |
| H9 | GPIO7 | FX3_DQ7 | T9 | 1.8V | |
| J10 | GPIO8 | FX3_DQ8 | V11 | 1.8V | |
| J9 | GPIO9 | FX3_DQ9 | V9 | 1.8V | |
| K11 | GPIO10 | FX3_DQ10 | V10 | 1.8V | |
| L10 | GPIO11 | FX3_DQ11 | W10 | 1.8V | |
| K10 | GPIO12 | FX3_DQ12 | Y10 | 1.8V | |
| K9 | GPIO13 | FX3_DQ13 | Y11 | 1.8V | |
| J8 | GPIO14 | FX3_DQ14 | AA11 | 1.8V | |
| G8 | GPIO15 | FX3_DQ15 | AA8 | 1.8V | |
| J6 | GPIO16 | FX3_PCLK | AB16 | 1.5V | |
| K8 | GPIO17 | FX3_CTL0 | AA9 | 1.8V | |
| K7 | GPIO18 | FX3_CTL1 | AB8 | 1.8V | |
| J7 | GPIO19 | FX3_CTL2 | AC9 | 1.8V | |
| H7 | GPIO20 | FX3_CTL3 | AD9 | 1.8V | |
| G7 | GPIO21 | FX3_CTL4 | AF8 | 1.8V | |
| G6 | GPIO22 | FX3_CTL5 | AF7 | 1.8V | |
| K6 | GPIO23 | FX3_CTL6 | AG7 | 1.8V | |
| H8 | GPIO24 | FX3_CTL7 | AF6 | 1.8V | |
| G5 | GPIO25 | FX3_CTL8 | AG6 | 1.8V | |
| H6 | GPIO26 | FX3_CTL9 | AH7 | 1.8V | |
| K5 | GPIO27 | FX3_CTL10 | AH6 | 1.8V | |
| J5 | GPIO28 | FX3_CTL11 | AH4 | 1.8V | |
| H5 | GPIO29 | FX3_CTL12 | AH5 | 1.8V | |
| G4 | GPIO30 | FX3_PMODE0 | - | 1.8V | |
| H4 | GPIO31 | FX3_PMODE1 | - | 1.8V | |
| L4 | GPIO32 | FX3_PMODE2 | - | 1.8V | |
| K2 | GPIO33 | - | - | - | |
| J4 | GPIO34 | - | - | - | |
| K1 | GPIO35 | - | - | - | |
| J2 | GPIO36 | - | - | - | |
| J3 | GPIO37 | - | - | - | |
| J1 | GPIO38 | - | - | - | |
| H2 | GPIO39 | - | - | - | |
| H3 | GPIO40 | - | - | - | |
| F4 | GPIO41 | FPGA_CONF_DONE | L8 | - | Connected to FPGA configuration status CONF_DONE. Additionally, connected to LED1. |
| G2 | GPIO42 | FPGA_NSTATUS | K7 | - | Connected to FPGA nSTATUS pin. |
| G3 | GPIO43 | FPGA_NCONFIG | C5 | - | A high-to-low logic initiates a FPGA reconfiguration. |
| F3 | GPIO44 | FX3_AS_SW | - | - | Logic level L connects FX3_SPI interface to FPGA conf. Flash (IC30, IC32) |
| F2 | GPIO45 | FX3_SPI_AS_SS | - | - | FPGA conf. Flash slave select |
| F5 | GPIO46 | FX3_SPI_FPGA_SS | - | - | |
| E1 | GPIO47 | FX3_FPGA_GPIO0 | AA10 | 1.8V | |
| E5 | GPIO48 | FX3_FPGA_GPIO1 | AB9 | 1.8V | |
| E4 | GPIO49 | FX3_FPGA_GPIO2 | AG8 | 1.8V | |
| D1 | GPIO50 | FX3_FPGA_GPIO3 | AK3 | 1.5V | |
| D2 | GPIO51 | FX3_FPGA_GPIO4 | AJ4 | 1.5V | |
| D3 | GPIO52 | FX3_FPGA_GPIO5 | AJ3 | 1.5V | |
| D4 | GPIO53 | FX3_SPI_SCLK | P20 | 2.5V/3.3V | |
| C1 | GPIO54 | FX3_SPI_FLASH_SS | - | - | Connected to FX3 memory through header J28 |
| C2 | GPIO55 | FX3_SPI_MISO | M21 | 2.5V/3.3V | |
| D5 | GPIO56 | FX3_SPI_MOSI | N20 | 2.5V/3.3V | |
| C4 | GPIO57 | - | - | - | |
| A3 | SSRXM | FX3_USB_SSRX_P | - | - | |
| A4 | SSRXP | FX3_USB_SSRX_N | - | - | |
| A6 | SSTXM | FX3_USB_SSTX_IC_P | - | - | |
| A5 | SSTXP | FX3_USB_SSTX_IC_N | - | - | |
| B3 | R_usb3 | - | - | - | USB3 precision resistor |
| C9 | OTG_ID | FX3_USB_OTG_ID | - | - | |
| A9 | DP | FX3_USB_D_P | - | - | |
| A10 | DM | FX3_USB_D_N | - | - | |
| C8 | R_usb2 | - | - | - | USB2 precision resistor |
| E11 | VBUS | FX3_VBUS | - | - | |
| B2 | FSLC[0] | - | - | - | 10k pulldown for 19.2MHz crystal selection |
| C6 | XTALIN | CYUSB_XTAL_P | - | - | |
| C7 | XTALOUT | CYUSB_XTAL_N | - | - | |
| B4 | FSLC[1] | - | - | - | 10k pulldown for 19.2MHz crystal selection |
| E6 | FSLC[2] | - | - | - | |
| D7 | CLKIN | - | - | - | |
| D6 | CLKIN_32 | - | - | - | |
| D9 | I2C_SCL | FX3_I2C_SCL/ I2C_SCL | AG23 | 1.5V | Voltage level reduced to connect to FPGA. Net labels on FPGA side: I2C_SCL_LS, I2C_SDA_LS |
| D10 | I2C_SDA | FX3_I2C_SDA/ I2C_SDA | AH22 | 1.5V | |
| E7 | TDI | FX3_JTAG_TDI | - | - | 10-pin JTAG connector J29 |
| C10 | TDO | FX3_JTAG_TDO | - | - | |
| B11 | TRST# | FX3_JTAG_TRST | - | - | |
| E8 | TMS | FX3_JTAG_TMS | - | - | |
| F6 | TCK | FX3_JTAG_TCK | - | - | |
| D11 | O[60] | - | - | - |
ADC
There is one Dual-Channel 14-Bit, analog-to-digital converter (ADS4246 – IC37) mounted on board. ADC analog input is connected to RX BB outputs of LMS7002M#1 IC. Digital output pins are connected to FPGA.
The Table 9 lists 14-bit analog to digital converter ADC (IC37) pins, schematic signal name, FPGA interconnections and I/O standard.
| Chip pin (IC37) | Chip reference (IC37) | Schematic signal name | FPGA pin | FPGA I/O standard |
|---|---|---|---|---|
| 41 | DA0_P/DA1 | ADC_DA0_P | L10 | 1.5V |
| 40 | DA0_M/DA0 | ADC_DA0_N | L9 | 1.5V |
| 43 | DA2_P/DA3 | ADC_DA1_P | P10 | 1.5V |
| 42 | DA2_M/DA2 | ADC_DA1_N | N11 | 1.5V |
| 45 | DA4_P/DA5 | ADC_DA2_P | N10 | 1.5V |
| 44 | DA4_M/DA4 | ADC_DA2_N | N9 | 1.5V |
| 47 | DA6_P/DA7 | ADC_DA3_P | R12 | 1.5V |
| 46 | DA6_M/DA6 | ADC_DA3_N | R11 | 1.5V |
| 51 | DA8_P/DA13 | ADC_DA4_P | P12 | 1.5V |
| 50 | DA8_M/DA12 | ADC_DA4_N | N12 | 1.5V |
| 53 | DA10_P/DA9 | ADC_DA5_P | M12 | 1.5V |
| 52 | DA10_M/DA8 | ADC_DA5_N | M11 | 1.5V |
| 55 | DA12_P/DA11 | ADC_DA6_P | L11 | 1.5V |
| 54 | DA12_M/DA10 | ADC_DA6_N | K11 | 1.5V |
| 61 | DB0_P/DB1 | ADC_DB0_P | K12 | 1.5V |
| 60 | DB0_M/DB0 | ADC_DB0_N | J12 | 1.5V |
| 63 | DB2_P/DB3 | ADC_DB1_P | E22 | 1.5V |
| 62 | DB2_M/DB2 | ADC_DB1_N | E21 | 1.5V |
| 3 | DB4_P/DB5 | ADC_DB2_P | E10 | 1.5V |
| 2 | DB4_M/DB4 | ADC_DB2_N | D10 | 1.5V |
| 5 | DB6_P/DB7 | ADC_DB3_P | G14 | 1.5V |
| 4 | DB6_M/DB6 | ADC_DB3_N | F14 | 1.5V |
| 7 | DB8_P/DB13 | ADC_DB4_P | H12 | 1.5V |
| 6 | DB8_M/DB12 | ADC_DB4_N | G12 | 1.5V |
| 9 | DB10_P/DB9 | ADC_DB5_P | J14 | 1.5V |
| 8 | DB10_M/DB8 | ADC_DB5_N | H14 | 1.5V |
| 11 | DB12_P/DB11 | ADC_DB6_P | K13 | 1.5V |
| 10 | DB12_M/DB10 | ADC_DB6_N | J13 | 1.5V |
| 35 | CTRL1 | ADC_CTRL1 | - | - |
| 36 | CTRL2 | ADC_CTRL2 | - | - |
| 34 | CTRL3 | ADC_CTRL3 | - | - |
| 29 | INP_A | ADC_INA_P | - | - |
| 30 | INM_A | ADC_INA_N | - | - |
| 23 | VCM | ADC_VCM | - | - |
| 57 | CLKOUTP/CLKOUT | ADC_CLKOUT_P | L14 | 1.5V |
| 56 | CLKOUTM/UNUSED | ADC_CLKOUT_N | L13 | 1.5V |
| 19 | INP_B | ADC_INB_P | - | - |
| 20 | INM_B | ADC_INB_N | - | - |
| 25 | CLKP | ADC_CLK_P | - | - |
| 26 | CLKM | ADC_CLK_N | - | - |
| 13 | SCLK | FPGA_SPI0_SCLK | T25 | 2.5V/3.3V |
| 14 | SDATA | FPGA_SPI0_MOSI | R26 | 2.5V/3.3V |
| 64 | SDOUT | FPGA_SPI0_MISO_ADC | L20 | 1.5V |
| 15 | SEN | FPGA_SPI0_ADC_SS | E26 | 1.5V |
| 12 | RESET | FPGA_ADC_RESET | D6 | 1.5V |
DACs
LimeSDR-QPCIe board has two 14-Bit Dual Transmit Digital-To-Analog Converters. By default, analog output pins are connected to TX BB input pads of LMS70002M#1 IC. By changing on-board resistors it can be connected to LMS70002M#2 instead. To connect DACs to LMS70002M#2 TX BB input pads R268, R271, R275, R279, R270, R274, R278, R282 resistors has to be removed and R269, R273, R277, R281, R272, R276, R280, R283 resistors has to be fitted.
The tables below list 14-bit digital to analog converter DAC#1 (IC40 - Table 10) and DAC#2 (IC41 - Table 11) pins, schematic signal name, FPGA interconnections and I/O standard.
| Chip pin (IC40) | Chip reference (IC40) | Schematic signal name | FPGA pin | FPGA I/O standard | Comment |
|---|---|---|---|---|---|
| 14 | DA0 | DAC1_DA0 | E27 | 2.5V/3.3V | |
| 13 | DA1 | DAC1_DA1 | F25 | 2.5V/3.3V | |
| 12 | DA2 | DAC1_DA2 | D28 | 2.5V/3.3V | |
| 11 | DA3 | DAC1_DA3 | E28 | 2.5V/3.3V | |
| 10 | DA4 | DAC1_DA4 | F30 | 2.5V/3.3V | |
| 9 | DA5 | DAC1_DA5 | E30 | 2.5V/3.3V | |
| 8 | DA6 | DAC1_DA6 | D27 | 2.5V/3.3V | |
| 7 | DA7 | DAC1_DA7 | C29 | 2.5V/3.3V | |
| 6 | DA8 | DAC1_DA8 | C30 | 2.5V/3.3V | |
| 5 | DA9 | DAC1_DA9 | D29 | 2.5V/3.3V | |
| 4 | DA10 | DAC1_DA10 | D30 | 2.5V/3.3V | |
| 3 | DA11 | DAC1_DA11 | B29 | 2.5V/3.3V | |
| 2 | DA12 | DAC1_DA12 | A29 | 2.5V/3.3V | |
| 1 | DA13 | DAC1_DA13 | B28 | 2.5V/3.3V | |
| 17, 18 | WRTA/WRTIQ, CLKA/CLKIQ | DAC1_CLK | - | 2.5V/3.3V | Clocked from buffer IC55 pin 3. Clock value passed from FPGA to buffer from FPGA pin M23, DAC_CLK_WRT |
| 36 | DB0 | DAC1_DB0 | F28 | 2.5V/3.3V | |
| 35 | DB1 | DAC1_DB1 | F30 | 2.5V/3.3V | |
| 34 | DB2 | DAC1_DB2 | J28 | 2.5V/3.3V | |
| 33 | DB3 | DAC1_DB3 | F29 | 2.5V/3.3V | |
| 32 | DB4 | DAC1_DB4 | K30 | 2.5V/3.3V | |
| 31 | DB5 | DAC1_DB5 | K28 | 2.5V/3.3V | |
| 30 | DB6 | DAC1_DB6 | G29 | 2.5V/3.3V | |
| 29 | DB7 | DAC1_DB7 | J29 | 2.5V/3.3V | |
| 28 | DB8 | DAC1_DB8 | J30 | 2.5V/3.3V | |
| 27 | DB9 | DAC1_DB9 | H27 | 2.5V/3.3V | |
| 26 | DB10 | DAC1_DB10 | H29 | 2.5V/3.3V | |
| 25 | DB11 | DAC1_DB11 | H30 | 2.5V/3.3V | |
| 24 | DB12 | DAC1_DB12 | H26 | 2.5V/3.3V | |
| 23 | DB13 | DAC1_DB13 | H25 | 2.5V/3.3V | |
| 19, 20 | WRTB/RESETIQ, CLKB/SELECTIQ | DAC1_CLK | - | 2.5V/3.3V | Clocked from buffer IC55 pin 3. Clock value passed from FPGA to buffer from FPGA pin M23, DAC_CLK_WRT |
| 48 | MODE | DAC1_MODE | J23 | 2.5V/3.3V | |
| 37 | SLEEP | DAC1_SLEEP | J25 | 2.5V/3.3V | |
| 42 | GSET | - | - | 3.3V | Hardwired to VCC3P3D_DAC1 |
| 43 | EXTIO | - | - | - | Connected to 100nF capacitor |
| Chip pin (IC41) | Chip reference (IC41) | Schematic signal name | FPGA pin | FPGA I/O standard | Comment |
|---|---|---|---|---|---|
| 14 | DA0 | DAC2_DA0 | R27 | 2.5V/3.3V | |
| 13 | DA1 | DAC2_DA1 | K26 | 2.5V/3.3V | |
| 12 | DA2 | DAC2_DA2 | N27 | 2.5V/3.3V | |
| 11 | DA3 | DAC2_DA3 | P30 | 2.5V/3.3V | |
| 10 | DA4 | DAC2_DA4 | N29 | 2.5V/3.3V | |
| 9 | DA5 | DAC2_DA5 | M27 | 2.5V/3.3V | |
| 8 | DA6 | DAC2_DA6 | M28 | 2.5V/3.3V | |
| 7 | DA7 | DAC2_DA7 | L26 | 2.5V/3.3V | |
| 6 | DA8 | DAC2_DA8 | L28 | 2.5V/3.3V | |
| 5 | DA9 | DAC2_DA9 | L29 | 2.5V/3.3V | |
| 4 | DA10 | DAC2_DA10 | L25 | 2.5V/3.3V | |
| 3 | DA11 | DAC2_DA11 | L30 | 2.5V/3.3V | |
| 2 | DA12 | DAC2_DA12 | P29 | 2.5V/3.3V | |
| 1 | DA13 | DAC2_DA13 | N26 | 2.5V/3.3V | |
| 17, 18 | WRTA/WRTIQ, CLKA/CLKIQ | DAC2_CLK | - | 2.5V/3.3V | Clocked from buffer IC55 pin 5. Clock value passed from FPGA to buffer from FPGA pin M23, DAC_CLK_WRT |
| 36 | DB0 | DAC2_DB0 | P26 | 2.5V/3.3V | |
| 35 | DB1 | DAC2_DB1 | N25 | 2.5V/3.3V | |
| 34 | DB2 | DAC2_DB2 | P25 | 2.5V/3.3V | |
| 33 | DB3 | DAC2_DB3 | R28 | 2.5V/3.3V | |
| 32 | DB4 | DAC2_DB4 | R25 | 2.5V/3.3V | |
| 31 | DB5 | DAC2_DB5 | K27 | 2.5V/3.3V | |
| 30 | DB6 | DAC2_DB6 | N24 | 2.5V/3.3V | |
| 29 | DB7 | DAC2_DB7 | M23 | 2.5V/3.3V | |
| 28 | DB8 | DAC2_DB8 | M22 | 2.5V/3.3V | |
| 27 | DB9 | DAC2_DB9 | N22 | 2.5V/3.3V | |
| 26 | DB10 | DAC2_DB10 | R20 | 2.5V/3.3V | |
| 25 | DB11 | DAC2_DB11 | T21 | 2.5V/3.3V | |
| 24 | DB12 | DAC2_DB12 | R21 | 2.5V/3.3V | |
| 23 | DB13 | DAC2_DB13 | R22 | 2.5V/3.3V | |
| 19, 20 | WRTB/RESETIQ, CLKB/SELECTIQ | DAC2_CLK | - | 2.5V/3.3V | Clocked from buffer IC55 pin 5. Clock value passed from FPGA to buffer from FPGA pin M23, DAC_CLK_WRT |
| 48 | MODE | DAC2_MODE | L23 | 2.5V/3.3V | |
| 37 | SLEEP | DAC2_SLEEP | L24 | 2.5V/3.3V | |
| 42 | GSET | - | - | 3.3V | Hardwired to VCC3P3D_DAC2 |
| 43 | EXTIO | - | - | - | Connected to 100nF capacitor |
GNSS receiver
LimeSDR-QPCIe board has GNSS receiver module GPS/GNSS M0578 (IC48). External active antenna for this module can be connected to J34 connector. Module is connected to FPGA (IC29), pin connections can be found on Table 12.
| GNSS pin (IC48) | GNSS module reference (IC48) | Schematic signal name | FPGA pin | FPGA I/O standard |
|---|---|---|---|---|
| 9 | UART RX | GNSS_RX | K25 | 3.3V(2.5V) |
| 10 | UART TX | GNSS_TX | K22 | 3.3V(2.5V) |
| 6 | 1PPS | GNSS_TPULSE | T23 | 3.3V(2.5V) |
| 13 | FIX | GNSS_FIX | R23 | 3.3V(2.5V) |