LimeSDR-QPCIe v1.2 hardware description: Difference between revisions

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{| class="wikitable"
{| class="wikitable"
|+ Table 6 DDR3 TOP interface pins
|+ Table 6 DDR3 TOP interface pins
!RAM reference || RAM pin || Schematic signal name || FPGA pin (IC29) || FPGA I/O standard || Comments
|-
! colspan="6" | Address bus (IC33 and IC34 shared signals)
|-
| A0 ||N3 ||DDR3_TOP_A0 ||B11 ||SSTL-15 Class I ||Active termination
|-
| A1 ||P7 ||DDR3_TOP_A1 ||A11 ||SSTL-15 Class I ||Active termination
|-
| A2 ||P3 ||DDR3_TOP_A2 ||F9 ||SSTL-15 Class I ||Active termination
|-
| A3 ||N2 ||DDR3_TOP_A3 ||E10 ||SSTL-15 Class I ||Active termination
|-
| A4 ||P8 ||DDR3_TOP_A4 ||F16 ||SSTL-15 Class I ||Active termination
|-
| A5 ||P2 ||DDR3_TOP_A5 ||E16 ||SSTL-15 Class I ||Active termination
|-
| A6 ||R8 ||DDR3_TOP_A6 ||D9 ||SSTL-15 Class I ||Active termination
|-
| A7 ||R2 ||DDR3_TOP_A7 ||C10 ||SSTL-15 Class I ||Active termination
|-
| A8 ||T8 ||DDR3_TOP_A8 ||E12 ||SSTL-15 Class I ||Active termination
|-
| A9 ||R3 ||DDR3_TOP_A9 ||D13 ||SSTL-15 Class I ||Active termination
|-
| A10/AP ||L7 ||DDR3_TOP_A10 ||B7 ||SSTL-15 Class I ||Active termination
|-
| A11 ||R7 ||DDR3_TOP_A11 ||A8 ||SSTL-15 Class I ||Active termination
|-
| A12/BC# ||N7 ||DDR3_TOP_A12 ||B6 ||SSTL-15 Class I ||Active termination
|-
| A13 ||T3 ||DDR3_TOP_A13 ||A6 ||SSTL-15 Class I ||Active termination
|-
! colspan="6" | Bank address bus (IC33 and IC34 shared signals)
|-
| BA0 ||M2 ||DDR3_TOP_BA0 ||A10 ||SSTL-15 Class I ||Active termination
|-
| BA1 ||N8 ||DDR3_TOP_BA1 ||F15 ||SSTL-15 Class I ||Active termination
|-
| BA2 ||M3 ||DDR3_TOP_BA2 ||E15 ||SSTL-15 Class I ||Active termination
|-
! colspan="6" | Data bus [0:15] (IC33)
|-
| DQ0 ||E3 ||DDR3_TOP_DQ0 ||C15 ||SSTL-15 Class I ||
|-
| DQ1 ||F7 ||DDR3_TOP_DQ1 ||C16 ||SSTL-15 Class I ||
|-
| DQ2 ||F2 ||DDR3_TOP_DQ2 ||C11 ||SSTL-15 Class I ||
|-
| DQ3 ||F8 ||DDR3_TOP_DQ3 ||A13 ||SSTL-15 Class I ||
|-
| DQ4 ||H3 ||DDR3_TOP_DQ4 ||D17 ||SSTL-15 Class I ||
|-
| DQ5 ||H8 ||DDR3_TOP_DQ5 ||E17 ||SSTL-15 Class I ||
|-
| DQ6 ||G2 ||DDR3_TOP_DQ6 ||D12 ||SSTL-15 Class I ||
|-
| DQ7 ||H7 ||DDR3_TOP_DQ7 ||A14 ||SSTL-15 Class I ||
|-
| DQ8 ||D7 ||DDR3_TOP_DQ8 ||B17 ||SSTL-15 Class I ||
|-
| DQ9 ||C3 ||DDR3_TOP_DQ9 ||C17 ||SSTL-15 Class I ||
|-
| DQ10 ||C8 ||DDR3_TOP_DQ10 ||A16 ||SSTL-15 Class I ||
|-
| DQ11 ||C2 ||DDR3_TOP_DQ11 ||C14 ||SSTL-15 Class I ||
|-
| DQ12 ||A7 ||DDR3_TOP_DQ12 ||F18 ||SSTL-15 Class I ||
|-
| DQ13 ||A2 ||DDR3_TOP_DQ13 ||G18 ||SSTL-15 Class I ||
|-
| DQ14 ||B8 ||DDR3_TOP_DQ14 ||B18 ||SSTL-15 Class I ||
|-
| DQ15 ||A3 ||DDR3_TOP_DQ15 ||A19 ||SSTL-15 Class I ||
|-
! colspan="6" | Data bus [16:31] (IC34)
|-
| DQ0 ||E3 ||DDR3_TOP_DQ16 ||D18 ||SSTL-15 Class I ||
|-
| DQ1 ||F7 ||DDR3_TOP_DQ17 ||D19 ||SSTL-15 Class I ||
|-
| DQ2 ||F2 ||DDR3_TOP_DQ18 ||A21 ||SSTL-15 Class I ||
|-
| DQ3 ||F8 ||DDR3_TOP_DQ19 ||B21 ||SSTL-15 Class I ||
|-
| DQ4 ||H3 ||DDR3_TOP_DQ20 ||E18 ||SSTL-15 Class I ||
|-
| DQ5 ||H8 ||DDR3_TOP_DQ21 ||F19 ||SSTL-15 Class I ||
|-
| DQ6 ||G2 ||DDR3_TOP_DQ22 ||B23 ||SSTL-15 Class I ||
|-
| DQ7 ||H7 ||DDR3_TOP_DQ23 ||B24 ||SSTL-15 Class I ||
|-
| DQ8 ||D7 ||DDR3_TOP_DQ24 ||C19 ||SSTL-15 Class I ||
|-
| DQ9 ||C3 ||DDR3_TOP_DQ25 ||D20 ||SSTL-15 Class I ||
|-
| DQ10 ||C8 ||DDR3_TOP_DQ26 ||A25 ||SSTL-15 Class I ||
|-
| DQ11 ||C2 ||DDR3_TOP_DQ27 ||D22 ||SSTL-15 Class I ||
|-
| DQ12 ||A7 ||DDR3_TOP_DQ28 ||C20 ||SSTL-15 Class I ||
|-
| DQ13 ||A2 ||DDR3_TOP_DQ29 ||C21 ||SSTL-15 Class I ||
|-
| DQ14 ||B8 ||DDR3_TOP_DQ30 ||D23 ||SSTL-15 Class I ||
|-
| DQ15 ||A3 ||DDR3_TOP_DQ31 ||C25 ||SSTL-15 Class I ||
|-
! colspan="6" | Data mask[0:1] (IC33)
|-
| LDM ||E7 ||DDR3_TOP_DM0 ||B14 ||SSTL-15 Class I ||
|-
| UDM ||D3 ||DDR3_TOP_DM1 ||B19 ||SSTL-15 Class I ||
|-
! colspan="6" | Data mask[2:3] (IC34)
|-
| LDM ||E7 ||DDR3_TOP_DM2 ||C24 ||SSTL-15 Class I ||
|-
| UDM ||D3 ||DDR3_TOP_DM3 ||D25 ||SSTL-15 Class I ||
|-
! colspan="6" | Data strobe[0:1] (IC33)
|-
| LDQS ||G3 ||DDR3_TOP_DQS0_P ||K17 ||Differential 1.5-V SSTL Class I ||
|-
| LDQS# ||F3 ||DDR3_TOP_DQS0_N ||J17 ||Differential 1.5-V SSTL Class I ||
|-
| UDQS ||C7 ||DDR3_TOP_DQS1_P ||K16 ||Differential 1.5-V SSTL Class I ||
|-
| UDQS# ||B7 ||DDR3_TOP_DQS1_N ||L16 ||Differential 1.5-V SSTL Class I ||
|-
! colspan="6" | Data strobe[2:3] (IC34)
|-
| LDQS ||G3 ||DDR3_TOP_DQS2_P ||L18 ||Differential 1.5-V SSTL Class I ||
|-
| LDQS# ||F3 ||DDR3_TOP_DQS2_N ||K18 ||Differential 1.5-V SSTL Class I ||
|-
| UDQS ||C7 ||DDR3_TOP_DQS3_P ||K20 ||Differential 1.5-V SSTL Class I ||
|-
| UDQS# ||B7 ||DDR3_TOP_DQS3_N ||J19 ||Differential 1.5-V SSTL Class I ||
|-
! colspan="6" | Memory clock (IC33 and IC34 shared signals)
|-
| CK# ||K7 ||DDR3_TOP_CK_N ||M8 ||Differential 1.5-V SSTL Class I ||
|-
| CK ||J7 ||DDR3_TOP_CK_P ||M9 ||Differential 1.5-V SSTL Class I ||
|-
! colspan="6" | Control signals(IC33 and IC34 shared signals)
|-
| CKE ||K9 ||DDR3_TOP_CKE ||A18 ||SSTL-15 Class I ||
|-
| WE# ||L3 ||DDR3_TOP_WEn ||C7 ||SSTL-15 Class I ||Active termination
|-
| CAS# ||K3 ||DDR3_TOP_CASn ||C9 ||SSTL-15 Class I ||Active termination
|-
| RAS# ||J3 ||DDR3_TOP_RASn ||B8 ||SSTL-15 Class I ||Active termination
|-
| CS# ||L2 ||DDR3_TOP_CSn ||J15 ||SSTL-15 Class I ||Active termination
|-
| ODT ||K1 ||DDR3_TOP_ODT ||B13 ||SSTL-15 Class I ||Active termination
|-
| RESET# ||T2 ||DDR3_TOP_RESETn ||B22 ||1.5V ||Active termination
|-
! colspan="6" | VREF (IC33 and IC34 shared signals)
|-
| VREFDQ ||H1 ||VREF_DDR3_TOP ||- || ||
|-
| VREFCA ||M8 ||VREF_DDR3_TOP ||- || ||
|-
! colspan="6" | Memory ZQ impedance calibration (IC33)
|-
| ZQ ||L8 ||DDR3_TOP_RZQ0 ||- || ||
|-
! colspan="6" | Memory ZQ impedance calibration (IC34)
|-
| ZQ ||L8 ||DDR3_TOP_RZQ1 ||- || ||
|-
! colspan="6" | FPGA OCT calibration pin
|-
| - ||- ||OCT_RZQIN1 ||B12 ||SSTL-15 ||
|}
{| class="wikitable"
|+ Table 7 DDR3 BOT interface pins
!RAM reference || RAM pin || Schematic signal name || FPGA pin (IC29) || FPGA I/O standard || Comments
!RAM reference || RAM pin || Schematic signal name || FPGA pin (IC29) || FPGA I/O standard || Comments


Revision as of 08:13, 19 July 2018

Introduction

LimeSDR-QPCIe is low-cost software defined radio board based on Lime LMS7002M Field Programmable Radio Frequency (FPRF) transceiver and Altera Cyclone V PFGA, through which apps can be programmed to support any type of wireless standard, e.g. UMTS, LTE, LoRa, GPS, WiFi, Zigbee, RFID, Digital Broadcastimng, Radar and many more.

LimeSDR-QPCIe Board Key Features

The LimeSDR-QPCIe development board provides a hardware platform for developing and prototyping high-performance and logic-intensive digital and RF designs using Altera’s Cyclone V FPGA and Lime Microsystems transceiver.

Figure 1. LimeSDR-QPCIe v1.2 board


For more information on the following topics, refer to the respective documents:

  • Cyclone V device family, refer to Cyclone V Device support resources link
  • LMS7002M transceiver resources link


LimeSDR-QPCIe v1.2 board features:

  • USB Interface
    • Cypress FX3 Super Speed USB 3rd generation controller
  • FPGA Features
    • Cyclone V, 5CGXFC7D7F31C8N device in 896-pin FBGA package
    • 150’000 logic elements
    • 6860 Kbits embedded memory
    • 312 embedded 18x18 multipliers
    • 7 PLLs
    • 9 Transceivers (2.5Gbps)
    • PCIe Hard IP Blocks
    • 2 Hard Memory Controllers
  • FPGA Configuration
    • JTAG mode configuration
    • Active serial mode configuration
    • Possibility to update FPGA gateware by using FX3 (USB)
    • Possibility to update FPGA gateware by using PCIe interface.
  • RF
    • 2x LMS7002M, FPRF transceivers
    • Onboard RSSI measurement circuits
    • Onboard loopback control switches
  • DACs and ADCs
    • 2x DAC5672A, dual, 14-bit, Digital-To-Analog converters
    • 1x ADS424, Dual-Channel, 14-bit, Analog-To-Digital converter
  • Memory Devices
    • 4 x 2Gbit DDR3 SDRAM (128M x 16)
    • 4Mbit flash for FX3 firmware
    • 128Mbit flash for FPGA gateware
    • 2 x 128Kbit and 2 x 512Kbit EEPROMs for LMS MCU firmware, LMS MCU data
    • 1 x 128K EEPROM for FX3 or FPGA data
  • Connections
    • microUSB3.0 (type B) connector
    • PCIe x4 edge connector (Gen1)
    • Coaxial RF (U.FL) connectors
    • 2x PMOD header (0.1” pitch)
    • FPGA (0.1” pitch) and FX3 (0.05” pitch) JTAG connectors
    • 12V DC power jack and pinheader
    • LVDS connector (0.05” pitch)
    • Fan connector (12V/5V)
    • PCIe 6-pin power connector
    • Holder for coin cell CR1220 battery
  • Clock System
    • 30.72MHz VCTCXO (precision: ±1 ppm initial, ±4 ppm stable).
    • Possibility to lock VCTCXO to external clock using ADF4002 or tune VCTCXO by onboard DAC (AD5662)
    • Programmable clock generator for the FPGA reference clock input or LMS PLLs
    • VCTCXO clock output for external device synchronization.
    • 1x 100 MHz, 4 x 125MHz crystal oscillators for FPGA
  • Miscellaneous devices
    • LM75 Digital temperature sensor with 2-Wire Interface.
    • DS3231 real-time clock.
    • M0578-A3 GPS/GNSS module receiver
  • Board Size 190mm x 106.7mm (7.48” x 4.20”)

LimeSDR-QPCIe Board Overview

LimeSDR-QPCIe board version 1.2 picture with highlighted major connectors presented in Figure 2. There are three connector types – data and debugging (PCIe, USB3.0, PMOD, LVDS and JTAG), power (DC jack and external supply pinheaders) and high frequency (RF and reference clock).

Figure 2 LimeSDR-QPCIe v1.2 Development Board Connectors


Board components description listed in the Table 1.

Table 1. Board components
Featured Devices
Board Reference Type Description
IC1, IC2 FPRF Field programmable RF transceivers LMS7002M
IC8 FPGA Altera Cyclone V GX, 5CGXFC7D7F31C8N, 896-BGA
IC13 USB3.0 microcontroller Cypress FX3 Supper Speed USB 3rd generation controller CYUSB3013
Miscellaneous devices on board
IC7, IC8 IC 8-bit shift registers 74HC595BQ,115
IC9, IC49 IC Bidirectional voltage shifters SN74AVC4T774RSVR
IC10, IC11, IC12, IC13, IC14, IC15, IC16, IC17 IC 100MHz – 3 GHz SPDT RF switches SKY13323-378LF
IC18, IC20, IC23, IC25, IC26, IC28 IC 12-bit ADCs MAX11108AVB+T
IC19, IC24, IC27 IC 1MHz–10GHz dual log detector/controller ADL5519
IC22 IC SP4T RF switch PE42442A-Z
IC31 IC 4 parallel 2:1 switches TS3A5018PWR
IC37 IC 14-bit 2-channel ADC ADS4246IRGCT
IC38 IC Dual differential amplifier ADA4930
IC39, IC56 IC Differential line drivers SN65LVDS1DBVR
IC40, IC41 IC Dual differential DACs DAC5672AIPFB
IC44, IC45 IC Bidirectional 8-channel voltage translators FXLA108BQX
IC47 IC Temperature sensor LM75
IC48 IC GPS receiver module M10578-A3
IC50 IC Real time clock (RTC) DS3231S#
BATT1 Holder Holder for coin cell CR1220 battery
ESD26 TVS USB3.0 ESD protection TVS diode
ESD1, ESD2, ESD3, ESD4, ESD5, ESD6, ESD7, ESD8, ESD9, ESD10, ESD11, ESD12, ESD13, ESD14, ESD15, ESD16, ESD17, ESD18, ESD19, ESD20, ESD21, ESD22, ESD23, ESD24, ESD25 TVS RF connector ESD protection TVS diodes
Configuration, Status and Setup Components
R56, R57, R58, R59 0 Ohm resistor Board BOM version BOM_VER[3:0]. Default BOM_VER=0 (all resistors populated).
R160, R161, R163, R164, R166, R167, R168, R169, R171, R172 0 Ohm resistor FPGA (IC8) MSEL[3:0]. Default mode: Active Serial Standard configuration.
[R268, R271, R275, R279], [R269, R273, R277, R281] 0 Ohm resistor DAC#1 differential channels TX1_BB_I/Q connection selection to either LMS7002M #1 or LMS7002M #2. Default populated group is [R268, R271, R275, R279]. Resistor groups are defined in [] brackets.
[R270, R274, R278, R282], [R272, R276, R280, R283] 0 Ohm resistor DAC#2 differential channels TX2_BB_I/Q connection selection to either LMS7002M #1 or LMS7002M #2. Default populated group is [R270, R274, R278, R282]. Resistor groups are defined in [] brackets.
R364, R379, R384 and their respective power connecting resistors R365, R380, R382 0 Ohm resistor Clock buffer (IC52) CLKin0 (pin 13) clock source selection. R364 and R365 are populated by default.
R368, R372, R374 0 Ohm resistor Clock buffer (IC52) CLKin1 (pin 28) clock source selection. R374 is populated by default.
R375 0 Ohm resistor Clock buffer (IC52) source (CLKin0 or CLKin1) selection. If unpopulated, clock source is CLKin0 (default). If populated, clock source is CLKin1.
R302, R305, R307 10 kOhm resistor USB3.0 microcontroller (IC13) boot configuration (PMODE0[2:0]) resistors. Default mode: SPI boot, On Failure - USB Boot
R294, R296, R298 10 kOhm resistor USB3.0 microcontroller (IC13) crystal/clock frequency selection (FSLC[2:0]) resistors. Default mode: 19.2MHz crystal
J28, R313 Pin header, 0 Ohm resistor USB3.0 microcontroller (IC13) boot source (Flash memory or USB), 0.1” pitch jumper or 0402 0R resistor. In normal operation jumper or resistor must be placed.
J29 JTAG chain pin header USB3.0 microcontroller (IC13) debugging pin header, 0.05” pitch
SW1 Push-button USB3.0 microcontroller reset button
J26 JTAG chain pin header FPGA programming pin header for Altera USB-Blaster download cable, 0.1” pitch
LED1 Green status LED FPGA configuration done LED
LED2-LED5 Green status LEDs User defined general purpose green LEDs
LED6 Red-green status LED User defined general purpose dual colour LED
General User Input/Output
J31, J32 Connector 0.1” PMOD connectors
SW2 Switch 4-bit FPGA switch
J33 Pin header Board cooling fan pin header, 0.1”
Memory Devices
IC3, IC5, IC51 EEPROM 128Kbit (16K x 8) EEPROM, LMS7002 MCU firmware and general purpose memory
IC4, IC6 EEPROM 512Kbit (64K x 8) EEPROM, connected to main I2C bus
IC30 Flash memory 128Mbit (16M x 8) Flash for FPGA configuration (unpopulated)
IC32 Flash memory 128Mbit (16M x 8) Flash for FPGA configuration
IC33, IC34, IC35, IC36 DDR3 memory 2Gbit (128M x 16) DDR3 SDRAM
Communication Ports
J27 USB3.0 connector microUSB3.0 (type B) connector
P1 PCIe connector PCI Express (Gen1) x4 connector
Clock Circuitry
XO1 VCOCXO 10MHz voltage- and oven-controlled crystal oscillator
XO2, XO3 VCTCXO 30.72MHz voltage-controlled crystal oscillator
XO4 VCTCXO 40MHz voltage-controlled crystal oscillator
IC57 IC Programmable clock generator for the FPGA reference clock input and RF boards
IC53 IC ADF4002 phase detector
IC54 IC 16-bit DAC for VCTCXO/VCOCXO frequency tuning
IC52 IC Clock buffer
IC55 IC Clock buffer
J36 U.FL connector Reference clock input
J35 U.FL connector Reference clock output
XO5 Crystal oscillator 100MHz single-ended FPGA clock
XO6 Crystal oscillator 125MHz single-ended FPGA clock
XO7 Crystal oscillator 125MHz differential FPGA-DDR clock
XO8 Crystal oscillator 125MHz differential FPGA-DDR clock
XO9 Crystal oscillator 125MHz differential FPGA clock for PCIe REFCLK1
IC56 IC Single-ended to differential clock converter. Clock source is IC57 pin 9. Connected to FPGA PCIe REFCLK2 and LVDS connector J30.
Power Supply
J37 DC input jack External 12V DC power supply
J38 Header 6-pin PCIe power connector, 0.165” pitch
J39 Pin header External 12V DC power supply and main internal power rail

LimeSDR-QPCIe board version 1.2 picture with highlighted top components are presented in Figure 3.

Figure 3 LimeSDR-QPCIe Development Board Top Components


LimeSDR-QPCIe board version 1.2 picture with highlighted bottom components is presented in Figure 4.

Figure 4 LimeSDR-QPCIe Development Board Bottom Components

LimeSDR-QPCIe Board Architecture

The heart of the LimeSDR-QPCIe board is Altera Cyclone V GX FPGA. Its main function is to transfer digital data between the PC through an edge PCIE and a USB3.0 connector. The block diagram for LimeSDR-QPCIe board is presented in the Figure 5.

Figure 5 LimeSDR-QPCIe v1.2 Block Diagram

FPGA configuration

FPGA is set to use x1 Active Serial (AS) configuration scheme. In this scheme if valid configuration file exists in FLASH memory (IC30 or IC32) it is automatically loaded after power is applied to the board. In Table 2 it is listed resistor setup for Active Serial (AS) configuration mode select.

Table 2 FPGA configuration setup (AS)
Schematic signal name Logic level 0R Resistor setup
MSEL0 H R160 (NF) R161 (Fit)
MSEL1 H R163 (NF) R164 (Fit)
MSEL2 L R166 (Fit) R167 (NF)
MSEL3 L R168 (Fit) R169 (NF)
MSEL4 H R171 (NF) R172 (Fit)

There are two options which allows to change configuration file in FLASH memory:

  • USB 3.0 controller – CYUSB3013 (IC42) has access to configuration memory. With valid firmware and software, gateware for FPGA can be uploaded into FLASH memory (IC30 or IC32) by using USB3.0 cable. IC42 can initiate FPGA reconfiguration. For signal interconnect details see chapter 2.2.2.3 USB 3.0 Controller.
  • JTAG Header – 10pin connector (J26) provides access to FPGA JTAG chain. By using external download cable such as USB-Blaster and Quartus II Programmer software FLASH memory (IC30 or IC32) can be reprogrammed. JTAG connections are listed in Table 3.
Table 3 JTAG header (J26)
Connector pin Schematic signal name FPGA pin (IC29) Comment
1 FPGA_JTAG_TCK AC7 R170 Pull-Down resistor
2 VCC2P5 -
3 FPGA_JTAG_TDO W9
4 VCC2P5 -
5 FPGA_JTAG_TMS V7 R162 Pull-Up resistor
6 - -
7 - -
8 - -
9 FPGA_JTAG_TDI U7 R165 Pull-Up resistor
10 GND -

Main components

This chapter describes main components mounted on LimeSDR-QPCIe v1.2 board.

LMS7002M RF transceiver

There are two LMS7002M field programmable RF transceiver ICs (LMS7002M#1 - IC1 and LMS7002M#1 - IC2), interface signals can be acknowledged by corresponding names LMSx_*, where x can be 1 or 2. For example LMS1_* signals belongs to IC1 and LMS2_* belongs to IC2.

In the following manner interface and control signals are described below:

  • Digital Interface Signals: LMS7002 is using data bus LMSx_DIQ1_D[11:0] and LMSx_DIQ2_D[11:0], LMSx_ENABLE_IQSEL1 and LMSx_ENABLE_IQSEL2, LMSx_FCLK1 and LMSx_FCLK2, LMSx_MCLK1 and LMSx_MCLK2 signals to transfer data to/from FPGA. Indexes 1 and 2 indicate transceiver digital data PORT-1 or PORT-2. Any of these ports can be used to transmit or receive data. By default, PORT-1 is selected as receive port and PORT-2 is selected as transmit port. The FCLK# is input clock and MCLK# is output clock for LMS7002M transceiver. TXNRX signals sets ports directions. For LMS7002M interface timing details refer to LMS7002M transceiver datasheet page 12-13 [1].
  • LMS Control Signals: these signals are used for optional functionality:
    • LMSx_RXEN, LMSx_TXEN – receiver and transmitter enable/disable signals.
    • LMS_RESET – LMS7002M reset signal.
  • SPI Interface: LMS7002M transceiver is configured via 4-wire SPI interface; FPGA_SPI0_SCLK, FPGA_SPI0_MOSI, FPGA_SPI0_MISO_LMSx, FPGA_SPI0_LMSx_SS. The SPI interface controlled from FPGA.
  • LMS I2C Interface: LMS EEPROM are connected to this interface. The signals LMSx_I2C_SCL, LMSx_I2C_DATA is not connected to FPGA


The Table 4 and Table 5below lists RF transceiver respectively LMS7002#1 and LMS7002#2 pins, schematic signal names, FPGA interconnections and I/O standard.

Table 4 RF transceiver (LMS7002M#1) digital interface pins
Chip pin (IC1) Chip reference (IC1) Schematic signal name FPGA pin FPGA I/O standard Comments
AM24 xoscin_rx LMS1_RxPLL_CLK NC 3.3V Connected to 30.72 MHz clock
P34 MCLK2 LMS1_MCLK2 U21 2.5V/3.3V
R29 FCLK2 LMS1_FCLK2 Y22 2.5V/3.3V
U31 TXNRX2 LMS1_TXNRX2 U26 2.5V/3.3V
V34 RXEN LMS1_RXEN Y26 2.5V/3.3V
R33 ENABLE_IQSEL2 LMS1_ENABLE_IQSEL2 AA26 2.5V/3.3V
H30 DIQ2_D0 LMS1_DIQ2_D0 AC27 2.5V/3.3V
J31 DIQ2_D1 LMS1_DIQ2_D1 AB27 2.5V/3.3V
K30 DIQ2_D2 LMS1_DIQ2_D2 Y21 2.5V/3.3V
K32 DIQ2_D3 LMS1_DIQ2_D3 AA29 2.5V/3.3V
L31 DIQ2_D4 LMS1_DIQ2_D4 Y28 2.5V/3.3V
K34 DIQ2_D5 LMS1_DIQ2_D5 AC26 2.5V/3.3V
M30 DIQ2_D6 LMS1_DIQ2_D6 W27 2.5V/3.3V
M32 DIQ2_D7 LMS1_DIQ2_D7 AA25 2.5V/3.3V
N31 DIQ2_D8 LMS1_DIQ2_D8 V26 2.5V/3.3V
N33 DIQ2_D9 LMS1_DIQ2_D9 AH29 2.5V/3.3V
P30 DIQ2_D10 LMS1_DIQ2_D10 V27 2.5V/3.3V
P32 DIQ2_D11 LMS1_DIQ2_D11 W28 2.5V/3.3V
E5 xoscin_tx LMS1_TxPLL_CLK NC 3.3V Connected to 30.72 MHz clock
AB34 MCLK1 LMS1_MCLK1 U22 2.5V/3.3V
AA33 FCLK1 LMS1_FCLK1 Y30 2.5V/3.3V
V32 TXNRX1 LMS1_TXNRX1 U27 2.5V/3.3V
U29 TXEN LMS1_TXEN V21 2.5V/3.3V
Y32 ENABLE_IQSEL1 LMS1_ENABLE_IQSEL1 U28 2.5V/3.3V
AG31 DIQ1_D0 LMS1_DIQ1_D0 T28 2.5V/3.3V
AF30 DIQ1_D1 LMS1_DIQ1_D1 Y23 2.5V/3.3V
AF34 DIQ1_D2 LMS1_DIQ1_D2 AB28 2.5V/3.3V
AE31 DIQ1_D3 LMS1_DIQ1_D3 T29 2.5V/3.3V
AD30 DIQ1_D4 LMS1_DIQ1_D4 AA23 2.5V/3.3V
AC29 DIQ1_D5 LMS1_DIQ1_D5 V22 2.5V/3.3V
AE33 DIQ1_D6 LMS1_DIQ1_D6 V24 2.5V/3.3V
AD32 DIQ1_D7 LMS1_DIQ1_D7 Y27 2.5V/3.3V
AC31 DIQ1_D8 LMS1_DIQ1_D8 AC24 2.5V/3.3V
AC33 DIQ1_D9 LMS1_DIQ1_D9 V25 2.5V/3.3V
AB30 DIQ1_D10 LMS1_DIQ1_D10 W22 2.5V/3.3V
AB32 DIQ1_D11 LMS1_DIQ1_D11 AA24 2.5V/3.3V
U33 CORE_LDO_EN LMS1_CORE_LDO_EN Y25 2.5V/3.3V
E27 RESET LMS1_RESET L21 2.5V/3.3V
D28 SEN FPGA_SPI0_LMS1_SS V29 2.5V/3.3V SPI interface
C29 SCLK FPGA_SPI0_SCLK T25 2.5V/3.3V SPI interface
F30 SDIO FPGA_SPI0_MOSI R26 2.5V/3.3V SPI interface
F28 SDO FPGA_SPI0_MISO_LMS1 R30 2.5V/3.3V SPI interface
D26 SDA LMS1_I2C_SDA - 2.5V Connected to EEPROM
C27 SCL LMS1_I2C_SCL - 2.5V Connected to EEPROM
AM24 ||xoscin_rx ||LMS2_RxPLL_CLK ||NC ||3.3V ||Connected to 30.72 MHz clock
Table 5 RF transceiver (LMS7002M#2) digital interface pins
Chip pin (IC2) Chip reference (IC2) Schematic signal name FPGA pin FPGA I/O standard Comments
P34 MCLK2 LMS2_MCLK2 U23 2.5V/3.3V
R29 FCLK2 LMS2_FCLK2 AC29 2.5V/3.3V
U31 TXNRX2 LMS2_TXNRX2 AC30 2.5V/3.3V
V34 RXEN LMS2_RXEN AE25 2.5V/3.3V
R33 ENABLE_IQSEL2 LMS2_ENABLE_IQSEL2 AF25 2.5V/3.3V
H30 DIQ2_D0 LMS2_DIQ2_D0 AA28 2.5V/3.3V
J31 DIQ2_D1 LMS2_DIQ2_D1 AJ30 2.5V/3.3V
K30 DIQ2_D2 LMS2_DIQ2_D2 AB29 2.5V/3.3V
K32 DIQ2_D3 LMS2_DIQ2_D3 AD24 2.5V/3.3V
L31 DIQ2_D4 LMS2_DIQ2_D4 AG28 2.5V/3.3V
K34 DIQ2_D5 LMS2_DIQ2_D5 AG27 2.5V/3.3V
M30 DIQ2_D6 LMS2_DIQ2_D6 AB26 2.5V/3.3V
M32 DIQ2_D7 LMS2_DIQ2_D7 AF24 2.5V/3.3V
N31 DIQ2_D8 LMS2_DIQ2_D8 AH30 2.5V/3.3V
N33 DIQ2_D9 LMS2_DIQ2_D9 AE23 2.5V/3.3V
P30 DIQ2_D10 LMS2_DIQ2_D10 AG29 2.5V/3.3V
P32 DIQ2_D11 LMS2_DIQ2_D11 AE26 2.5V/3.3V
E5 xoscin_tx LMS2_TxPLL_CLK NC 3.3V Connected to 30.72 MHz clock
AB34 MCLK1 LMS2_MCLK1 T24 2.5V/3.3V
AA33 FCLK1 LMS2_FCLK1 W30 2.5V/3.3V
V32 TXNRX1 LMS2_TXNRX1 AF28 2.5V/3.3V
U29 TXEN LMS2_TXEN AD27 2.5V/3.3V
Y32 ENABLE_IQSEL1 LMS2_ENABLE_IQSEL1 AF29 2.5V/3.3V
AG31 DIQ1_D0 LMS2_DIQ1_D0 AD25 2.5V/3.3V
AF30 DIQ1_D1 LMS2_DIQ1_D1 AD29 2.5V/3.3V
AF34 DIQ1_D2 LMS2_DIQ1_D2 AH27 2.5V/3.3V
AE31 DIQ1_D3 LMS2_DIQ1_D3 AE30 2.5V/3.3V
AD30 DIQ1_D4 LMS2_DIQ1_D4 AE28 2.5V/3.3V
AC29 DIQ1_D5 LMS2_DIQ1_D5 AD30 2.5V/3.3V
AE33 DIQ1_D6 LMS2_DIQ1_D6 AJ28 2.5V/3.3V
AD32 DIQ1_D7 LMS2_DIQ1_D7 AF26 2.5V/3.3V
AC31 DIQ1_D8 LMS2_DIQ1_D8 AE27 2.5V/3.3V
AC33 DIQ1_D9 LMS2_DIQ1_D9 AJ29 2.5V/3.3V
AB30 DIQ1_D10 LMS2_DIQ1_D10 AD28 2.5V/3.3V
AB32 DIQ1_D11 LMS2_DIQ1_D11 AF30 2.5V/3.3V
U33 CORE_LDO_EN LMS2_CORE_LDO_EN AD23 2.5V/3.3V
E27 RESET LMS2_RESET AA30 2.5V/3.3V
D28 SEN FPGA_SPI0_LMS2_SS U29 2.5V/3.3V SPI interface
C29 SCLK FPGA_SPI0_SCLK T25 2.5V/3.3V SPI interface
F30 SDIO FPGA_SPI0_MOSI R26 2.5V/3.3V SPI interface
F28 SDO FPGA_SPI0_MISO_LMS2 V30 2.5V/3.3V SPI interface
D26 SDA LMS2_I2C_SDA - 2.5V Connected to EEPROM
C27 SCL LMS2_I2C_SCL - 2.5V Connected to EEPROM
SDRAM

LimeSDR-QPCIe board has four 2Gb DDR3 SDRAM memory ICs (AS4C128M16D3B-12BCN [link]) which are connected to Cyclone V GX FPGA. The memory can be used for data manipulation at high data rates between transceiver and FPGA. There are two independent DDR3 SDRAM interfaces:

  • DDR3 TOP – this is 32bit data interface which consist of two x16 memory devices (IC33 AND IC34) with a single address and command bus. Interface is connected to FPGA Bank 7A and 8A and uses hard memory controller. Error! Reference source not found. lists DDR3 TOP interface pins.
  • DDR3 BOT – this is 32bit data interface which consist of two x16 memory devices (IC35 AND IC36) with a single address and command bus. Interface is connected to FPGA Bank 3B and 4A and uses hard memory controller. lists DDR3 BOT interface pins.


Following Table 6 lists signal and pin information for DDR3 TOP interface and Table 7 for the DDR3 BOT interface.

Table 6 DDR3 TOP interface pins
RAM reference RAM pin Schematic signal name FPGA pin (IC29) FPGA I/O standard Comments
Address bus (IC33 and IC34 shared signals)
A0 N3 DDR3_TOP_A0 B11 SSTL-15 Class I Active termination
A1 P7 DDR3_TOP_A1 A11 SSTL-15 Class I Active termination
A2 P3 DDR3_TOP_A2 F9 SSTL-15 Class I Active termination
A3 N2 DDR3_TOP_A3 E10 SSTL-15 Class I Active termination
A4 P8 DDR3_TOP_A4 F16 SSTL-15 Class I Active termination
A5 P2 DDR3_TOP_A5 E16 SSTL-15 Class I Active termination
A6 R8 DDR3_TOP_A6 D9 SSTL-15 Class I Active termination
A7 R2 DDR3_TOP_A7 C10 SSTL-15 Class I Active termination
A8 T8 DDR3_TOP_A8 E12 SSTL-15 Class I Active termination
A9 R3 DDR3_TOP_A9 D13 SSTL-15 Class I Active termination
A10/AP L7 DDR3_TOP_A10 B7 SSTL-15 Class I Active termination
A11 R7 DDR3_TOP_A11 A8 SSTL-15 Class I Active termination
A12/BC# N7 DDR3_TOP_A12 B6 SSTL-15 Class I Active termination
A13 T3 DDR3_TOP_A13 A6 SSTL-15 Class I Active termination
Bank address bus (IC33 and IC34 shared signals)
BA0 M2 DDR3_TOP_BA0 A10 SSTL-15 Class I Active termination
BA1 N8 DDR3_TOP_BA1 F15 SSTL-15 Class I Active termination
BA2 M3 DDR3_TOP_BA2 E15 SSTL-15 Class I Active termination
Data bus [0:15] (IC33)
DQ0 E3 DDR3_TOP_DQ0 C15 SSTL-15 Class I
DQ1 F7 DDR3_TOP_DQ1 C16 SSTL-15 Class I
DQ2 F2 DDR3_TOP_DQ2 C11 SSTL-15 Class I
DQ3 F8 DDR3_TOP_DQ3 A13 SSTL-15 Class I
DQ4 H3 DDR3_TOP_DQ4 D17 SSTL-15 Class I
DQ5 H8 DDR3_TOP_DQ5 E17 SSTL-15 Class I
DQ6 G2 DDR3_TOP_DQ6 D12 SSTL-15 Class I
DQ7 H7 DDR3_TOP_DQ7 A14 SSTL-15 Class I
DQ8 D7 DDR3_TOP_DQ8 B17 SSTL-15 Class I
DQ9 C3 DDR3_TOP_DQ9 C17 SSTL-15 Class I
DQ10 C8 DDR3_TOP_DQ10 A16 SSTL-15 Class I
DQ11 C2 DDR3_TOP_DQ11 C14 SSTL-15 Class I
DQ12 A7 DDR3_TOP_DQ12 F18 SSTL-15 Class I
DQ13 A2 DDR3_TOP_DQ13 G18 SSTL-15 Class I
DQ14 B8 DDR3_TOP_DQ14 B18 SSTL-15 Class I
DQ15 A3 DDR3_TOP_DQ15 A19 SSTL-15 Class I
Data bus [16:31] (IC34)
DQ0 E3 DDR3_TOP_DQ16 D18 SSTL-15 Class I
DQ1 F7 DDR3_TOP_DQ17 D19 SSTL-15 Class I
DQ2 F2 DDR3_TOP_DQ18 A21 SSTL-15 Class I
DQ3 F8 DDR3_TOP_DQ19 B21 SSTL-15 Class I
DQ4 H3 DDR3_TOP_DQ20 E18 SSTL-15 Class I
DQ5 H8 DDR3_TOP_DQ21 F19 SSTL-15 Class I
DQ6 G2 DDR3_TOP_DQ22 B23 SSTL-15 Class I
DQ7 H7 DDR3_TOP_DQ23 B24 SSTL-15 Class I
DQ8 D7 DDR3_TOP_DQ24 C19 SSTL-15 Class I
DQ9 C3 DDR3_TOP_DQ25 D20 SSTL-15 Class I
DQ10 C8 DDR3_TOP_DQ26 A25 SSTL-15 Class I
DQ11 C2 DDR3_TOP_DQ27 D22 SSTL-15 Class I
DQ12 A7 DDR3_TOP_DQ28 C20 SSTL-15 Class I
DQ13 A2 DDR3_TOP_DQ29 C21 SSTL-15 Class I
DQ14 B8 DDR3_TOP_DQ30 D23 SSTL-15 Class I
DQ15 A3 DDR3_TOP_DQ31 C25 SSTL-15 Class I
Data mask[0:1] (IC33)
LDM E7 DDR3_TOP_DM0 B14 SSTL-15 Class I
UDM D3 DDR3_TOP_DM1 B19 SSTL-15 Class I
Data mask[2:3] (IC34)
LDM E7 DDR3_TOP_DM2 C24 SSTL-15 Class I
UDM D3 DDR3_TOP_DM3 D25 SSTL-15 Class I
Data strobe[0:1] (IC33)
LDQS G3 DDR3_TOP_DQS0_P K17 Differential 1.5-V SSTL Class I
LDQS# F3 DDR3_TOP_DQS0_N J17 Differential 1.5-V SSTL Class I
UDQS C7 DDR3_TOP_DQS1_P K16 Differential 1.5-V SSTL Class I
UDQS# B7 DDR3_TOP_DQS1_N L16 Differential 1.5-V SSTL Class I
Data strobe[2:3] (IC34)
LDQS G3 DDR3_TOP_DQS2_P L18 Differential 1.5-V SSTL Class I
LDQS# F3 DDR3_TOP_DQS2_N K18 Differential 1.5-V SSTL Class I
UDQS C7 DDR3_TOP_DQS3_P K20 Differential 1.5-V SSTL Class I
UDQS# B7 DDR3_TOP_DQS3_N J19 Differential 1.5-V SSTL Class I
Memory clock (IC33 and IC34 shared signals)
CK# K7 DDR3_TOP_CK_N M8 Differential 1.5-V SSTL Class I
CK J7 DDR3_TOP_CK_P M9 Differential 1.5-V SSTL Class I
Control signals(IC33 and IC34 shared signals)
CKE K9 DDR3_TOP_CKE A18 SSTL-15 Class I
WE# L3 DDR3_TOP_WEn C7 SSTL-15 Class I Active termination
CAS# K3 DDR3_TOP_CASn C9 SSTL-15 Class I Active termination
RAS# J3 DDR3_TOP_RASn B8 SSTL-15 Class I Active termination
CS# L2 DDR3_TOP_CSn J15 SSTL-15 Class I Active termination
ODT K1 DDR3_TOP_ODT B13 SSTL-15 Class I Active termination
RESET# T2 DDR3_TOP_RESETn B22 1.5V Active termination
VREF (IC33 and IC34 shared signals)
VREFDQ H1 VREF_DDR3_TOP -
VREFCA M8 VREF_DDR3_TOP -
Memory ZQ impedance calibration (IC33)
ZQ L8 DDR3_TOP_RZQ0 -
Memory ZQ impedance calibration (IC34)
ZQ L8 DDR3_TOP_RZQ1 -
FPGA OCT calibration pin
- - OCT_RZQIN1 B12 SSTL-15
Table 7 DDR3 BOT interface pins
RAM reference RAM pin Schematic signal name FPGA pin (IC29) FPGA I/O standard Comments
Address bus (IC35 and IC36 shared signals)
A0 N3 DDR3_BOT_A0 AJ12 SSTL-15 Class I Active termination
A1 P7 DDR3_BOT_A1 AK12 SSTL-15 Class I Active termination
A2 P3 DDR3_BOT_A2 AH11 SSTL-15 Class I Active termination
A3 N2 DDR3_BOT_A3 AH12 SSTL-15 Class I Active termination
A4 P8 DDR3_BOT_A4 AG13 SSTL-15 Class I Active termination
A5 P2 DDR3_BOT_A5 AG14 SSTL-15 Class I Active termination
A6 R8 DDR3_BOT_A6 AK10 SSTL-15 Class I Active termination
A7 R2 DDR3_BOT_A7 AK11 SSTL-15 Class I Active termination
A8 T8 DDR3_BOT_A8 AF11 SSTL-15 Class I Active termination
A9 R3 DDR3_BOT_A9 AG11 SSTL-15 Class I Active termination
A10/AP L7 DDR3_BOT_A10 AJ8 SSTL-15 Class I Active termination
A11 R7 DDR3_BOT_A11 AK8 SSTL-15 Class I Active termination
A12/BC# N7 DDR3_BOT_A12 AJ7 SSTL-15 Class I Active termination
A13 T3 DDR3_BOT_A13 AK7 SSTL-15 Class I Active termination
Bank address bus (IC35 and IC36 shared signals)
BA0 M2 DDR3_BOT_BA0 AH9 SSTL-15 Class I Active termination
BA1 N8 DDR3_BOT_BA1 AH10 SSTL-15 Class I Active termination
BA2 M3 DDR3_BOT_BA2 AJ10 SSTL-15 Class I Active termination
Data bus [0:15] (IC35)
DQ0 E3 DDR3_BOT_DQ0 AF15 SSTL-15 Class I
DQ1 F7 DDR3_BOT_DQ1 AE16 SSTL-15 Class I
DQ2 F2 DDR3_BOT_DQ2 AJ14 SSTL-15 Class I
DQ3 F8 DDR3_BOT_DQ3 AH15 SSTL-15 Class I
DQ4 H3 DDR3_BOT_DQ4 AE17 SSTL-15 Class I
DQ5 H8 DDR3_BOT_DQ5 AD17 SSTL-15 Class I
DQ6 G2 DDR3_BOT_DQ6 AJ15 SSTL-15 Class I
DQ7 H7 DDR3_BOT_DQ7 AF14 SSTL-15 Class I
DQ8 D7 DDR3_BOT_DQ8 AK17 SSTL-15 Class I
DQ9 C3 DDR3_BOT_DQ9 AK16 SSTL-15 Class I
DQ10 C8 DDR3_BOT_DQ10 AG17 SSTL-15 Class I
DQ11 C2 DDR3_BOT_DQ11 AJ18 SSTL-15 Class I
DQ12 A7 DDR3_BOT_DQ12 AG16 SSTL-15 Class I
DQ13 A2 DDR3_BOT_DQ13 AF16 SSTL-15 Class I
DQ14 B8 DDR3_BOT_DQ14 AJ19 SSTL-15 Class I
DQ15 A3 DDR3_BOT_DQ15 AH20 SSTL-15 Class I
Data bus [16:31] (IC36)
DQ0 E3 DDR3_BOT_DQ16 AE18 SSTL-15 Class I
DQ1 F7 DDR3_BOT_DQ17 AD18 SSTL-15 Class I
DQ2 F2 DDR3_BOT_DQ18 AJ20 SSTL-15 Class I
DQ3 F8 DDR3_BOT_DQ19 AK22 SSTL-15 Class I
DQ4 H3 DDR3_BOT_DQ20 AF19 SSTL-15 Class I
DQ5 H8 DDR3_BOT_DQ21 AF18 SSTL-15 Class I
DQ6 G2 DDR3_BOT_DQ22 AH21 SSTL-15 Class I
DQ7 H7 DDR3_BOT_DQ23 AK23 SSTL-15 Class I
DQ8 D7 DDR3_BOT_DQ24 AG19 SSTL-15 Class I
DQ9 C3 DDR3_BOT_DQ25 AG18 SSTL-15 Class I
DQ10 C8 DDR3_BOT_DQ26 AH24 SSTL-15 Class I
DQ11 C2 DDR3_BOT_DQ27 AK25 SSTL-15 Class I
DQ12 A7 DDR3_BOT_DQ28 AE20 SSTL-15 Class I
DQ13 A2 DDR3_BOT_DQ29 AD19 SSTL-15 Class I
DQ14 B8 DDR3_BOT_DQ30 AG24 SSTL-15 Class I
DQ15 A3 DDR3_BOT_DQ31 AK26 SSTL-15 Class I
Data mask[0:1] (IC35)
LDM E7 DDR3_BOT_DM0 AE15 SSTL-15 Class I
UDM D3 DDR3_BOT_DM1 AH19 SSTL-15 Class I
Data mask[2:3] (IC36)
LDM E7 DDR3_BOT_DM2 AJ23 SSTL-15 Class I
UDM D3 DDR3_BOT_DM3 AJ27 SSTL-15 Class I
Data strobe[0:1] (IC35)
LDQS G3 DDR3_BOT_DQS0_P Y16 Differential 1.5-V SSTL Class I
LDQS# F3 DDR3_BOT_DQS0_N AA16 Differential 1.5-V SSTL Class I
UDQS C7 DDR3_BOT_DQS1_P Y17 Differential 1.5-V SSTL Class I
UDQS# B7 DDR3_BOT_DQS1_N Y18 Differential 1.5-V SSTL Class I
Data strobe[2:3] (IC36)
LDQS G3 DDR3_BOT_DQS2_P Y20 Differential 1.5-V SSTL Class I
LDQS# F3 DDR3_BOT_DQS2_N AA20 Differential 1.5-V SSTL Class I
UDQS C7 DDR3_BOT_DQS3_P AB19 Differential 1.5-V SSTL Class I
UDQS# B7 DDR3_BOT_DQS3_N AC19 Differential 1.5-V SSTL Class I
Memory clock (IC35 and IC36 shared signals)
CK# K7 DDR3_BOT_CK_N AA14 Differential 1.5-V SSTL Class I
CK J7 DDR3_BOT_CK_P Y13 Differential 1.5-V SSTL Class I
Control signals(IC35 and IC36 shared signals)
sCKE K9 DDR3_BOT_CKE AK18 SSTL-15 Class I
WE# L3 DDR3_BOT_WEn AK5 SSTL-15 Class I Active termination
CAS# K3 DDR3_BOT_CASn AF9 SSTL-15 Class I Active termination
RAS# J3 DDR3_BOT_RASn AG9 SSTL-15 Class I Active termination
CS# L2 DDR3_BOT_CSn Y12 SSTL-15 Class I Active termination
ODT K1 DDR3_BOT_ODT AH14 SSTL-15 Class I Active termination
RESET# T2 DDR3_BOT_RESETn AK21 1.5V Active termination
VREF (IC35 and IC36 shared signals)
VREFDQ H1 VREF_DDR3_BOT -
VREFCA M8 VREF_DDR3_BOT -
Memory ZQ impedance calibration (IC35)
ZQ L8 DDR3_BOT_RZQ0 -
Memory ZQ impedance calibration (IC36)
ZQ L8 DDR3_BOT_RZQ1 -
FPGA OCT calibration pin
- - OCT_RZQIN0 AK13 SSTL-15
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