https://wiki.myriadrf.org/api.php?action=feedcontributions&user=VytautasBuitvydas&feedformat=atomMyriad-RF Wiki - User contributions [en]2024-03-28T12:47:04ZUser contributionsMediaWiki 1.40.1https://wiki.myriadrf.org/index.php?title=Connecting_LimeNET-Micro_v2.1_to_USB_Host&diff=2293Connecting LimeNET-Micro v2.1 to USB Host2019-04-15T06:30:56Z<p>VytautasBuitvydas: /* Quick start */</p>
<hr />
<div>= Introduction =<br />
<br />
LimeNET-Micro v2.1 can be connected to USB2.0 host and used as a Software Defined Radio like [https://wiki.myriadrf.org/LimeSDR-Mini LimeSDR-Mini] but with reduced sample rate due to USB2.0 connection. <br />
<br />
<br />
= Quick start = <br />
<br />
* Remove '''J14''' and install '''J18''' jumper. For additional info see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#USB_subsystem 3.3 USB subsystem] of [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description].<br />
* Set power selection jumper '''J27''' to "A-USB external" position. Note that in application where LimeNET-Micro v2.1 board requires more power than USB2.0 can supply external power supply has to be used. For additional info for power options see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#Power_Distribution 3.12 Power distribution] of [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description].<br />
* Connect microUSB cable to '''J15''' connector.<br />
* Install drivers, see chapter [https://wiki.myriadrf.org/LimeNET_Micro#USB_Drivers 5 USB Drivers ]<br />
* Connect to software, see chapter [https://wiki.myriadrf.org/LimeNET_Micro#Software 6 software]<br />
<br />
<br />
[[File:LimeNET-Micro_v2.1_diagrams v05 USB2 Host.png|center|thumb|550px| Connecting LimeNET-Micro v2.1 to USB host ]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Connecting_LimeNET-Micro_v2.1_to_USB_Host&diff=2292Connecting LimeNET-Micro v2.1 to USB Host2019-04-15T06:29:16Z<p>VytautasBuitvydas: /* Quick start */</p>
<hr />
<div>= Introduction =<br />
<br />
LimeNET-Micro v2.1 can be connected to USB2.0 host and used as a Software Defined Radio like [https://wiki.myriadrf.org/LimeSDR-Mini LimeSDR-Mini] but with reduced sample rate due to USB2.0 connection. <br />
<br />
<br />
= Quick start = <br />
<br />
* Remove '''J14''' and install '''J18''' jumper. For additional info see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#USB_subsystem 3.3 USB subsystem] of [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description].<br />
* Set power selection jumper '''J27''' to "A-USB external" position. Note that in application where LimeNET-Micro v2.1 board requires more power than USB2.0 can supply external power supply has to be used. For additional info for power options see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#Power_Distribution 3.12 Power distribution] of [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description].<br />
* Connect microUSB cable to '''J15''' connector.<br />
* Install drivers, see chapter [https://wiki.myriadrf.org/LimeNET_Micro#USB_Drivers 5 USB Drivers ]<br />
* Connect to software, see chapter [https://wiki.myriadrf.org/LimeNET_Micro#Software 6 software]<br />
<br />
[[File:LimeNET-Micro_v2.1_diagrams v05 USB2 Host.png|center|550px|Connecting LimeNET-Micro v2.1 to USB host ]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:LimeNET-Micro_v2.1_diagrams_v05_USB2_Host.png&diff=2291File:LimeNET-Micro v2.1 diagrams v05 USB2 Host.png2019-04-15T06:28:56Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Connecting_LimeNET-Micro_v2.1_to_USB_Host&diff=2283Connecting LimeNET-Micro v2.1 to USB Host2019-04-12T14:59:42Z<p>VytautasBuitvydas: Created page with "= Introduction = LimeNET-Micro v2.1 can be connected to USB2.0 host and used as a Software Defined Radio like [https://wiki.myriadrf.org/LimeSDR-Mini LimeSDR-Mini] but with r..."</p>
<hr />
<div>= Introduction =<br />
<br />
LimeNET-Micro v2.1 can be connected to USB2.0 host and used as a Software Defined Radio like [https://wiki.myriadrf.org/LimeSDR-Mini LimeSDR-Mini] but with reduced sample rate due to USB2.0 connection. <br />
<br />
<br />
= Quick start = <br />
<br />
* Remove '''J14''' and install '''J18''' jumper. For additional info see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#USB_subsystem 3.3 USB subsystem] of [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description].<br />
* Set power selection jumper '''J27''' to "A-USB external" position. Note that in application where LimeNET-Micro v2.1 board requires more power than USB2.0 can supply external power supply has to be used. For additional info for power options see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#Power_Distribution 3.12 Power distribution] of [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description].<br />
* Connect microUSB cable to '''J15''' connector.<br />
* Install drivers, see chapter [https://wiki.myriadrf.org/LimeNET_Micro#USB_Drivers 5 USB Drivers ]<br />
* Connect to software, see chapter [https://wiki.myriadrf.org/LimeNET_Micro#Software 6 software]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET_Micro&diff=2281LimeNET Micro2019-04-12T14:29:53Z<p>VytautasBuitvydas: /* Documentation */</p>
<hr />
<div>== LimeNET-Micro Board ==<br />
<br />
LimeNET Micro makes deploying wireless networks more accessible than ever before, by extending the LimeNET line of integrated hardware solutions via an ultra-low cost platform that is capable of supporting narrowband systems, such as GSM and IoT wireless standards, in a stand-alone configuration.<br />
LimeNET-Micro v2.1 board<br />
<br />
[[File:LimeSDR-Micro_v2.1_board.png|center|550px|LimeNET-Micro v2.1 ]]<br />
<br />
== Features and Specifications ==<br />
<br />
{| class="wikitable"<br />
! Feature !! Description<br />
|-<br />
| RF Transceiver || Lime Microsystems LMS7002M MIMO FPRF<br />
|-<br />
| FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| Raspberry Pi || Raspberry Pi CM3(L)<br />
|-<br />
| USB 2.0 controller || FTDI FT601 (connects FPGA to USB2.0 HUB)<br />
|-<br />
| Oscillator || Rakon U7475LF @30.72MHz<br />
|-<br />
| Continuous frequency range || 10MHz - 3.5 GHz<br />
|-<br />
| Bandwidth || Up to 10 MHz<br />
|-<br />
| RF connection || 2 SMA connectors (2 TRX)<br />
|-<br />
| Power Output (CW) || Up to 10 dbm<br />
|-<br />
| Power Supply || Via PoE, external 5V DC connector or microUSB port<br />
|-<br />
| Status indicators || Programmable LEDs<br />
|-<br />
| Dimensions || without connectors 125mm x 65mm<br />
|}<br />
<br />
== Getting Help ==<br />
<br />
If you have questions, the [https://discourse.myriadrf.org/ MyriadRF Discourse] is a best place to ask for help.<br />
<br />
== Documentation ==<br />
* [[Getting_Started_with_the_LimeNET-Micro | Getting Started with the LimeNET-Micro]]<br />
* [[LimeNET-Micro_v2.1_hardware_description | LimeNET-Micro v2.1 hardware description]]<br />
* [[LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi | LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi]]<br />
* [[Connecting_LimeNET-Micro_v2.1_to_USB_Host | Connecting LimeNET-Micro v2.1 to USB Host]]<br />
* [[LMS7002Mr3_Calibration_Using_MCU|LMS7002M (Mask 1) Transceiver Calibration]] - LMS7002Mr3 calibration guide, using internal MCU<br />
* [[LimeSDR Made Simple]] - Demystifying using SDR in the real world and programming a simple example with confidence, through bite sized chunks (note that not all examples will work with the Mini, e.g. those using the waveform player)<br />
* [https://github.com/myriadrf/LMS7002M-docs/blob/master/LMS7002M_Data_Sheet_v3.1r00.pdf LMS7002M Datasheet (PDF)] - LMS7002M RF transceiver datasheet<br />
* [https://github.com/myriadrf/LMS7002M-docs/blob/master/LMS7002M_Programming_and_Calibration_Guide_v31r05.pdf LMS7002M Programming and Calibration Guide (PDF)] - LMS7002M programming and calibration guide<br />
<br />
== USB Drivers ==<br />
<br />
'''Windows only''', OSX and Linux users do not need to install drivers for USB support.<br />
Follow driver installation instructions in [[LimeSDR-Mini_driver_installation|Driver Installation Documentation]].<br />
<br />
== Software ==<br />
<br />
*[[LimeSuiteGUI|LimeSuiteGUI]]<br />
*[[LimeSDR ExtIO Plugin for HDSDR|LimeSDR ExtIO Plugin for HDSDR]]<br />
*[[Gr-limesdr_Plugin_for_GNURadio|gr-limesdr Plugin for GNURadio]]<br />
<br />
== FPGA Binaries ==<br />
<br />
Here are the links to pre-compiled MCU firmware and FPGA gateware (bitstream):<br />
* FPGA [https://github.com/myriadrf/LimeNet-Micro_GW/blob/FTDI/LimeNET-Micro_bitstreams/LimeNET-Micro_lms7_trx_HW_2.1_auto.rpd gateware]<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
LimeNET-Micro 2.1<br />
<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1/Project%20Outputs%20for%20LimeNet-Micro_2v1-SDR/LimeNET-Micro_2v1-SDR_Schematic_r2.PDF Schematic (PDF)]<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1 PCB project (Altium project)]<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1/Project%20Outputs%20for%20LimeNet-Micro_2v1-SDR/BOM/LimeNET-Micro_2v1_SDR_BOMr2.xls BOM (XLS)]<br />
<br />
== Additional Components ==<br />
<br />
Here is a list of additional components to be used with LimeNET-Micro board.<br />
* [https://www.raspberrypi.org/products/raspberry-pi-touch-display/ Raspberry Pi Touch Display]<br />
* [https://www.raspberrypi.org/products/camera-module-v2/ Camera Module V2]<br />
<br />
<br />
<br />
<br />
{{Community}}</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2280LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T13:06:52Z<p>VytautasBuitvydas: /* LimeNET-Micro SO-DIMM adapter board Key Features */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
TBD<br />
<br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs.<br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapter]]<br />
<br />
== Data transfer options ==<br />
<br />
<br />
Data from/to LimeNET-Micro board can be transferred in two ways – through Raspberry Pi SPI interface (Option Nr.1) or USB2.0 (Option Nr.2). Each option requires specific gateware to be programmed for LimeNET-Micro board.<br />
<br />
* '''Option Nr. 1''' – in this case when LimeNET-Micro SO-DIMM adapter is connected no additional cables are needed and data can be transferred trough Raspberry Pi SPI interface. <br />
* '''Option Nr. 2''' – in this case for LimeNET-Micro v2.1 board jumper '''J14''' has to be removed and '''J18''' has to be installed and one end of microUSB cable has to be connected to ''' J15''' connector. For additional info see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#USB_subsystem 3.3 USB subsystem] of [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description]. Connect other end of microUSB cable to one of the Raspberry Pi USB2.0 ports.<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
TBD</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2279LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T12:39:12Z<p>VytautasBuitvydas: /* Data transfer options */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
TBD<br />
<br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs.<br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm (2.441” x 1.181”)<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapter]]<br />
<br />
== Data transfer options ==<br />
<br />
<br />
Data from/to LimeNET-Micro board can be transferred in two ways – through Raspberry Pi SPI interface (Option Nr.1) or USB2.0 (Option Nr.2). Each option requires specific gateware to be programmed for LimeNET-Micro board.<br />
<br />
* '''Option Nr. 1''' – in this case when LimeNET-Micro SO-DIMM adapter is connected no additional cables are needed and data can be transferred trough Raspberry Pi SPI interface. <br />
* '''Option Nr. 2''' – in this case for LimeNET-Micro v2.1 board jumper '''J14''' has to be removed and '''J18''' has to be installed and one end of microUSB cable has to be connected to ''' J15''' connector. For additional info see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#USB_subsystem 3.3 USB subsystem] of [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description]. Connect other end of microUSB cable to one of the Raspberry Pi USB2.0 ports.<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
TBD</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2278LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T12:38:24Z<p>VytautasBuitvydas: /* Data transfer options */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
TBD<br />
<br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs.<br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm (2.441” x 1.181”)<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapter]]<br />
<br />
== Data transfer options ==<br />
<br />
<br />
Data from/to LimeNET-Micro board can be transferred in two ways – through Raspberry Pi SPI interface (Option Nr.1) or USB2.0 (Option Nr.2). Each option requires specific gateware to be programmed for LimeNET-Micro board.<br />
<br />
* '''Option Nr. 1''' – in this case when LimeNET-Micro SO-DIMM adapter is connected no additional cables are needed and data can be transferred trough Raspberry Pi SPI interface. <br />
* '''Option Nr. 2''' – in this case for LimeNET-Micro v2.1 board jumper '''J14''' has to be removed and '''J18''' has to be installed and one end of microUSB cable has to be connected to ''' J15''' connector. For additional info see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#USB_subsystem 3.3 USB subsystem] of[https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description]. Connect other end of microUSB cable to one of the Raspberry Pi USB2.0 ports.<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
TBD</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2277LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T12:29:28Z<p>VytautasBuitvydas: /* Basic setup */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
TBD<br />
<br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs.<br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm (2.441” x 1.181”)<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapter]]<br />
<br />
== Data transfer options ==<br />
<br />
<br />
Data from/to LimeNET-Micro board can be transferred in two ways – through Raspberry Pi SPI interface (Option Nr.1) or USB2.0 (Option Nr.2). <br />
<br />
* '''Option Nr. 1''' – in this case when LimeNET-Micro SO-DIMM adapter is connected no additional cables are needed and data can be transferred trough Raspberry Pi SPI interface. <br />
* '''Option Nr. 2''' – in this case for LimeNET-Micro v2.1 board jumper '''J14''' has to be removed and '''J18''' has to be installed and one end of microUSB cable has to be connected to ''' J15''' connector. For additional info see chapter [https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description#USB_subsystem 3.3 USB subsystem] of[https://wiki.myriadrf.org/LimeNET-Micro_v2.1_hardware_description LimeNET-Micro v2.1 hardware description]. Connect other end of microUSB cable to one of the Raspberry Pi USB2.0 ports.<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
TBD</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2276LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T11:50:33Z<p>VytautasBuitvydas: /* Complete Adapter Kit Package */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
TBD<br />
<br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs.<br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm (2.441” x 1.181”)<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapter]]<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
TBD</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2275LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T11:50:09Z<p>VytautasBuitvydas: /* Board Design Files */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs. <br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm (2.441” x 1.181”)<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapter]]<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
TBD</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2274LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T11:49:59Z<p>VytautasBuitvydas: /* Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs. <br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm (2.441” x 1.181”)<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapter]]<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2273LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T11:15:49Z<p>VytautasBuitvydas: /* Basic setup */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs. <br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm (2.441” x 1.181”)<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapter]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2272LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-12T11:15:34Z<p>VytautasBuitvydas: /* Introduction */</p>
<hr />
<div>= Introduction = <br />
<br />
LimeNET-Micro SO-DIMM adapter v1.2 board can be used to connect “classic” Raspberry Pi to LimeNET-Micro v2.1 instead of CM3 (Compute module 3). <br />
<br />
= Complete Adapter Kit Package = <br />
<br />
The LimeNET-Micro complete adapter kit showed Figure 1. <br />
<br />
Adapter kit content:<br />
* LimeNET-Micro SO-DIMM adapter<br />
* Flat ribbon cable with 2 female plugs. <br />
<br />
= LimeNET-Micro SO-DIMM adapter board Key Features = <br />
<br />
LimeNET-Micro SO-DIMM adapter is a small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro boards.<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
* [https://wiki.myriadrf.org/LimeNET_Micro LimeNET-Micro board] <br />
<br />
<br />
LimeNET-Micro SO-DIMM adapter board features: <br />
* '''Connections''' <br />
**DDR2 SODIMM connector <br />
**20x2 Raspberry Pi Header<br />
**Raspberry Pi 5V power jumper<br />
**Raspberry Pi 5V power header<br />
**Raspberry Pi 3.3V power header<br />
**Raspberry Pi USB2.0 header<br />
*'''Board Size''' without connectors 67.6mm x 31mm (2.441” x 1.181”)<br />
<br />
== LimeNET-Micro SO-DIMM adapter board overview ==<br />
LimeNET-Micro SO-DIMM adapter board version v1.2 picture with highlighted major components and connections presented in Figure 2.<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 2.png|center|thumb|640px|Figure 2 LimeNET-Micro SO-DIMM adapter top side components and connectors]]<br />
<br />
Board components description listed in the Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. Board components<br />
! Board Reference!! Type (IC5) !! Description<br />
|-<br />
|J1||Connector||DDR2 SODIMM connector <br />
|-<br />
|J2||Header||20x2 Raspberry Pi Header<br />
|-<br />
|J3||Jumper||Raspberry Pi 5V power jumper<br />
|-<br />
|J4 ||Header||Raspberry Pi 5V power header<br />
|-<br />
|J5||Header ||Raspberry Pi 3.3V power header<br />
|-<br />
|J6||Header||Raspberry Pi USB2.0 header<br />
|}<br />
<br />
= Getting Started with LimeNET-Micro and LimeNET-Micro SO-DIMM adapter = <br />
== Basic setup ==<br />
<br />
To get LimeNET-Micro board up and running with SO-DIMM adapter:<br />
* Make sure that LimeNET-Micro and Raspberry Pi boards are powered off. <br />
*Connect female plug of one end of ribbon cable to Raspberry Pi, make sure to match first pin positions (see Figure 3), lock key should be facing towards Raspberry Pi board;<br />
*Connect female plug of other end of ribbon cable to LimeNET-Micro SO-DIMM adapter, make sure to match lock pin position (See Figure 2);<br />
*Install LimeNET-Micro SO-DIMM adapter into LimeNET-Micro SO-DIMM socket;<br />
*Power up Raspberry Pi (follow instructions on https://www.raspberrypi.org) and power up LimeNET-Micro board (follow instructions on https://wiki.myriadrf.org/Getting_Started_with_the_LimeNET-Micro)<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 3.png|center|thumb|640px|Figure 3 Connecting ribbon cable to Raspberry Pi]]<br />
<br />
[[File:LimeNET-Micro_SODIMM_adapter_Figure 4.jpg|center|thumb|640px|Figure 4 Raspberry Pi and LimeNET-Micro SO-DIMM adapteri]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:LimeNET-Micro_SODIMM_adapter_Figure_4.jpg&diff=2271File:LimeNET-Micro SODIMM adapter Figure 4.jpg2019-04-12T11:15:15Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:LimeNET-Micro_SODIMM_adapter_Figure_3.png&diff=2270File:LimeNET-Micro SODIMM adapter Figure 3.png2019-04-12T11:12:16Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:LimeNET-Micro_SODIMM_adapter_Figure_2.png&diff=2269File:LimeNET-Micro SODIMM adapter Figure 2.png2019-04-12T11:05:50Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi&diff=2268LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi2019-04-11T13:57:24Z<p>VytautasBuitvydas: Created page with "= Introduction = A small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro."</p>
<hr />
<div>= Introduction = <br />
<br />
A small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro.</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Adapter_for_Classic_Raspberry_Pi&diff=2267Adapter for Classic Raspberry Pi2019-04-11T13:55:45Z<p>VytautasBuitvydas: /* Introduction */</p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET_Micro&diff=2266LimeNET Micro2019-04-11T13:55:38Z<p>VytautasBuitvydas: /* Documentation */</p>
<hr />
<div>== LimeNET-Micro Board ==<br />
<br />
LimeNET Micro makes deploying wireless networks more accessible than ever before, by extending the LimeNET line of integrated hardware solutions via an ultra-low cost platform that is capable of supporting narrowband systems, such as GSM and IoT wireless standards, in a stand-alone configuration.<br />
LimeNET-Micro v2.1 board<br />
<br />
[[File:LimeSDR-Micro_v2.1_board.png|center|550px|LimeNET-Micro v2.1 ]]<br />
<br />
== Features and Specifications ==<br />
<br />
{| class="wikitable"<br />
! Feature !! Description<br />
|-<br />
| RF Transceiver || Lime Microsystems LMS7002M MIMO FPRF<br />
|-<br />
| FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| Raspberry Pi || Raspberry Pi CM3(L)<br />
|-<br />
| USB 2.0 controller || FTDI FT601 (connects FPGA to USB2.0 HUB)<br />
|-<br />
| Oscillator || Rakon U7475LF @30.72MHz<br />
|-<br />
| Continuous frequency range || 10MHz - 3.5 GHz<br />
|-<br />
| Bandwidth || Up to 10 MHz<br />
|-<br />
| RF connection || 2 SMA connectors (2 TRX)<br />
|-<br />
| Power Output (CW) || Up to 10 dbm<br />
|-<br />
| Power Supply || Via PoE, external 5V DC connector or microUSB port<br />
|-<br />
| Status indicators || Programmable LEDs<br />
|-<br />
| Dimensions || without connectors 125mm x 65mm<br />
|}<br />
<br />
== Getting Help ==<br />
<br />
If you have questions, the [https://discourse.myriadrf.org/ MyriadRF Discourse] is a best place to ask for help.<br />
<br />
== Documentation ==<br />
* [[Getting_Started_with_the_LimeNET-Micro | Getting Started with the LimeNET-Micro]]<br />
* [[LimeNET-Micro_SO-DIMM_Adapter_for_Classic_Raspberry_Pi | LimeNET-Micro SO-DIMM Adapter for Classic Raspberry Pi]]<br />
* [[LimeNET-Micro_v2.1_hardware_description | LimeNET-Micro v2.1 hardware description]]<br />
* [[LMS7002Mr3_Calibration_Using_MCU|LMS7002M (Mask 1) Transceiver Calibration]] - LMS7002Mr3 calibration guide, using internal MCU<br />
* [[LimeSDR Made Simple]] - Demystifying using SDR in the real world and programming a simple example with confidence, through bite sized chunks (note that not all examples will work with the Mini, e.g. those using the waveform player)<br />
* [https://github.com/myriadrf/LMS7002M-docs/blob/master/LMS7002M_Data_Sheet_v3.1r00.pdf LMS7002M Datasheet (PDF)] - LMS7002M RF transceiver datasheet<br />
* [https://github.com/myriadrf/LMS7002M-docs/blob/master/LMS7002M_Programming_and_Calibration_Guide_v31r05.pdf LMS7002M Programming and Calibration Guide (PDF)] - LMS7002M programming and calibration guide<br />
<br />
== USB Drivers ==<br />
<br />
'''Windows only''', OSX and Linux users do not need to install drivers for USB support.<br />
Follow driver installation instructions in [[LimeSDR-Mini_driver_installation|Driver Installation Documentation]].<br />
<br />
== Software ==<br />
<br />
*[[LimeSuiteGUI|LimeSuiteGUI]]<br />
*[[LimeSDR ExtIO Plugin for HDSDR|LimeSDR ExtIO Plugin for HDSDR]]<br />
*[[Gr-limesdr_Plugin_for_GNURadio|gr-limesdr Plugin for GNURadio]]<br />
<br />
== FPGA Binaries ==<br />
<br />
Here are the links to pre-compiled MCU firmware and FPGA gateware (bitstream):<br />
* FPGA [https://github.com/myriadrf/LimeNet-Micro_GW/blob/FTDI/LimeNET-Micro_bitstreams/LimeNET-Micro_lms7_trx_HW_2.1_auto.rpd gateware]<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
LimeNET-Micro 2.1<br />
<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1/Project%20Outputs%20for%20LimeNet-Micro_2v1-SDR/LimeNET-Micro_2v1-SDR_Schematic_r2.PDF Schematic (PDF)]<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1 PCB project (Altium project)]<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1/Project%20Outputs%20for%20LimeNet-Micro_2v1-SDR/BOM/LimeNET-Micro_2v1_SDR_BOMr2.xls BOM (XLS)]<br />
<br />
== Additional Components ==<br />
<br />
Here is a list of additional components to be used with LimeNET-Micro board.<br />
* [https://www.raspberrypi.org/products/raspberry-pi-touch-display/ Raspberry Pi Touch Display]<br />
* [https://www.raspberrypi.org/products/camera-module-v2/ Camera Module V2]<br />
<br />
<br />
<br />
<br />
{{Community}}</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Adapter_for_Classic_Raspberry_Pi&diff=2265Adapter for Classic Raspberry Pi2019-04-11T13:53:32Z<p>VytautasBuitvydas: Created page with "=Introduction= A small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro."</p>
<hr />
<div>=Introduction=<br />
<br />
A small SO-DIMM form factor board plus ribbon cable to enable use of a classic/consumer Raspberry Pi with the LimeNET Micro.</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=LimeNET_Micro&diff=2264LimeNET Micro2019-04-11T13:52:44Z<p>VytautasBuitvydas: /* Documentation */</p>
<hr />
<div>== LimeNET-Micro Board ==<br />
<br />
LimeNET Micro makes deploying wireless networks more accessible than ever before, by extending the LimeNET line of integrated hardware solutions via an ultra-low cost platform that is capable of supporting narrowband systems, such as GSM and IoT wireless standards, in a stand-alone configuration.<br />
LimeNET-Micro v2.1 board<br />
<br />
[[File:LimeSDR-Micro_v2.1_board.png|center|550px|LimeNET-Micro v2.1 ]]<br />
<br />
== Features and Specifications ==<br />
<br />
{| class="wikitable"<br />
! Feature !! Description<br />
|-<br />
| RF Transceiver || Lime Microsystems LMS7002M MIMO FPRF<br />
|-<br />
| FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| Raspberry Pi || Raspberry Pi CM3(L)<br />
|-<br />
| USB 2.0 controller || FTDI FT601 (connects FPGA to USB2.0 HUB)<br />
|-<br />
| Oscillator || Rakon U7475LF @30.72MHz<br />
|-<br />
| Continuous frequency range || 10MHz - 3.5 GHz<br />
|-<br />
| Bandwidth || Up to 10 MHz<br />
|-<br />
| RF connection || 2 SMA connectors (2 TRX)<br />
|-<br />
| Power Output (CW) || Up to 10 dbm<br />
|-<br />
| Power Supply || Via PoE, external 5V DC connector or microUSB port<br />
|-<br />
| Status indicators || Programmable LEDs<br />
|-<br />
| Dimensions || without connectors 125mm x 65mm<br />
|}<br />
<br />
== Getting Help ==<br />
<br />
If you have questions, the [https://discourse.myriadrf.org/ MyriadRF Discourse] is a best place to ask for help.<br />
<br />
== Documentation ==<br />
* [[Getting_Started_with_the_LimeNET-Micro | Getting Started with the LimeNET-Micro]]<br />
* [[Adapter_for_Classic_Raspberry_Pi | Adapter for Classic Raspberry Pi]]<br />
* [[LimeNET-Micro_v2.1_hardware_description | LimeNET-Micro v2.1 hardware description]]<br />
* [[LMS7002Mr3_Calibration_Using_MCU|LMS7002M (Mask 1) Transceiver Calibration]] - LMS7002Mr3 calibration guide, using internal MCU<br />
* [[LimeSDR Made Simple]] - Demystifying using SDR in the real world and programming a simple example with confidence, through bite sized chunks (note that not all examples will work with the Mini, e.g. those using the waveform player)<br />
* [https://github.com/myriadrf/LMS7002M-docs/blob/master/LMS7002M_Data_Sheet_v3.1r00.pdf LMS7002M Datasheet (PDF)] - LMS7002M RF transceiver datasheet<br />
* [https://github.com/myriadrf/LMS7002M-docs/blob/master/LMS7002M_Programming_and_Calibration_Guide_v31r05.pdf LMS7002M Programming and Calibration Guide (PDF)] - LMS7002M programming and calibration guide<br />
<br />
== USB Drivers ==<br />
<br />
'''Windows only''', OSX and Linux users do not need to install drivers for USB support.<br />
Follow driver installation instructions in [[LimeSDR-Mini_driver_installation|Driver Installation Documentation]].<br />
<br />
== Software ==<br />
<br />
*[[LimeSuiteGUI|LimeSuiteGUI]]<br />
*[[LimeSDR ExtIO Plugin for HDSDR|LimeSDR ExtIO Plugin for HDSDR]]<br />
*[[Gr-limesdr_Plugin_for_GNURadio|gr-limesdr Plugin for GNURadio]]<br />
<br />
== FPGA Binaries ==<br />
<br />
Here are the links to pre-compiled MCU firmware and FPGA gateware (bitstream):<br />
* FPGA [https://github.com/myriadrf/LimeNet-Micro_GW/blob/FTDI/LimeNET-Micro_bitstreams/LimeNET-Micro_lms7_trx_HW_2.1_auto.rpd gateware]<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
LimeNET-Micro 2.1<br />
<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1/Project%20Outputs%20for%20LimeNet-Micro_2v1-SDR/LimeNET-Micro_2v1-SDR_Schematic_r2.PDF Schematic (PDF)]<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1 PCB project (Altium project)]<br />
* [https://github.com/myriadrf/LimeNET-Micro/blob/master/hardware/2v1/Project%20Outputs%20for%20LimeNet-Micro_2v1-SDR/BOM/LimeNET-Micro_2v1_SDR_BOMr2.xls BOM (XLS)]<br />
<br />
== Additional Components ==<br />
<br />
Here is a list of additional components to be used with LimeNET-Micro board.<br />
* [https://www.raspberrypi.org/products/raspberry-pi-touch-display/ Raspberry Pi Touch Display]<br />
* [https://www.raspberrypi.org/products/camera-module-v2/ Camera Module V2]<br />
<br />
<br />
<br />
<br />
{{Community}}</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO&diff=2263Lime-GPSDO2019-04-11T12:26:57Z<p>VytautasBuitvydas: /* Documentation */</p>
<hr />
<div>== Lime-GPSDO Boards ==<br />
<br />
Lime-GPSDO is a combination of GPS receiver, high-quality clock source (VCOCXO) and Intel MAX10 FPGA fitted in one board which can be used as high stability clock source for timing sensitive applications. <br />
<br />
Lime-GPSDO v1.0 board<br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
== Features and Specifications ==<br />
<br />
{| class="wikitable"<br />
! Feature !! Description<br />
|-<br />
| FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| USB-to-UART bridge || Silicon labs USBXpress Family CP2102N<br />
|-<br />
| Oscillator || Rakon U7475LF @30.72MHz<br />
|-<br />
| GPS receiver || TBD<br />
|-<br />
| RF connection || 3 SMA connectors (Time pulse, GNSS antena, Clock output)<br />
|-<br />
| Status indicators || x3 Programmable LEDs<br />
|-<br />
| Dimensions || 50.50mm x 80mm <br />
|}<br />
<br />
== Getting Help ==<br />
<br />
If you have questions, the [https://discourse.myriadrf.org/ MyriadRF Discourse] is a best place to ask for help.<br />
<br />
== Documentation ==<br />
<br />
* [[Getting_Started_with_Lime-GPSDO | Getting Started with Lime-GPSDO]]<br />
* [[Lime-GPSDO_v1.0_hardware_description | Lime-GPSDO v1.0 hardware description]]<br />
<br />
== FPGA Binaries ==<br />
<br />
Here are the links to pre-compiled FPGA gateware (bitstream):<br />
* FPGA [https://github.com/myriadrf/Lime-GPSDO_GW/blob/master/Lime-GPSDO/Lime-GPSDO.pof TBD]<br />
<br />
== Board Design Files ==<br />
<br />
Here are links to the schematic, PCB project and BOM:<br />
<br />
Lime-GPSDO v1.0<br />
<br />
* [https://github.com/myriadrf/ Schematic (PDF) TBD]<br />
* [https://github.com/myriadrf/ PCB project (Altium project) TBD ]<br />
* [https://github.com/myriadrf/ BOM (XLS) TBD]<br />
<br />
== Additional Components ==<br />
<br />
Here is a list of additional components to be used with LimeSDR-Mini board.<br />
* TBD<br />
<br />
{{Community}}</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Getting_Started_with_Lime-GPSDO&diff=2262Getting Started with Lime-GPSDO2019-04-11T12:25:05Z<p>VytautasBuitvydas: /* Debug information */</p>
<hr />
<div>=Basic setup=<br />
<br />
<br />
To get Lime-GPSDO board up and running:<br />
# Connect GNSS antenna to J4 SMA connector (see Figure 1).<br />
# Power up board through microUSB connector (see Figure 1) or 5V DC power jack (see chapter [https://wiki.myriadrf.org/Lime-GPSDO_v1.0_hardware_description#Power_Distribution 3.8 Power Distribution] and Figure 1 for other power options).<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 1 Basic setup.png|center|thumb|840px|Figure 1 Basic setup]]<br />
<br />
=Board status=<br />
<br />
After connecting GNSS antenna and applying power you should see green color LED4 which indicates that board is getting power and red LED1 which indicates VCOCXO tune state which are listed below:<br />
*'''Solid RED''' – no GPS lock, VCOCXO frequency tuning is off;<br />
*'''Blinking RED''' – GPS is locked, 1s lowest accuracy tune state; <br />
*'''Blinking RED/GREEN''' - GPS is locked, 10s accuracy tune state;<br />
*'''Blinking GREEN''' - GPS is locked, 100s highest accuracy tune state.<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 2 Board status indication.png|center|thumb|640px|Figure 2 Board status indication]]<br />
<br />
Usually GNSS module takes some time to gain GPS lock after applying power this means that LED1 will stay solid red and VCOCXO frequency tune process starts after GNSS module gains GPS lock and LED1 starts blinking. <br />
<br />
=Debug information=<br />
<br />
There is ability to get NMEA messages from GNSS module or VCOCXO tune log through onboard USB-to-UART bridge. For this example desktop PC running Windows 10 is used. <br />
<br><br />
After connecting Lime-GPSDO microUSB to PC, you should see new COM port in “Device manager” <br />
[[File:Lime-GPSDO_Getting_started_Figure 3 Device manager after connecting Lime-GPSDO board.png|center|thumb|640px|Figure 3 Device manager after connecting Lime-GPSDO board]]<br />
Then serial terminal with 9600 baud rate setting can be used to connect to COM port and get serial data. Set SW1.0 switch to ON position to get NMEA messages from GNSS module or SW1.0 switch to OFF and SW1.1 to ON position to get VCOCXO tune state log Figure 13. Log is printed in following format:<br />
<br />
: '''Reserved,State,Accuracy,DAC val,1s,10s,100s'''<br />
:: '''State''' – 0 – coarse tune, 1 – Fine tune; <br><br />
:: '''Accuracy''' – 1 – 1s lowest accuracy state, 10s accuracy state, 100s highest accuracy state;<br><br />
:: '''DAC val''' – Current DAC value hexadecimal format;<br><br />
:: '''1s''' – Frequency error (hexadecimal format) in clock cycles measured in 1s period;<br><br />
:: '''10s''' – Frequency error (hexadecimal format) in clock cycles measured in 10s period;<br><br />
:: '''100s''' – Frequency error (hexadecimal format) in clock cycles measured in 10s period.<br><br />
<br />
Refer to chapter [https://wiki.myriadrf.org/Lime-GPSDO_v1.0_hardware_description#Switch_and_push_button Switch and push button] for slide switch description.<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 4 VCOCXO tune state log.png|center|thumb|640px|Figure 4 VCOCXO tune state log]]<br />
<br />
=Results=<br />
<br />
To evaluate Lime-GPSDO v1.0 clock accuracy and stability see charts below. Figure 5 – represents PPB measurement taken from one second period, Figure 6 – PPB measurement taken from 10 second period, Figure 7 – PPB measurement taken from 100 second period. Results were logged for approximately 14 hours. Measurements from 1 and 10 second period gives only rough estimate of clock stability because they give calculation error as large as ~30 PPB (1s measuring period) due to short measuring time. From 100s measuring period chart (Figure 16) results shows that Lime-GPSDO v1.0 board can achieve frequency stability of ±5 parts per billion. <br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 5 PPB vs Time, 1s measuring period.png|center|thumb|640px|Figure 5 PPB vs Time, 1s measuring period]]<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 6 PPB vs Time, 10s measuring period.png|center|thumb|640px|Figure 6 PPB vs Time, 10s measuring period]]<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 7 PPB vs Time, 100s measuring period.png|center|thumb|640px|Figure 7 PPB vs Time, 100s measuring period]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Lime-GPSDO_Getting_started_Figure_7_PPB_vs_Time,_100s_measuring_period.png&diff=2261File:Lime-GPSDO Getting started Figure 7 PPB vs Time, 100s measuring period.png2019-04-11T12:24:52Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Lime-GPSDO_Getting_started_Figure_6_PPB_vs_Time,_10s_measuring_period.png&diff=2260File:Lime-GPSDO Getting started Figure 6 PPB vs Time, 10s measuring period.png2019-04-11T12:24:44Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Lime-GPSDO_Getting_started_Figure_5_PPB_vs_Time,_1s_measuring_period.png&diff=2259File:Lime-GPSDO Getting started Figure 5 PPB vs Time, 1s measuring period.png2019-04-11T12:24:31Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Lime-GPSDO_Getting_started_Figure_4_VCOCXO_tune_state_log.png&diff=2258File:Lime-GPSDO Getting started Figure 4 VCOCXO tune state log.png2019-04-11T12:17:55Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Getting_Started_with_Lime-GPSDO&diff=2257Getting Started with Lime-GPSDO2019-04-11T12:17:06Z<p>VytautasBuitvydas: /* Debug information */</p>
<hr />
<div>=Basic setup=<br />
<br />
<br />
To get Lime-GPSDO board up and running:<br />
# Connect GNSS antenna to J4 SMA connector (see Figure 1).<br />
# Power up board through microUSB connector (see Figure 1) or 5V DC power jack (see chapter [https://wiki.myriadrf.org/Lime-GPSDO_v1.0_hardware_description#Power_Distribution 3.8 Power Distribution] and Figure 1 for other power options).<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 1 Basic setup.png|center|thumb|840px|Figure 1 Basic setup]]<br />
<br />
=Board status=<br />
<br />
After connecting GNSS antenna and applying power you should see green color LED4 which indicates that board is getting power and red LED1 which indicates VCOCXO tune state which are listed below:<br />
*'''Solid RED''' – no GPS lock, VCOCXO frequency tuning is off;<br />
*'''Blinking RED''' – GPS is locked, 1s lowest accuracy tune state; <br />
*'''Blinking RED/GREEN''' - GPS is locked, 10s accuracy tune state;<br />
*'''Blinking GREEN''' - GPS is locked, 100s highest accuracy tune state.<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 2 Board status indication.png|center|thumb|640px|Figure 2 Board status indication]]<br />
<br />
Usually GNSS module takes some time to gain GPS lock after applying power this means that LED1 will stay solid red and VCOCXO frequency tune process starts after GNSS module gains GPS lock and LED1 starts blinking. <br />
<br />
=Debug information=<br />
<br />
There is ability to get NMEA messages from GNSS module or VCOCXO tune log through onboard USB-to-UART bridge. For this example desktop PC running Windows 10 is used. <br />
<br><br />
After connecting Lime-GPSDO microUSB to PC, you should see new COM port in “Device manager” <br />
[[File:Lime-GPSDO_Getting_started_Figure 3 Device manager after connecting Lime-GPSDO board.png|center|thumb|640px|Figure 3 Device manager after connecting Lime-GPSDO board]]<br />
Then serial terminal with 9600 baud rate setting can be used to connect to COM port and get serial data. Set SW1.0 switch to ON position to get NMEA messages from GNSS module or SW1.0 switch to OFF and SW1.1 to ON position to get VCOCXO tune state log Figure 13. Log is printed in following format:<br />
<br />
: '''Reserved,State,Accuracy,DAC val,1s,10s,100s'''<br />
:: '''State''' – 0 – coarse tune, 1 – Fine tune; <br><br />
:: '''Accuracy''' – 1 – 1s lowest accuracy state, 10s accuracy state, 100s highest accuracy state;<br><br />
:: '''DAC val''' – Current DAC value hexadecimal format;<br><br />
:: '''1s''' – Frequency error (hexadecimal format) in clock cycles measured in 1s period;<br><br />
:: '''10s''' – Frequency error (hexadecimal format) in clock cycles measured in 10s period;<br><br />
:: '''100s''' – Frequency error (hexadecimal format) in clock cycles measured in 10s period.<br><br />
<br />
Refer to chapter [https://wiki.myriadrf.org/Lime-GPSDO_v1.0_hardware_description#Switch_and_push_button Switch and push button] for slide switch description.<br />
<br />
Lime-GPSDO_Getting_started_Figure 4 VCOCXO tune state log.png</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Getting_Started_with_Lime-GPSDO&diff=2256Getting Started with Lime-GPSDO2019-04-11T12:14:14Z<p>VytautasBuitvydas: Created page with "=Basic setup= To get Lime-GPSDO board up and running: # Connect GNSS antenna to J4 SMA connector (see Figure 1). # Power up board through microUSB connector (see Figure 1) o..."</p>
<hr />
<div>=Basic setup=<br />
<br />
<br />
To get Lime-GPSDO board up and running:<br />
# Connect GNSS antenna to J4 SMA connector (see Figure 1).<br />
# Power up board through microUSB connector (see Figure 1) or 5V DC power jack (see chapter [https://wiki.myriadrf.org/Lime-GPSDO_v1.0_hardware_description#Power_Distribution 3.8 Power Distribution] and Figure 1 for other power options).<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 1 Basic setup.png|center|thumb|840px|Figure 1 Basic setup]]<br />
<br />
=Board status=<br />
<br />
After connecting GNSS antenna and applying power you should see green color LED4 which indicates that board is getting power and red LED1 which indicates VCOCXO tune state which are listed below:<br />
*'''Solid RED''' – no GPS lock, VCOCXO frequency tuning is off;<br />
*'''Blinking RED''' – GPS is locked, 1s lowest accuracy tune state; <br />
*'''Blinking RED/GREEN''' - GPS is locked, 10s accuracy tune state;<br />
*'''Blinking GREEN''' - GPS is locked, 100s highest accuracy tune state.<br />
<br />
[[File:Lime-GPSDO_Getting_started_Figure 2 Board status indication.png|center|thumb|640px|Figure 2 Board status indication]]<br />
<br />
Usually GNSS module takes some time to gain GPS lock after applying power this means that LED1 will stay solid red and VCOCXO frequency tune process starts after GNSS module gains GPS lock and LED1 starts blinking. <br />
<br />
=Debug information=<br />
<br />
There is ability to get NMEA messages from GNSS module or VCOCXO tune log through onboard USB-to-UART bridge. For this example desktop PC running Windows 10 is used. <br />
<br><br />
After connecting Lime-GPSDO microUSB to PC, you should see new COM port in “Device manager” <br />
[[File:Lime-GPSDO_Getting_started_Figure 3 Device manager after connecting Lime-GPSDO board.png|center|thumb|640px|Figure 3 Device manager after connecting Lime-GPSDO board]]<br />
Then serial terminal with 9600 baud rate setting can be used to connect to COM port and get serial data. Set SW1.0 switch to ON position to get NMEA messages from GNSS module or SW1.0 switch to OFF and SW1.1 to ON position to get VCOCXO tune state log Figure 13. Log is printed in following format:<br />
<br />
: '''Reserved,State,Accuracy,DAC val,1s,10s,100s'''<br />
<br />
:: '''State''' – 0 – coarse tune, 1 – Fine tune; <br><br />
:: '''Accuracy''' – 1 – 1s lowest accuracy state, 10s accuracy state, 100s highest accuracy state;<br><br />
:: '''DAC val''' – Current DAC value hexadecimal format;<br><br />
:: '''1s''' – Frequency error (hexadecimal format) in clock cycles measured in 1s period;<br><br />
:: '''10s''' – Frequency error (hexadecimal format) in clock cycles measured in 10s period;<br><br />
:: '''100s''' – Frequency error (hexadecimal format) in clock cycles measured in 10s period.<br></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Lime-GPSDO_Getting_started_Figure_3_Device_manager_after_connecting_Lime-GPSDO_board.png&diff=2255File:Lime-GPSDO Getting started Figure 3 Device manager after connecting Lime-GPSDO board.png2019-04-11T11:55:55Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Lime-GPSDO_Getting_started_Figure_2_Board_status_indication.png&diff=2254File:Lime-GPSDO Getting started Figure 2 Board status indication.png2019-04-11T11:49:08Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Lime-GPSDO_Getting_started_Figure_1_Basic_setup.png&diff=2253File:Lime-GPSDO Getting started Figure 1 Basic setup.png2019-04-11T11:33:03Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2252Lime-GPSDO v1.0 hardware description2019-04-11T11:07:53Z<p>VytautasBuitvydas: /* GPIO */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
[[File:Figure 5 Power rail selection for pin 10 of J12 connector.png|thumb|center|640px|Figure 5 Power rail selection for pin 10 of J12 connector ]]<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 4. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 6. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Lime-GPSDO clock pins<br />
! Source !! Schematic signal name !! I/O standard !! FPGA pin !! Description<br />
|-<br />
| rowspan="3" | Clock buffer (IC1)||CLK0_OUT||3.3V||H6||30.72 MHz<br />
|-<br />
|CLK1_OUT||3.3V||-||Connected to J5 SMA connector<br />
|-<br />
|CLK2_OUT||3.3V||-||Connected to J6 SMA connector<br />
|-<br />
|GNSS module IC5||GNSS_TPULSE||3.3V||A2||1PPS time pulse output<br />
|-<br />
|Oscillator (XO2)||CLK50_FPGA||3.3V||H4||50MHz clock source s<br />
|-<br />
| rowspan="2" | FPGA (IC6)||FPGA_TPULSE||3.3V||C2||FPGA 1PPS time pulse output connected to J3<br />
|-<br />
|FPGA_CLK_OUT||3.3V||L3||Clock output from FPGA, can be connected to J6 SMA connectors<br />
|}<br />
<br />
=== Power Distribution ===<br />
<br />
Lime-GPSDO board can be powered from USB port. In applications where USB power is insufficient board can be powered from external 5V power supply. External power supply can be fed to J14 barrel power connector by using power plug (1.35mm ID, 3.5mm OD) or pin header J13 (GND and VCC). Also there is an option to power up board from J8 GNSS USB pin header. External power supply connections has automatic source selection between USB and external source with polarity protection. <br><br><br />
Lime-GPSDO board power distribution block diagram is presented in Figure 10.<br />
<br />
[[File:Figure 10 Lime-GPSDO board power distribution block diagram.png|center|thumb|640px|Figure 10 Lime-GPSDO board power distribution block diagram]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2251Lime-GPSDO v1.0 hardware description2019-04-11T11:05:23Z<p>VytautasBuitvydas: /* Board Overview */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 4. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 6. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Lime-GPSDO clock pins<br />
! Source !! Schematic signal name !! I/O standard !! FPGA pin !! Description<br />
|-<br />
| rowspan="3" | Clock buffer (IC1)||CLK0_OUT||3.3V||H6||30.72 MHz<br />
|-<br />
|CLK1_OUT||3.3V||-||Connected to J5 SMA connector<br />
|-<br />
|CLK2_OUT||3.3V||-||Connected to J6 SMA connector<br />
|-<br />
|GNSS module IC5||GNSS_TPULSE||3.3V||A2||1PPS time pulse output<br />
|-<br />
|Oscillator (XO2)||CLK50_FPGA||3.3V||H4||50MHz clock source s<br />
|-<br />
| rowspan="2" | FPGA (IC6)||FPGA_TPULSE||3.3V||C2||FPGA 1PPS time pulse output connected to J3<br />
|-<br />
|FPGA_CLK_OUT||3.3V||L3||Clock output from FPGA, can be connected to J6 SMA connectors<br />
|}<br />
<br />
=== Power Distribution ===<br />
<br />
Lime-GPSDO board can be powered from USB port. In applications where USB power is insufficient board can be powered from external 5V power supply. External power supply can be fed to J14 barrel power connector by using power plug (1.35mm ID, 3.5mm OD) or pin header J13 (GND and VCC). Also there is an option to power up board from J8 GNSS USB pin header. External power supply connections has automatic source selection between USB and external source with polarity protection. <br><br><br />
Lime-GPSDO board power distribution block diagram is presented in Figure 10.<br />
<br />
[[File:Figure 10 Lime-GPSDO board power distribution block diagram.png|center|thumb|640px|Figure 10 Lime-GPSDO board power distribution block diagram]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2250Lime-GPSDO v1.0 hardware description2019-04-11T11:04:06Z<p>VytautasBuitvydas: /* Power Distribution */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 4. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 6. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Lime-GPSDO clock pins<br />
! Source !! Schematic signal name !! I/O standard !! FPGA pin !! Description<br />
|-<br />
| rowspan="3" | Clock buffer (IC1)||CLK0_OUT||3.3V||H6||30.72 MHz<br />
|-<br />
|CLK1_OUT||3.3V||-||Connected to J5 SMA connector<br />
|-<br />
|CLK2_OUT||3.3V||-||Connected to J6 SMA connector<br />
|-<br />
|GNSS module IC5||GNSS_TPULSE||3.3V||A2||1PPS time pulse output<br />
|-<br />
|Oscillator (XO2)||CLK50_FPGA||3.3V||H4||50MHz clock source s<br />
|-<br />
| rowspan="2" | FPGA (IC6)||FPGA_TPULSE||3.3V||C2||FPGA 1PPS time pulse output connected to J3<br />
|-<br />
|FPGA_CLK_OUT||3.3V||L3||Clock output from FPGA, can be connected to J6 SMA connectors<br />
|}<br />
<br />
=== Power Distribution ===<br />
<br />
Lime-GPSDO board can be powered from USB port. In applications where USB power is insufficient board can be powered from external 5V power supply. External power supply can be fed to J14 barrel power connector by using power plug (1.35mm ID, 3.5mm OD) or pin header J13 (GND and VCC). Also there is an option to power up board from J8 GNSS USB pin header. External power supply connections has automatic source selection between USB and external source with polarity protection. <br><br><br />
Lime-GPSDO board power distribution block diagram is presented in Figure 10.<br />
<br />
[[File:Figure 10 Lime-GPSDO board power distribution block diagram.png|center|thumb|640px|Figure 10 Lime-GPSDO board power distribution block diagram]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Figure_10_Lime-GPSDO_board_power_distribution_block_diagram.png&diff=2249File:Figure 10 Lime-GPSDO board power distribution block diagram.png2019-04-11T11:03:53Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2248Lime-GPSDO v1.0 hardware description2019-04-11T11:02:09Z<p>VytautasBuitvydas: /* Clock Distribution */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 4. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 6. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Lime-GPSDO clock pins<br />
! Source !! Schematic signal name !! I/O standard !! FPGA pin !! Description<br />
|-<br />
| rowspan="3" | Clock buffer (IC1)||CLK0_OUT||3.3V||H6||30.72 MHz<br />
|-<br />
|CLK1_OUT||3.3V||-||Connected to J5 SMA connector<br />
|-<br />
|CLK2_OUT||3.3V||-||Connected to J6 SMA connector<br />
|-<br />
|GNSS module IC5||GNSS_TPULSE||3.3V||A2||1PPS time pulse output<br />
|-<br />
|Oscillator (XO2)||CLK50_FPGA||3.3V||H4||50MHz clock source s<br />
|-<br />
| rowspan="2" | FPGA (IC6)||FPGA_TPULSE||3.3V||C2||FPGA 1PPS time pulse output connected to J3<br />
|-<br />
|FPGA_CLK_OUT||3.3V||L3||Clock output from FPGA, can be connected to J6 SMA connectors<br />
|}<br />
<br />
=== Power Distribution ===<br />
<br />
Lime-GPSDO board can be powered from USB port. In applications where USB power is insufficient board can be powered from external 5V power supply. External power supply can be fed to J14 barrel power connector by using power plug (1.35mm ID, 3.5mm OD) or pin header J13 (GND and VCC). Also there is an option to power up board from J8 GNSS USB pin header. External power supply connections has automatic source selection between USB and external source with polarity protection. <br><br><br />
Lime-GPSDO board power distribution block diagram is presented in Figure 10.</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2247Lime-GPSDO v1.0 hardware description2019-04-11T11:01:11Z<p>VytautasBuitvydas: /* Clock Distribution */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 4. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 6. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Lime-GPSDO clock pins<br />
! Source !! Schematic signal name !! I/O standard !! FPGA pin !! Description<br />
|-<br />
| rowspan="3" | Clock buffer (IC1)||CLK0_OUT||3.3V||H6||30.72 MHz<br />
|-<br />
|CLK1_OUT||3.3V||-||Connected to J5 SMA connector<br />
|-<br />
|CLK2_OUT||3.3V||-||Connected to J6 SMA connector<br />
|-<br />
|GNSS module IC5||GNSS_TPULSE||3.3V||A2||1PPS time pulse output<br />
|-<br />
|Oscillator (XO2)||CLK50_FPGA||3.3V||H4||50MHz clock source s<br />
|-<br />
| rowspan="2" | FPGA (IC6)||FPGA_TPULSE||3.3V||C2||FPGA 1PPS time pulse output connected to J3<br />
|-<br />
|FPGA_CLK_OUT||3.3V||L3||Clock output from FPGA, can be connected to J6 SMA connectors<br />
|}</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2246Lime-GPSDO v1.0 hardware description2019-04-11T10:53:58Z<p>VytautasBuitvydas: /* Temperature sensor */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 4. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 6. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2245Lime-GPSDO v1.0 hardware description2019-04-11T10:53:44Z<p>VytautasBuitvydas: /* Communication interfaces */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 4. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 6. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2244Lime-GPSDO v1.0 hardware description2019-04-11T10:53:19Z<p>VytautasBuitvydas: /* Indication LEDs */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 4. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2243Lime-GPSDO v1.0 hardware description2019-04-11T10:52:59Z<p>VytautasBuitvydas: /* GPIO */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 3. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2242Lime-GPSDO v1.0 hardware description2019-04-11T10:52:26Z<p>VytautasBuitvydas: /* GPIO */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 4. <br />
<br />
{| class="wikitable"<br />
|+ Table 3. GPIO connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2241Lime-GPSDO v1.0 hardware description2019-04-11T09:40:02Z<p>VytautasBuitvydas: /* Communication interfaces */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 4. <br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]<br />
<br />
{| class="wikitable"<br />
|+ Table 7. Communication interface pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|EXT_I2C_SCL||B4||3.3V||Serial Clock<br />
|-<br />
|EXT_I2C_SDA||A5||3.3V||Data<br />
|-<br />
|FPGA_SPI1_SCLK||N5||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI1_MOSI||N4||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI1_DAC_SS||N6||3.3V||Slave select<br />
|-<br />
|FPGA_SPI2_SCLK||M4||3.3V||Serial Clock (FPGA output)<br />
|-<br />
|FPGA_SPI2_MOSI||N3||3.3V||Data, master output<br />
|-<br />
|FPGA_SPI2_FLASH_SS||N2||3.3V||Slave select<br />
|-<br />
|GNSS_UART_TX||B3||3.3V||GNSS UART transmit (FPGA input)<br />
|-<br />
|GNSS_UART_RX||A4||3.3V||GNSS UART receive (FPGA output)<br />
|-<br />
|CP_CTS||F13||3.3V||Clear To Send control input (FPGA output)<br />
|-<br />
|CP_RTS||F12||3.3V||Ready To Send control output (FPGA input)<br />
|-<br />
|CP_RXD||G13||3.3V||Asynchronous data input (FPGA output)<br />
|-<br />
|CP_TXD||G12||3.3V||Asynchronous data output (FPGA input)<br />
|-<br />
|CP_DSR||H13||3.3V||Data Set Ready control input (FPGA output)<br />
|-<br />
|CP_DTR||J13||3.3V||Data Terminal Ready control output (FPGA input)<br />
|-<br />
|EXT_UART_RX||C12||3.3V||UART receive<br />
|-<br />
|EXT_UART_TX||C11||3.3V||UART transmit<br />
<br />
|}<br />
<br />
=== Temperature sensor ===<br />
<br />
Lime-GPSDO has integrated temperature sensor which can be used to monitor board temperature through I2C interface. <br><br />
Sensor has overtemperature shutdown output connected to FPGA. Which can be used to take actions to reduce board temperature when it rises below set limits. For example, fan will be turned on if board will heat up to 55°C and FAN will be turned off if board will cool down to 45°C.<br />
<br />
[[File:Figure 7 FAN control temperature hysteresis.png|center|thumb|640px|Figure 7 FAN control temperature hysteresis ]]<br />
<br />
{| class="wikitable"<br />
|+ Table 8. Temperature sensor pins<br />
! Schematic signal name !! FPGA pin !! I/O standard !! Comment<br />
|-<br />
|FPGA_I2C_SCL||J1||3.3V||Serial Clock<br />
|-<br />
|FPGA_I2C_SDA||K1||3.3V||Data<br />
|-<br />
|LM75_OS||H1||3.3V||Overtemperature shutdown output (FPGA input)<br />
|}<br />
<br />
=== Clock Distribution ===<br />
<br />
Lime-GPSDO board has onboard 30.72 MHz VCOCXO that is reference clock output. Clock distribution block diagram is presented in Figure 8.<br />
<br />
[[File:Figure 8 Lime-GPSDO board clock distribution block diagram.png|center|thumb|640px|Figure 8 Lime-GPSDO board clock distribution block diagram]]<br />
VCOCXO frequency can be tuned by DAC (IC2). There is voltage control input of VCOCXO exposed and connected to J2 pin header. By removing R10 resistor and providing control voltage trough J2 header VCOCXO frequency can be tuned externally. Refer to XO1 Rakon U7475LF datasheet for valid control voltage ranges. <br><br><br />
J6 SMA connector source can be changed from IC1 clock buffer (default configuration) to FPGA (IC6) clock output by removing R12 and fitting R14 resistors. Refer to Figure 9.<br />
[[File:Figure 9 SMA connector J6 source selection.png|center|thumb|640px|Figure 9 SMA connector J6 source selection]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Figure_9_SMA_connector_J6_source_selection.png&diff=2240File:Figure 9 SMA connector J6 source selection.png2019-04-11T09:39:49Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Figure_8_Lime-GPSDO_board_clock_distribution_block_diagram.png&diff=2239File:Figure 8 Lime-GPSDO board clock distribution block diagram.png2019-04-11T09:37:34Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=File:Figure_7_FAN_control_temperature_hysteresis.png&diff=2238File:Figure 7 FAN control temperature hysteresis.png2019-04-11T09:32:45Z<p>VytautasBuitvydas: </p>
<hr />
<div></div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2237Lime-GPSDO v1.0 hardware description2019-04-11T09:25:18Z<p>VytautasBuitvydas: /* Communication interfaces */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 4. <br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.<br />
<br />
[[File:Figure 6 Communication interfaces.png|center|thumb|640px|Figure 6 Communication interfaces]]</div>VytautasBuitvydashttps://wiki.myriadrf.org/index.php?title=Lime-GPSDO_v1.0_hardware_description&diff=2236Lime-GPSDO v1.0 hardware description2019-04-11T09:25:11Z<p>VytautasBuitvydas: /* GPIO */</p>
<hr />
<div>== Lime-GPSDO Board Key Features ==<br />
<br />
The Lime-GPSDO development board provides high stability clock source for timing sensitive applications. Clock frequency is being constantly monitored inside MAX10 FPGA and tuned by PPS signal from GNSS module. <br />
<br />
[[File:Lime-GPSDO_v1.0.png|center|550px|Lime-GPSDO v1.0 ]]<br />
<br />
For more information on the following topics, refer to the respective documents:<br />
<br />
* MAX10 device family, refer to Intel documentation [https://www.intel.com/content/www/us/en/programmable/products/fpga/max-series/max-10/support.html link]<br />
* N20B GNSS module resources [http://gamma.spb.ru/images/pdf/N20B_Hardware%20Design_V1.1.pdf link]<br />
<br />
Lime-GPSDO board features: <br />
* '''USB Interface'''<br />
** Silicon labs USBXpress Family USB-to-UART bridge CP2102N.<br />
* '''FPGA Features'''<br />
**MAX10 10M16SAU169C8 device in 169-pin UBGA<br />
**16K logic elements<br />
**549 Kbits embedded memory (M9K) and 2368 Kbits of user Flash Memory<br />
**45 embedded 18x18 multipliers <br />
**1 PLLs <br />
*'''FPGA Configuration''' <br />
**JTAG mode configuration <br />
*'''Memory Devices''' <br />
**4Mbit FLASH<br />
**128Kbit (16K x 8) EEPROM<br />
*'''Connections''' <br />
**microUSB2.0 (type B)<br />
**SMA connectors for clock IN/OUT, time pulse output and GNSS antenna<br />
**FPGA GPIO header (0.05” pitch)<br />
**FPGA JTAG connectors (0.05” pitch and side connector) <br />
**5V DC power jack and pinheader<br />
**Backup battery connector for GNSS receiver<br />
**Clock output pinheader<br />
**External UART connector<br />
**External I2C connector<br />
*'''Clock System'''<br />
**30.72MHz VCOCXO:<br />
***Frequency calibration ±0.5ppm;<br />
***Frequency stability over temperature in still air ±20ppb;<br />
***Frequency slope ΔF/ΔT in still air ±1.2ppb/°C<br />
**Possibility to tune VCOCXO by onboard DAC<br />
**Possibility to use GNSS PPS signal as a reference when tuning VCOCXO frequency <br />
*'''Board Size''' without connectors 50.50mm x 80mm (1.99” x 3.15”)<br />
<br />
== Board Overview ==<br />
<br />
Lime-GPSDO board version 1.0 picture with highlighted major components and connections presented in Figure 1 and Figure 2. There are three connector types – data and debugging (USB2.0, FPGA GPIO and JTAG), power (DC jack and external supply pinheader), clock source output, GNSS antenna and time pulse output.<br />
<br />
[[File:Figure 1 Lime-GPSDO top side components and connectors.png|thumb|center|640px|Figure 1 Lime-GPSDO top side components and connectors]]<br />
<br />
[[File:Figure 2 Bottom side components.png|thumb|center|440px|Figure 2 Bottom side components]]<br />
<br />
<br />
Board components description listed in the Table 1 and Table 2.<br />
<br />
{| class="wikitable"<br />
|+ Table 1. Board components<br />
! colspan="3"|Featured Devices<br />
|-<br />
! Board reference !! Type !! Description<br />
|-<br />
| IC5||GNSS module||GNSS receiver<br />
|-<br />
| IC5 || FPGA || Intel MAX 10 (10M16SAU169C8G 169-UBGA)<br />
|-<br />
| IC9||USB UART||Silicon labs USB-to-UART bridge<br />
|-<br />
! colspan="3"|Miscellaneous devices onboard<br />
|-<br />
| IC13||IC||Temperature sensor LM75<br />
|-<br />
! colspan="3"|Configuration, Status and Setup Components<br />
|-<br />
| J9||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, side connection.<br />
|-<br />
| J10||JTAG chain pin header||FPGA programming pin header for Altera USB-Blaster download cable, 0.05” pitch<br />
|-<br />
| LEDS1, LEDS2, LEDS3||Red-green status LEDs||User defined FPGA indication.<br />
|-<br />
! colspan="3"|General User Input/Output<br />
|-<br />
| J12||Pin header||8 FPGA GPIOs plus 2 power pins, 0.05” pitch<br />
|-<br />
| SW1||Slide switch||4 slide switches connected to FPGA<br />
|-<br />
| SW2||Push button||Push button connected to FPGA<br />
|-<br />
! colspan="3"|Memory Devices<br />
|-<br />
| IC11||EEPROM||128K (16K x 8) EEPROM connected to FPGA<br />
|-<br />
| IC10 || IC || I²C EEPROM Memory 128Kb (16K x 8), connected to FPGA I2C bus<br />
|-<br />
| IC7||Flash memory||4Mbit FLASH memory connected to FPGA<br />
|-<br />
! colspan="3"|Communication Ports<br />
|-<br />
| J11||USB2.0 connector||microUSB2.0 (type B) connector<br />
|-<br />
| J8 ||Header||GNSS USB 2.0 connection header (unused)<br />
|-<br />
| J15||Header||External UART interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
| J16||Header||External I2C interface header, can be used to control external periphery. Additional logic has to be implemented in FPGA.<br />
|-<br />
! colspan="3"|Clock Circuitry<br />
|-<br />
| XO1||VCOCXO||30.72MHz voltage-controlled crystal oscillator used as a reference clock.<br />
|-<br />
| XO2||XO||50MHz crystal oscillator, used for FPGA logic.<br />
|-<br />
| IC2||DAC||Analog devices 16bit Digital-to-analog converter for VCOCXO voltage control<br />
|-<br />
| J1 ||Pin header||Optional clock output of XO1<br />
|-<br />
| J2||Pin header||Optional Voltage control input for XO1<br />
|-<br />
| J3||SMA connector||Time pulse output from GNSS modules<br />
|-<br />
| J5||SMA connector||Reference clock output<br />
|-<br />
| J6||U.FL connector||Reference clock output, connector is not fitted by default.<br />
|-<br />
! colspan="3"|Power Supply<br />
|-<br />
| J14||DC input jack||External 5V DC power supply<br />
|-<br />
| J13||Pin header||External 5V DC power supply and main internal power rail<br />
|-<br />
! colspan="3"|Other<br />
|-<br />
| J4||SMA connector||Antenna input for GNSS module<br />
|-<br />
| J7 ||Pin header||Backup battery connection header for GNSS module. Typical 3.0V (follow recommendation in fitted GNSS module datasheet)<br />
|}<br />
<br />
== LimeSDR-Mini Board Architecture ==<br />
<br />
<br />
The heart of the Lime-GPSDO board is Intel MAX10 FPGA. Its main function is to measure VCOCXO clock frequency and tune it by PPS signal from GNSS module and provide control. The block diagram for Lime-GPSDO board is presented in the Figure 3.<br />
[[File:Figure 3 Lime-GPSDO Development Board Block Diagram.png|thumb|center|640px|Figure 3 Lime-GPSDO Development Board Block Diagram ]]<br />
<br />
=== GNSS module ===<br />
<br />
<br />
GNSS module has serial data communication interface, timing pulse and other control signals connected to FPGA. It also has SMA connector for external antenna.<br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Chip pin (IC5)!! Chip reference (IC5) !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
|3||TIMEPULSE||GNSS_TPULSE||A2||3.3-V LVCMOS||Also connected to J3 SMA conn.<br />
|-<br />
|4||EXTINT||GNSS_EXTINT||B1||3.3-V LVCMOS||<br />
|-<br />
|8||RESET_N||GNSS_RESET||C1||3.3-V LVCMOS||<br />
|-<br />
|14||LNA_EN /RESV||GNSS_OFF||F1||3.3-V LVCMOS||<br />
|-<br />
|15||RTK_STAT /RESV||GNSS_ANT_DET||E1||3.3-V LVCMOS||<br />
|-<br />
|16||GEOFENCE_STAT /RESV||GNSS_ANT_OK||D1||3.3-V LVCMOS||<br />
|-<br />
|18||DDC_SDA /SPI_CSN||GNSS_DDC_SDA||B2||3.3-V LVCMOS||<br />
|-<br />
|19||DDC_SCL /SPI_CLK||GNSS_DDC_SCL||A3||3.3-V LVCMOS||<br />
|-<br />
|20||UART_TX /SPI_MISO||GNSS_UART_TX||B3||3.3-V LVCMOS||<br />
|-<br />
|21||UART_RX /SPI_MOSI||GNSS_UART_RX||A4||3.3-V LVCMOS||<br />
|-<br />
|11 ||RF_IN||RF_IN||- ||-||Connected to J4 SMA conn.<br />
|}<br />
<br />
By default time pulse output (J3 SMA connector) is connected to FPGA pin C2 output but can be changed to GNSS time pulse signal by removing R8 resistor and soldering R9 resistors. Refer to Figure 4.<br />
<br />
<br />
[[File:Figure 4 Time pulse output selection.png|center|thumb|640px|Figure 4 Time pulse output selection]]<br />
<br />
=== GPIO ===<br />
<br />
There are eight general purpose input/output pins from FPGA connected to FPGA GPIO header (J12). Schematic names and pin connections can be found in Table 4. <br />
<br />
{| class="wikitable"<br />
|+ Table 2. GNSS module connection<br />
! Connector pin !! Schematic signal name !! FPGA pin !! FPGA I/O standard !! Comment<br />
|-<br />
| 1||FPGA_GPIO0||M12||3.3V||<br />
|-<br />
| 2||FPGA_GPIO1||M10||3.3V||<br />
|-<br />
| 3||FPGA_GPIO2||N12||3.3V||<br />
|-<br />
| 4||FPGA_GPIO3||N10||3.3V||<br />
|-<br />
| 5||FPGA_GPIO4||M11||3.3V||<br />
|-<br />
| 6||FPGA_GPIO5||M9||3.3V||<br />
|-<br />
| 7||FPGA_GPIO6||N11||3.3V||<br />
|-<br />
| 8||FPGA_GPIO7||N9||3.3V||<br />
|-<br />
| 9||GND||-||||<br />
|-<br />
| 10||VCC||-||||3.3V or 5V selectable power rail.<br />
|}<br />
<br />
<br />
Voltage for pin 10 of J12 connector can be 3.3V (default) or 5V. To connect this pin to 5V power rail remove R47 and solder R48 resistors (see Figure 5).<br />
<br />
=== Indication LEDs ===<br />
<br />
<br />
Lime-GPSDO board comes with four dual color (red and green (RG)) indication LEDs. Most of LEDs are connected to FPGA and their function can be changed. Default LEDs functions and other information are listed in the table below.<br />
<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="2"|LED1||FPGA_LED1_G||rowspan="2"| LED1||A11||GNSS lock and VCOCXO tune state: <br> Solid RED – no GPS lock; <br> Blinking RED – GPS is locked, 1s lowest accuracy tune state; <br> Blinking RED/GREEN - GPS is locked, 10s accuracy tune state; <br> Blinking GREEN - GPS is locked, 100s highest accuracy tune state.<br />
|-<br />
||FPGA_LED1_R||B11||<br />
|-<br />
| rowspan="2"|LED2||FPGA_LED2_G||rowspan="2"|LED2||A10||<br />
|-<br />
||FPGA_LED2_R||B10||<br />
|-<br />
| rowspan="2" | LED3||FPGA_LED3_G||rowspan="2" | LED3||A8||<br />
|-<br />
||FPGA_LED3_R||A9||<br />
|-<br />
|rowspan="2" | LED4||-||rowspan="2" | LED4 VCC3P3||-||rowspan="2" | Green LED indicates VCC3P3 power rail presence. Red LED is unused<br />
|-<br />
||-||-<br />
|}<br />
<br />
<br />
=== Switch and push button ===<br />
<br />
There are four sliding switches and one push button connected to FPGA. Sliding switch to “ON” position sets logic “0” level and opposite sets logic “1”. Default functions and connection information are listed in the table below.<br />
<br />
{| class="wikitable"<br />
|+ Table 5. Default LEDs functions<br />
! Board Reference !! Schematic signal name !! Board label !! FPGA pin !! Description<br />
|-<br />
| rowspan="4"|SW1||FPGA_SW0||rowspan="4"|FPGA SWITCH||N7||rowspan="2"|FPGA_SW[1:0]=x0 - UART of GNNSS module connected to USB UART <br> FPGA_SW[1:0]= 01 - limegnss_gpio module connected to USB UART<br />
|-<br />
||FPGA_SW1||M7<br />
|-<br />
||FPGA_SW2||N8||Not used<br />
|-<br />
||FPGA_SW3||M8||Not used<br />
|-<br />
|SW2||FPGA_BTN||FPGA BTN||B7||Board reset<br />
|}<br />
<br />
=== Communication interfaces ===<br />
<br />
Lime-GPSDO board has various options of communication interfaces. There is USB-to-UART bridge and micro USB connector, pin headers for UART, I2C and interfaces for onboard periphery. For graphical representation see Figure 6 and detailed description can be found in Table 7.</div>VytautasBuitvydas