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https://wiki.myriadrf.org/index.php?title=LimeSDR_Hardware_Installation&diff=1774
LimeSDR Hardware Installation
2018-04-29T14:36:27Z
<p>Ghalfacree: Formatting change for clarity.</p>
<hr />
<div>The LimeSDR family of software defined radios are designed to make it as easy as possible to get started in the world of SDR. Before you can begin, though, you'll need to run through some simple steps in order to get your LimeSDR installed and configured correctly.<br />
<br />
==Unpacking==<br />
The LimeSDR family includes the LimeSDR USB, LimeSDR Mini, and LimeSDR PCIe (PCI Express) software defined radio devices. The first two of these are similar, differing only in their size and base capabilities and connecting to the host PC via a USB interface; the latter is functionally identical to the LimeSDR USB but connects to a PCI Express (PCIe) interface as an internal add-in card.<br />
<br />
Begin by removing your LimeSDR from its packaging. Note the anti-static bag, used to protect the LimeSDR during transit. The LimeSDR is a sensitive electronic device, and should be handled with appropriate precautions against electrostatic discharge (ESD); be sure to ground yourself, for example by tapping your finger on the exposed metal of a radiator pipe, before removing it from the anti-static bag, and ensure you hold the board by its edges. Also be careful of components, such as the small male pin headers, which protrude above the surface of the LimeSDR board; these can catch on the edge of the bag.<br />
<br />
==Connecting Antennas==<br />
The LimeSDR family of SDR boards have multiple RF ports, to which antennas appropriate to the frequencies in which you will be operating must be connected. Some hardware bundles include antennas; others come without. The port you use depends on whether you will be receiving or transmitting and at what frequency. The following sections describe the ports and their capabilities.<br />
<br />
When configuring your software, be sure to select the ports to which you have connected antennas; the LimeSDR does not automatically sense if an antenna is connected to a port or not.<br />
<br />
===LimeSDR Mini RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR Mini RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX: 2GHz - 3.5GHz frequency range<br />
|-<br />
|RX1_W<br />
|Channel 1 RX: 10MHz - 2GHz frequency range<br />
|-<br />
|TX1_1<br />
|Channel 1 TX: 2GHz - 3.5GHz frequency range<br />
|-<br />
|TX1_2<br />
|Channel 1 TX: 10MHz - 2GHz frequency range<br />
|-<br />
|}<br />
<br />
The LimeSDR Mini has SMA connectors for its ports, requiring no additional conversion for connection to external antennas. Depending on desired positioning, however, SMA extension cables will give you increased flexibility in positioning and alignment.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_W ports within the frequency bands listed.<br />
<br />
===LimeSDR USB RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX: frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX: frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX: frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX: frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX: wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX: wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX: primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX: primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX: secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX: secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR USB has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
===LimeSDR PCIe RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX: frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX: frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX: frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX: frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX: wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX: wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX: primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX: primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX: secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX: secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR PCIe has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
==Case Assembly==<br />
Some LimeSDR bundles include aluminium or acrylic cases, while cases - both first- and third-party - are also available separately. Current official cases include the [https://github.com/myriadrf/LimeSDR-USB_Acrylic_Case LimeSDR USB Acrylic Case], [https://github.com/myriadrf/LimeSDR-Mini_Acrylic_Case LimeSDR Mini Acrylic Case], LimeSDR USB Aluminium Case, LimeSDR Mini Aluminium Case, and the [https://github.com/myriadrf/LimeSDR-USB_Hacker_Case LimeSDR USB Acrylic Hacker Case].<br />
<br />
The majority of these cases can be assembled quickly and easily without further instruction. If you have purchased the official LimeSDR Acrylic Case for the LimeSDR USB, see [https://github.com/myriadrf/LimeSDR-USB_acrylic_case#assembly the detailed assembly instructions on GitHub] or the [https://www.youtube.com/watch?v=4QyM0tKj0Co video guide on YouTube]. If you have purchased a third-party case, consult the documentation from your case manufacturer for instructions.<br />
<br />
If you do not have a case for your LimeSDR, it can be used without one providing you are careful to ensure that it does not come into contact with electrically conductive surfaces - including metal desk coverings - while in use, or the board may suffer a damaging electrical short.<br />
<br />
==Connecting a LimeSDR USB or LimeSDR Mini to a PC==<br />
The LimeSDR USB and LimeSDR Mini both connect to a host computer over a USB 3.0 interface, although both are backwards compatible with older USB 2.0 ports at a reduced rate of operation. The LimeSDR Mini includes a male USB plug in its design; simply insert this directly into a free USB 3.0 Type A port on your host computer or via a good-quality USB 3.0 extension lead for more flexible positioning.<br />
<br />
The LimeSDR USB comes with a USB 3.0 splitter cable. While the LimeSDR USB draws its power entirely via USB, negating the need for an external power supply, it can require more power than a single uSB port can provide. The splitter cable is wired so that the USB plug with a blue inner, in the middle of the cable, has both power and data connections while the USB plug with a white inner, at the far end of the cable, has only power connections.<br />
<br />
Begin by connecting the white, power, USB plug to a free USB 2.0 or 3.0 port on your host computer, then connect the blue, power and data, USB plug to a free USB 3.0 port. The final end of the cable, which is terminated in a USB 3.0 SuperSpeed connector, should finally be inserted into the matching connector on the LimeSDR USB. Note that there is no power switch on the LimeSDR USB; as soon as the cable is connected, the board will become live. Disconnecting the LimeSDR USB should be performed in the opposite order, starting with the USB 3.0 SuperSpeed connector on the LimeSDR USB itself.<br />
<br />
If using the LimeSDR USB with a laptop or all-in-one system, the splitter cable may not reach between USB sockets. If so, attach a good-quality USB extension cable - not supplied - to the white, power-only, connector of the splitter to extend its reach.<br />
<br />
==Connecting a LimeSDR PCIe to a PC==<br />
The LimeSDR PCIe is an internal expansion card connecting to the PCI Express bus. As such, it should only be installed with the computer completely powered off.<br />
<br />
Remove the side of your computer's case and any other components required to gain access to the motherboard's expansion slots. The LimeSDR PCIe requires a 4-lane (4x) PCI Express slot to operate; if no dedicated x4 PCIe slot is available, it can be installed in an x8 or x16 PCIe slot.<br />
<br />
Remove the blanking plate from the rear panel of your case, if installed, and insert the LimeSDR PCIe with the status LEDs facing towards the rear of the case. No dedicated power connector is required; power is drawn from the PCI Express slot.<br />
<br />
Before replacing the side of your case, connect your antennas or pigtail leads to the U.FL connectors on the card, as these will not be accessible once the side is replaced. Route these though the expansion slot at the rear of the case for ease of access.<br />
<br />
Replace the side of your case and power your computer back on.<br />
<br />
==Next Steps==<br />
Windows users will now need to install the LimeSDR driver, following the instructions on the [[LimeSDR Windows Driver Installation]] page. All other users should move on to [[LimeSDR Firmware Management]] to update their firmware and gateware to the latest releases, without which the LimeSDR may not operate as expected.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Hardware_Installation&diff=1773
LimeSDR Hardware Installation
2018-04-29T14:28:03Z
<p>Ghalfacree: Added links to case repositories, where available; added LimeSDR USB Acrylic Case YouTube build guide.</p>
<hr />
<div>The LimeSDR family of software defined radios are designed to make it as easy as possible to get started in the world of SDR. Before you can begin, though, you'll need to run through some simple steps in order to get your LimeSDR installed and configured correctly.<br />
<br />
==Unpacking==<br />
The LimeSDR family includes the LimeSDR USB, LimeSDR Mini, and LimeSDR PCIe (PCI Express) software defined radio devices. The first two of these are similar, differing only in their size and base capabilities and connecting to the host PC via a USB interface; the latter is functionally identical to the LimeSDR USB but connects to a PCI Express (PCIe) interface as an internal add-in card.<br />
<br />
Begin by removing your LimeSDR from its packaging. Note the anti-static bag, used to protect the LimeSDR during transit. The LimeSDR is a sensitive electronic device, and should be handled with appropriate precautions against electrostatic discharge (ESD); be sure to ground yourself, for example by tapping your finger on the exposed metal of a radiator pipe, before removing it from the anti-static bag, and ensure you hold the board by its edges. Also be careful of components, such as the small male pin headers, which protrude above the surface of the LimeSDR board; these can catch on the edge of the bag.<br />
<br />
==Connecting Antennas==<br />
The LimeSDR family of SDR boards have multiple RF ports, to which antennas appropriate to the frequencies in which you will be operating must be connected. Some hardware bundles include antennas; others come without. The port you use depends on whether you will be receiving or transmitting and at what frequency. The following sections describe the ports and their capabilities.<br />
<br />
When configuring your software, be sure to select the ports to which you have connected antennas; the LimeSDR does not automatically sense if an antenna is connected to a port or not.<br />
<br />
===LimeSDR Mini RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR Mini RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - 2GHz - 3.5GHz frequency range<br />
|-<br />
|RX1_W<br />
|Channel 1 RX - 10MHz - 2GHz frequency range<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - 2GHz - 3.5GHz frequency range<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - 10MHz - 2GHz frequency range<br />
|-<br />
|}<br />
<br />
The LimeSDR Mini has SMA connectors for its ports, requiring no additional conversion for connection to external antennas. Depending on desired positioning, however, SMA extension cables will give you increased flexibility in positioning and alignment.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_W ports within the frequency bands listed.<br />
<br />
===LimeSDR USB RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR USB has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
===LimeSDR PCIe RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR PCIe has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
==Case Assembly==<br />
Some LimeSDR bundles include aluminium or acrylic cases, while cases - both first- and third-party - are also available separately. Current official cases include the [https://github.com/myriadrf/LimeSDR-USB_Acrylic_Case LimeSDR USB Acrylic Case], [https://github.com/myriadrf/LimeSDR-Mini_Acrylic_Case LimeSDR Mini Acrylic Case], LimeSDR USB Aluminium Case, LimeSDR Mini Aluminium Case, and the [https://github.com/myriadrf/LimeSDR-USB_Hacker_Case LimeSDR USB Acrylic Hacker Case].<br />
<br />
The majority of these cases can be assembled quickly and easily without further instruction. If you have purchased the official LimeSDR Acrylic Case for the LimeSDR USB, see [https://github.com/myriadrf/LimeSDR-USB_acrylic_case#assembly the detailed assembly instructions on GitHub] or the [https://www.youtube.com/watch?v=4QyM0tKj0Co video guide on YouTube]. If you have purchased a third-party case, consult the documentation from your case manufacturer for instructions.<br />
<br />
If you do not have a case for your LimeSDR, it can be used without one providing you are careful to ensure that it does not come into contact with electrically conductive surfaces - including metal desk coverings - while in use, or the board may suffer a damaging electrical short.<br />
<br />
==Connecting a LimeSDR USB or LimeSDR Mini to a PC==<br />
The LimeSDR USB and LimeSDR Mini both connect to a host computer over a USB 3.0 interface, although both are backwards compatible with older USB 2.0 ports at a reduced rate of operation. The LimeSDR Mini includes a male USB plug in its design; simply insert this directly into a free USB 3.0 Type A port on your host computer or via a good-quality USB 3.0 extension lead for more flexible positioning.<br />
<br />
The LimeSDR USB comes with a USB 3.0 splitter cable. While the LimeSDR USB draws its power entirely via USB, negating the need for an external power supply, it can require more power than a single uSB port can provide. The splitter cable is wired so that the USB plug with a blue inner, in the middle of the cable, has both power and data connections while the USB plug with a white inner, at the far end of the cable, has only power connections.<br />
<br />
Begin by connecting the white, power, USB plug to a free USB 2.0 or 3.0 port on your host computer, then connect the blue, power and data, USB plug to a free USB 3.0 port. The final end of the cable, which is terminated in a USB 3.0 SuperSpeed connector, should finally be inserted into the matching connector on the LimeSDR USB. Note that there is no power switch on the LimeSDR USB; as soon as the cable is connected, the board will become live. Disconnecting the LimeSDR USB should be performed in the opposite order, starting with the USB 3.0 SuperSpeed connector on the LimeSDR USB itself.<br />
<br />
If using the LimeSDR USB with a laptop or all-in-one system, the splitter cable may not reach between USB sockets. If so, attach a good-quality USB extension cable - not supplied - to the white, power-only, connector of the splitter to extend its reach.<br />
<br />
==Connecting a LimeSDR PCIe to a PC==<br />
The LimeSDR PCIe is an internal expansion card connecting to the PCI Express bus. As such, it should only be installed with the computer completely powered off.<br />
<br />
Remove the side of your computer's case and any other components required to gain access to the motherboard's expansion slots. The LimeSDR PCIe requires a 4-lane (4x) PCI Express slot to operate; if no dedicated x4 PCIe slot is available, it can be installed in an x8 or x16 PCIe slot.<br />
<br />
Remove the blanking plate from the rear panel of your case, if installed, and insert the LimeSDR PCIe with the status LEDs facing towards the rear of the case. No dedicated power connector is required; power is drawn from the PCI Express slot.<br />
<br />
Before replacing the side of your case, connect your antennas or pigtail leads to the U.FL connectors on the card, as these will not be accessible once the side is replaced. Route these though the expansion slot at the rear of the case for ease of access.<br />
<br />
Replace the side of your case and power your computer back on.<br />
<br />
==Next Steps==<br />
Windows users will now need to install the LimeSDR driver, following the instructions on the [[LimeSDR Windows Driver Installation]] page. All other users should move on to [[LimeSDR Firmware Management]] to update their firmware and gateware to the latest releases, without which the LimeSDR may not operate as expected.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Hardware_Installation&diff=1772
LimeSDR Hardware Installation
2018-04-29T14:22:08Z
<p>Ghalfacree: Swapped device ordering to match other pages.</p>
<hr />
<div>The LimeSDR family of software defined radios are designed to make it as easy as possible to get started in the world of SDR. Before you can begin, though, you'll need to run through some simple steps in order to get your LimeSDR installed and configured correctly.<br />
<br />
==Unpacking==<br />
The LimeSDR family includes the LimeSDR USB, LimeSDR Mini, and LimeSDR PCIe (PCI Express) software defined radio devices. The first two of these are similar, differing only in their size and base capabilities and connecting to the host PC via a USB interface; the latter is functionally identical to the LimeSDR USB but connects to a PCI Express (PCIe) interface as an internal add-in card.<br />
<br />
Begin by removing your LimeSDR from its packaging. Note the anti-static bag, used to protect the LimeSDR during transit. The LimeSDR is a sensitive electronic device, and should be handled with appropriate precautions against electrostatic discharge (ESD); be sure to ground yourself, for example by tapping your finger on the exposed metal of a radiator pipe, before removing it from the anti-static bag, and ensure you hold the board by its edges. Also be careful of components, such as the small male pin headers, which protrude above the surface of the LimeSDR board; these can catch on the edge of the bag.<br />
<br />
==Connecting Antennas==<br />
The LimeSDR family of SDR boards have multiple RF ports, to which antennas appropriate to the frequencies in which you will be operating must be connected. Some hardware bundles include antennas; others come without. The port you use depends on whether you will be receiving or transmitting and at what frequency. The following sections describe the ports and their capabilities.<br />
<br />
When configuring your software, be sure to select the ports to which you have connected antennas; the LimeSDR does not automatically sense if an antenna is connected to a port or not.<br />
<br />
===LimeSDR Mini RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR Mini RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - 2GHz - 3.5GHz frequency range<br />
|-<br />
|RX1_W<br />
|Channel 1 RX - 10MHz - 2GHz frequency range<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - 2GHz - 3.5GHz frequency range<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - 10MHz - 2GHz frequency range<br />
|-<br />
|}<br />
<br />
The LimeSDR Mini has SMA connectors for its ports, requiring no additional conversion for connection to external antennas. Depending on desired positioning, however, SMA extension cables will give you increased flexibility in positioning and alignment.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_W ports within the frequency bands listed.<br />
<br />
===LimeSDR USB RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR USB has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
===LimeSDR PCIe RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR PCIe has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
==Case Assembly==<br />
If you have purchased the official LimeSDR Acrylic Case for the LimeSDR USB, see [https://github.com/myriadrf/LimeSDR-USB_acrylic_case#assembly the assembly instructions on GitHub]. If you have purchased a third-party case, consult the documentation from your case manufacturer for instructions.<br />
<br />
If you do not have a case for your LimeSDR, it can be used without one providing you are careful to ensure that it does not come into contact with electrically conductive surfaces - including metal desk coverings - while in use, or the board may suffer a damaging electrical short.<br />
<br />
==Connecting a LimeSDR USB or LimeSDR Mini to a PC==<br />
The LimeSDR USB and LimeSDR Mini both connect to a host computer over a USB 3.0 interface, although both are backwards compatible with older USB 2.0 ports at a reduced rate of operation. The LimeSDR Mini includes a male USB plug in its design; simply insert this directly into a free USB 3.0 Type A port on your host computer or via a good-quality USB 3.0 extension lead for more flexible positioning.<br />
<br />
The LimeSDR USB comes with a USB 3.0 splitter cable. While the LimeSDR USB draws its power entirely via USB, negating the need for an external power supply, it can require more power than a single uSB port can provide. The splitter cable is wired so that the USB plug with a blue inner, in the middle of the cable, has both power and data connections while the USB plug with a white inner, at the far end of the cable, has only power connections.<br />
<br />
Begin by connecting the white, power, USB plug to a free USB 2.0 or 3.0 port on your host computer, then connect the blue, power and data, USB plug to a free USB 3.0 port. The final end of the cable, which is terminated in a USB 3.0 SuperSpeed connector, should finally be inserted into the matching connector on the LimeSDR USB. Note that there is no power switch on the LimeSDR USB; as soon as the cable is connected, the board will become live. Disconnecting the LimeSDR USB should be performed in the opposite order, starting with the USB 3.0 SuperSpeed connector on the LimeSDR USB itself.<br />
<br />
If using the LimeSDR USB with a laptop or all-in-one system, the splitter cable may not reach between USB sockets. If so, attach a good-quality USB extension cable - not supplied - to the white, power-only, connector of the splitter to extend its reach.<br />
<br />
==Connecting a LimeSDR PCIe to a PC==<br />
The LimeSDR PCIe is an internal expansion card connecting to the PCI Express bus. As such, it should only be installed with the computer completely powered off.<br />
<br />
Remove the side of your computer's case and any other components required to gain access to the motherboard's expansion slots. The LimeSDR PCIe requires a 4-lane (4x) PCI Express slot to operate; if no dedicated x4 PCIe slot is available, it can be installed in an x8 or x16 PCIe slot.<br />
<br />
Remove the blanking plate from the rear panel of your case, if installed, and insert the LimeSDR PCIe with the status LEDs facing towards the rear of the case. No dedicated power connector is required; power is drawn from the PCI Express slot.<br />
<br />
Before replacing the side of your case, connect your antennas or pigtail leads to the U.FL connectors on the card, as these will not be accessible once the side is replaced. Route these though the expansion slot at the rear of the case for ease of access.<br />
<br />
Replace the side of your case and power your computer back on.<br />
<br />
==Next Steps==<br />
Windows users will now need to install the LimeSDR driver, following the instructions on the [[LimeSDR Windows Driver Installation]] page. All other users should move on to [[LimeSDR Firmware Management]] to update their firmware and gateware to the latest releases, without which the LimeSDR may not operate as expected.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Limesdr-mini-test-linux-gui.png&diff=1770
File:Limesdr-mini-test-linux-gui.png
2018-04-29T13:59:35Z
<p>Ghalfacree: LimeQuickTest running in GUI mode on Ubuntu 16.04.3.</p>
<hr />
<div>LimeQuickTest running in GUI mode on Ubuntu 16.04.3.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Limesdr-mini-test-linux-terminal.png&diff=1769
File:Limesdr-mini-test-linux-terminal.png
2018-04-29T13:56:25Z
<p>Ghalfacree: Testing a LimeSDR Mini via LimeQuickTest on Ubuntu 16.04.3.</p>
<hr />
<div>Testing a LimeSDR Mini via LimeQuickTest on Ubuntu 16.04.3.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Installing_Lime_Suite_on_Linux&diff=1766
Installing Lime Suite on Linux
2018-04-29T13:32:26Z
<p>Ghalfacree: "install.sh" no longer executable by default - instruction modified accordingly.</p>
<hr />
<div>Lime Suite is a cross-platform software stack for the configuration and use of a range of software defined radio (SDR) platforms, including the LimeSDR family. The following instructions are for users of Linux-based operating systems, and primarily focus on Canonical's Ubuntu Linux distribution.<br />
<br />
==Installing via PPA==<br />
The easiest way to install Lime Suite is via Personal Package Archive (PPA), from the official Myriad-RF repository. This will ensure not only that you are installing the latest version, but that it is kept up-to-date via your operating system's package manager along with all your other software.<br />
<br />
Open a terminal session, and type the following commands to add the PPA and refresh the list of available packages:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To install Lime Suite and its dependencies, type the following command:<br />
<br />
<source lang="bash"><br />
sudo apt install limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
</source><br />
<br />
Once installed, Lime Suite and its dependencies will be automatically updated along with the rest of your software by your package manager. LimeSDR users will still need to manually update the firmware and gateware on their device when an update is made available, as described in [[LimeSDR Firmware Management]].<br />
<br />
===Uninstalling via PPA===<br />
To remove Lime Suite and its dependencies when installed via PPA, type the following commands:<br />
<br />
<source lang="bash"><br />
sudo apt remove limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
sudo add-apt-repository -y -r ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To remove Lime Suite, its dependencies, and all configuration files, substitute "purge" for "remove" in the first command.<br />
<br />
==Building from Source==<br />
For other Linux-based operating systems, Lime Suite should be built from source. Note that this is only required when installing from the official PPA, as above, is not possible; under no circumstances should a system have both a PPA-installed and self-built copy of Lime Suite installed, or errors will almost certainly follow.<br />
<br />
===Installing Dependencies===<br />
Lime Suite depends on a range of additional software and libraries to operate. The majority of these can be installed using your distribution's package manager; in some cases, however, the versions of packages provided in official distribution repositories are too old to function with the latest Lime Suite release. For distributions with PPA support, the following command:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
will add the official Myriad-RF PPA, which includes up-to-date versions of these dependencies, to your system. For distributions without PPA support, the "soapysdr" library should be built and installed from the latest source available on the project's [https://github.com/pothosware/SoapySDR GitHub repository] before attempting to build Lime Suite.<br />
<br />
To install the dependencies use the following command, excluding "libsoapysdr-dev" if you have compiled and installed "soapysdr" from source:<br />
<br />
<source lang="bash"><br />
sudo apt install libsoapysdr-dev libi2c-dev libusb-1.0-0-dev git g++ cmake libsqlite3-dev libwxgtk3.0-dev freeglut3-dev<br />
</source><br />
<br />
For distributions which do not use the apt package manager, install the listed packages with your distribution's own package manager (e.g. yum, pacman.)<br />
<br />
===Downloading the Source===<br />
To obtain the latest Lime Suite source files from the "Stable" branch, clone and checkout the repository using the following command:<br />
<br />
<source lang="bash"><br />
git clone https://github.com/myriadrf/LimeSuite.git<br />
cd LimeSuite<br />
git checkout stable<br />
</source><br />
<br />
If you have previously cloned the repository to install an older release, change to the LimeSuite directory and update the source with the following command instead:<br />
<br />
<source lang="bash"><br />
git pull<br />
cd builddir<br />
make clean<br />
</source><br />
<br />
===Viewing the Configuration===<br />
To create a build directory for Lime Suite, type the following commands:<br />
<br />
<source lang="bash"><br />
mkdir builddir<br />
cd builddir<br />
</source><br />
<br />
To configure the build process, and to see what components are enabled and disabled, use the following command:<br />
<br />
<source lang="bash"><br />
cmake ../<br />
</source><br />
<br />
===Building and Installing Lime Suite===<br />
To begin the build process, type the following command:<br />
<br />
<source lang="bash"><br />
make -j$(nproc)<br />
</source><br />
<br />
The build process can take several minutes to complete, depending on the amount of memory and number of processor cores available on your system. When Lime Suite is built, install it by typing:<br />
<br />
<source lang="bash"><br />
sudo make install<br />
sudo ldconfig<br />
cd ../udev-rules<br />
sudo bash install.sh<br />
</source><br />
<br />
The building and installation process is now complete. You can delete the LimeSuite directory to save space, if required, or keep it to make upgrading to the next release as simple as possible.<br />
<br />
==Next Steps==<br />
If you have installed Lime Suite to use a LimeSDR device, follow the instructions in [[Getting Started with the LimeSDR]] to install, configure, and test your hardware.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Windows_Driver_Installation&diff=1717
LimeSDR Windows Driver Installation
2018-04-12T16:02:50Z
<p>Ghalfacree: Added LimeSDR PCIe driver installation instructions.</p>
<hr />
<div>The LimeSDR family of software defined radio boards requires drivers to be installed before it can be used on platforms running the Microsoft Windows family of operating systems. Follow these instructions to download and install the driver before trying to use the LimeSDR for the first time.<br />
<br />
Those using LimeSDR hardware on Linux or macOS can skip this step and move on to [[LimeSDR Firmware Management]] to upgrade the LimeSDR's firmware and gateware.<br />
<br />
==Installing the LimeSDR Mini Driver==<br />
<br />
The LimeSDR Mini uses an industry-standard FTDI chip for USB communication. In most cases, this driver is already available on Windows and the LimeSDR Mini can be used without manual installation.<br />
<br />
In the event that the default FTDI driver provided with your Windows installation does not operate correctly, please install the latest version as detailed below.<br />
<br />
===Downloading and Extracting the Driver===<br />
Download the latest version of the FTDI driver from [http://www.ftdichip.com/Drivers/D3XX.htm the FTDI website]. The name of this archive will depend on the version available, but should begin "FTD3XXDriver_WHYQLCertified". Extract the archive using Windows' built-in archive management or the tool of your choice.<br />
<br />
===Loading Device Manager===<br />
Connect your LimeSDR Mini to your host PC, if you have not already done so. Wait a few seconds for Windows to detect the device, then click on the Start Menu or press the Super key on your keyboard and type "Device Manager" followed by the Enter Key.<br />
<br />
In the list of device categories in the Device Manager window, expand "Other devices" and find "LimeSDR Mini" in the list. Right-click on this device then left-click on "Update Driver Software" to load the driver installation dialogue.<br />
<br />
[[File:LimeSDR-Mini drivers device manager update.png|thumb|center|600px|]]<br />
<br />
===Manually Installing the Driver===<br />
To ensure that Windows loads the correct driver, choose "Browse my computer for driver software" from the window that appears. Click the "Browse" button, then browse to the folder to which you extracted the driver archive followed by the sub-folder which matches your Windows version:<br />
<br />
* Windows 7<br />
* Windows 8<br />
* Windows 8.1<br />
* Windows 10<br />
<br />
If you have a 64-bit Windows installation, first navigate to the "x64" subfolder followed by the folder which matches your Windows version.<br />
<br />
[[File:LimeSDR-Mini drivers search.png|thumb|center|600px|]]<br />
<br />
Click "OK", then click "Next" to begin driver installation. A security dialogue may appear; if so, grant permission for the installation to continue. After a few seconds, Windows will display a dialogue confirming that the driver has been installed.<br />
<br />
[[File:LimeSDR-Mini drivers finished.png|thumb|center|600px|]]<br />
<br />
===Confirming Driver Installation===<br />
To confirm that the driver has been successfully loaded, click "Close" to return to the main Device Manager window. Expand the device category labelled "Universal Serial Bus controllers" and find "FTDI FT601 USB 3.0 Bridge Device" in the list; its logo should be a USB connector with no exclamation mark or other warning symbol present.<br />
<br />
[[File:LimeSDR-Mini_drivers_device_manager_updated.png|thumb|center|600px|]]<br />
<br />
If the device does not appear, disconnect the LimeSDR Mini from your system and reconnect it to refresh Device Manager.<br />
<br />
==Installing the LimeSDR USB Driver==<br />
<br />
The LimeSDR USB uses a special chip, known as the FX3, to handle USB communications. This requires the installation of a specific driver, detailed below.<br />
<br />
===Downloading and Extracting the Driver===<br />
Download the latest version of the LimeSDR USB driver from the Myriad-RF GitHub repository using [https://github.com/myriadrf/Windows-drivers/archive/master.zip this link]. The name of the archive will be "Windows-drivers-master.zip". Extract the archive using Windows' built-in archive management or the archive tool of your choice.<br />
<br />
===Loading Device Manager===<br />
Connect your LimeSDR USB to your host PC, if you have not already done so. Wait a few seconds for Windows to detect the device, then click on the Start Menu or press the Super key on your keyboard and type "Device Manager" followed by the Enter Key.<br />
<br />
In the list of device categories in the Device Manager window, expand "Other devices" and find "LimeSDR-USB" in the list. Right-click on this device then left-click on "Update Driver Software" to load the driver installation dialogue.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Update_Software.png|thumb|center|600px|]]<br />
<br />
===Manually Installing the Driver===<br />
To ensure that Windows loads the correct driver, choose "Browse my computer for driver software" from the window that appears. Click the "Browse" button, then browse to the folder to which you extracted the driver archive followed by the sub-folder which matches your Windows version:<br />
<br />
* wxp - Windows XP<br />
* vista - Windows Vista<br />
* Win7 - Windows 7<br />
* Win8 - Windows 8<br />
* Win81 - Windows 8.1<br />
* Win10 - Windows 10<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Select.png|thumb|center|600px|]]<br />
<br />
Click "OK", then click "Next" to begin driver installation. A security dialogue may appear; if so, grant permission for the installation to continue. After a few seconds, Windows will display a dialogue confirming that the driver has been installed.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Succesfull_Inst.png|thumb|center|600px|]]<br />
<br />
===Confirming Driver Installation===<br />
To confirm that the driver has been successfully loaded, click "Close" to return to the main Device Manager window. Expand the device category labelled "Universal Serial Bus controllers" and find "Myriad-RF LimeSDR-USB" in the list; its logo should be a USB connector with no exclamation mark or other warning symbol present.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Device_Man_Succ.png|thumb|center|600px|]]<br />
<br />
If the device does not appear, disconnect the LimeSDR from your system and reconnect it to refresh Device Manager. Make sure that both the power and data USB connectors are plugged into your host PC, as inadequate power can cause the LimeSDR USB to fail to operate correctly.<br />
<br />
==Installing the LimeSDR PCIe Driver==<br />
<br />
The LimeSDR PCIe uses a Xillybus FPGA core for USB communication. Before this can be used in Windows, it must be manually downloaded and installed..<br />
<br />
===Downloading and Extracting the Driver===<br />
Download the latest version of the Xillybus driver from [http://xillybus.com/downloads/xillybus-windriver-1.2.0.0.zip the Xillybus website]. The archive will be called "windriver-1.2.0.0.zip". Extract the archive using Windows' built-in archive management or the tool of your choice.<br />
<br />
===Loading Device Manager===<br />
Install the LimeSDR PCIe into your host PC, if you have not already done so. Click on the Start Menu or press the Super key on your keyboard and type "Device Manager" followed by the Enter Key.<br />
<br />
In the list of device categories in the Device Manager window, expand "PCI Devices" and find "LimeSDR-PCIe" in the list. Right-click on this device then left-click on "Update Driver Software" to load the driver installation dialogue.<br />
<br />
===Manually Installing the Driver===<br />
To ensure that Windows loads the correct driver, choose "Browse my computer for driver software" from the window that appears. Click the "Browse" button, then browse to the folder to which you extracted the driver archive. You do not have to select a subfolder for your platform architecture; the driver installation will automatically select the correct version.<br />
<br />
[[File:LimeSDR-PCIe drivers select path.png|thumb|center|600px|]]<br />
<br />
Click "OK", then click "Next" to begin driver installation. A security dialogue may appear; if so, grant permission for the installation to continue. After a few seconds, Windows will display a dialogue confirming that the driver has been installed.<br />
<br />
[[File:LimeSDR-PCIe drivers success.png|thumb|center|600px|]]<br />
<br />
===Confirming Driver Installation===<br />
To confirm that the driver has been successfully loaded, click "Close" to return to the main Device Manager window. Expand the device category labelled "Xillybus" and find "Xillybus driver for generic FPGA interface" in the list; its logo should be two monitors on a bus connector with no exclamation mark or other warning symbol present.<br />
<br />
[[File:LimeSDR-PCIe drivers device manager after installation.png|thumb|center|600px|]]<br />
<br />
If the device does not appear, reboot your computer to complete installation.<br />
<br />
==Next Steps==<br />
With the driver installed, you can move on to [[LimeSDR Firmware Management]] to learn how to update the firmware and gateware on your LimeSDR.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Hardware_Installation&diff=1716
LimeSDR Hardware Installation
2018-04-12T15:53:52Z
<p>Ghalfacree: Added LimeSDR PCIe installation instructions.</p>
<hr />
<div>The LimeSDR family of software defined radios are designed to make it as easy as possible to get started in the world of SDR. Before you can begin, though, you'll need to run through some simple steps in order to get your LimeSDR installed and configured correctly.<br />
<br />
==Unpacking==<br />
The LimeSDR family includes the LimeSDR USB, LimeSDR Mini, and LimeSDR PCIe (PCI Express) software defined radio devices. The first two of these are similar, differing only in their size and base capabilities and connecting to the host PC via a USB interface; the latter is functionally identical to the LimeSDR USB but connects to a PCI Express (PCIe) interface as an internal add-in card.<br />
<br />
Begin by removing your LimeSDR from its packaging. Note the anti-static bag, used to protect the LimeSDR during transit. The LimeSDR is a sensitive electronic device, and should be handled with appropriate precautions against electrostatic discharge (ESD); be sure to ground yourself, for example by tapping your finger on the exposed metal of a radiator pipe, before removing it from the anti-static bag, and ensure you hold the board by its edges. Also be careful of components, such as the small male pin headers, which protrude above the surface of the LimeSDR board; these can catch on the edge of the bag.<br />
<br />
==Connecting Antennas==<br />
The LimeSDR family of SDR boards have multiple RF ports, to which antennas appropriate to the frequencies in which you will be operating must be connected. Some hardware bundles include antennas; others come without. The port you use depends on whether you will be receiving or transmitting and at what frequency. The following sections describe the ports and their capabilities.<br />
<br />
When configuring your software, be sure to select the ports to which you have connected antennas; the LimeSDR does not automatically sense if an antenna is connected to a port or not.<br />
<br />
===LimeSDR USB RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR USB has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
===LimeSDR Mini RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR Mini RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - 2GHz - 3.5GHz frequency range<br />
|-<br />
|RX1_W<br />
|Channel 1 RX - 10MHz - 2GHz frequency range<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - 2GHz - 3.5GHz frequency range<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - 10MHz - 2GHz frequency range<br />
|-<br />
|}<br />
<br />
The LimeSDR Mini has SMA connectors for its ports, requiring no additional conversion for connection to external antennas. Depending on desired positioning, however, SMA extension cables will give you increased flexibility in positioning and alignment.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_W ports within the frequency bands listed.<br />
<br />
===LimeSDR PCIe RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR PCIe has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
==Case Assembly==<br />
If you have purchased the official LimeSDR Acrylic Case for the LimeSDR USB, see [https://github.com/myriadrf/LimeSDR-USB_acrylic_case#assembly the assembly instructions on GitHub]. If you have purchased a third-party case, consult the documentation from your case manufacturer for instructions.<br />
<br />
If you do not have a case for your LimeSDR, it can be used without one providing you are careful to ensure that it does not come into contact with electrically conductive surfaces - including metal desk coverings - while in use, or the board may suffer a damaging electrical short.<br />
<br />
==Connecting a LimeSDR USB or LimeSDR Mini to a PC==<br />
The LimeSDR USB and LimeSDR Mini both connect to a host computer over a USB 3.0 interface, although both are backwards compatible with older USB 2.0 ports at a reduced rate of operation. The LimeSDR Mini includes a male USB plug in its design; simply insert this directly into a free USB 3.0 Type A port on your host computer or via a good-quality USB 3.0 extension lead for more flexible positioning.<br />
<br />
The LimeSDR USB comes with a USB 3.0 splitter cable. While the LimeSDR USB draws its power entirely via USB, negating the need for an external power supply, it can require more power than a single uSB port can provide. The splitter cable is wired so that the USB plug with a blue inner, in the middle of the cable, has both power and data connections while the USB plug with a white inner, at the far end of the cable, has only power connections.<br />
<br />
Begin by connecting the white, power, USB plug to a free USB 2.0 or 3.0 port on your host computer, then connect the blue, power and data, USB plug to a free USB 3.0 port. The final end of the cable, which is terminated in a USB 3.0 SuperSpeed connector, should finally be inserted into the matching connector on the LimeSDR USB. Note that there is no power switch on the LimeSDR USB; as soon as the cable is connected, the board will become live. Disconnecting the LimeSDR USB should be performed in the opposite order, starting with the USB 3.0 SuperSpeed connector on the LimeSDR USB itself.<br />
<br />
If using the LimeSDR USB with a laptop or all-in-one system, the splitter cable may not reach between USB sockets. If so, attach a good-quality USB extension cable - not supplied - to the white, power-only, connector of the splitter to extend its reach.<br />
<br />
==Connecting a LimeSDR PCIe to a PC==<br />
The LimeSDR PCIe is an internal expansion card connecting to the PCI Express bus. As such, it should only be installed with the computer completely powered off.<br />
<br />
Remove the side of your computer's case and any other components required to gain access to the motherboard's expansion slots. The LimeSDR PCIe requires a 4-lane (4x) PCI Express slot to operate; if no dedicated x4 PCIe slot is available, it can be installed in an x8 or x16 PCIe slot.<br />
<br />
Remove the blanking plate from the rear panel of your case, if installed, and insert the LimeSDR PCIe with the status LEDs facing towards the rear of the case. No dedicated power connector is required; power is drawn from the PCI Express slot.<br />
<br />
Before replacing the side of your case, connect your antennas or pigtail leads to the U.FL connectors on the card, as these will not be accessible once the side is replaced. Route these though the expansion slot at the rear of the case for ease of access.<br />
<br />
Replace the side of your case and power your computer back on.<br />
<br />
==Next Steps==<br />
Windows users will now need to install the LimeSDR driver, following the instructions on the [[LimeSDR Windows Driver Installation]] page. All other users should move on to [[LimeSDR Firmware Management]] to update their firmware and gateware to the latest releases, without which the LimeSDR may not operate as expected.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Windows_Driver_Installation&diff=1715
LimeSDR Windows Driver Installation
2018-04-12T15:27:31Z
<p>Ghalfacree: Added LimeSDR Mini driver section, renumbered LimeSDR USB subsections.</p>
<hr />
<div>The LimeSDR family of software defined radio boards requires drivers to be installed before it can be used on platforms running the Microsoft Windows family of operating systems. Follow these instructions to download and install the driver before trying to use the LimeSDR for the first time.<br />
<br />
Those using LimeSDR hardware on Linux or macOS can skip this step and move on to [[LimeSDR Firmware Management]] to upgrade the LimeSDR's firmware and gateware.<br />
<br />
==Installing the LimeSDR Mini Driver==<br />
<br />
The LimeSDR Mini uses an industry-standard FTDI chip for USB communication. In most cases, this driver is already available on Windows and the LimeSDR Mini can be used without manual installation.<br />
<br />
In the event that the default FTDI driver provided with your Windows installation does not operate correctly, please install the latest version as detailed below.<br />
<br />
===Downloading and Extracting the Driver===<br />
Download the latest version of the FTDI driver from [http://www.ftdichip.com/Drivers/D3XX.htm the FTDI website]. The name of this archive will depend on the version available, but should begin "FTD3XXDriver_WHYQLCertified". Extract the archive using Windows' built-in archive management or the tool of your choice.<br />
<br />
===Loading Device Manager===<br />
Connect your LimeSDR Mini to your host PC, if you have not already done so. Wait a few seconds for Windows to detect the device, then click on the Start Menu or press the Super key on your keyboard and type "Device Manager" followed by the Enter Key.<br />
<br />
In the list of device categories in the Device Manager window, expand "Other devices" and find "LimeSDR Mini" in the list. Right-click on this device then left-click on "Update Driver Software" to load the driver installation dialogue.<br />
<br />
[[File:LimeSDR-Mini drivers device manager update.png|thumb|center|600px|]]<br />
<br />
===Manually Installing the Driver===<br />
To ensure that Windows loads the correct driver, choose "Browse my computer for driver software" from the window that appears. Click the "Browse" button, then browse to the folder to which you extracted the driver archive followed by the sub-folder which matches your Windows version:<br />
<br />
* Windows 7<br />
* Windows 8<br />
* Windows 8.1<br />
* Windows 10<br />
<br />
If you have a 64-bit Windows installation, first navigate to the "x64" subfolder followed by the folder which matches your Windows version.<br />
<br />
[[File:LimeSDR-Mini drivers search.png|thumb|center|600px|]]<br />
<br />
Click "OK", then click "Next" to begin driver installation. A security dialogue may appear; if so, grant permission for the installation to continue. After a few seconds, Windows will display a dialogue confirming that the driver has been installed.<br />
<br />
[[File:LimeSDR-Mini drivers finished.png|thumb|center|600px|]]<br />
<br />
===Confirming Driver Installation===<br />
To confirm that the driver has been successfully loaded, click "Close" to return to the main Device Manager window. Expand the device category labelled "Universal Serial Bus controllers" and find "FTDI FT601 USB 3.0 Bridge Device" in the list; its logo should be a USB connector with no exclamation mark or other warning symbol present.<br />
<br />
[[File:LimeSDR-Mini_drivers_device_manager_updated.png|thumb|center|600px|]]<br />
<br />
If the device does not appear, disconnect the LimeSDR Mini from your system and reconnect it to refresh Device Manager.<br />
<br />
==Installing the LimeSDR USB Driver==<br />
<br />
The LimeSDR USB uses a special chip, known as the FX3, to handle USB communications. This requires the installation of a specific driver, detailed below.<br />
<br />
===Downloading and Extracting the Driver===<br />
Download the latest version of the LimeSDR USB driver from the Myriad-RF GitHub repository using [https://github.com/myriadrf/Windows-drivers/archive/master.zip this link]. The name of the archive will be "Windows-drivers-master.zip". Extract the archive using Windows' built-in archive management or the archive tool of your choice.<br />
<br />
===Loading Device Manager===<br />
Connect your LimeSDR USB to your host PC, if you have not already done so. Wait a few seconds for Windows to detect the device, then click on the Start Menu or press the Super key on your keyboard and type "Device Manager" followed by the Enter Key.<br />
<br />
In the list of device categories in the Device Manager window, expand "Other devices" and find "LimeSDR-USB" in the list. Right-click on this device then left-click on "Update Driver Software" to load the driver installation dialogue.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Update_Software.png|thumb|center|600px|]]<br />
<br />
===Manually Installing the Driver===<br />
To ensure that Windows loads the correct driver, choose "Browse my computer for driver software" from the window that appears. Click the "Browse" button, then browse to the folder to which you extracted the driver archive followed by the sub-folder which matches your Windows version:<br />
<br />
* wxp - Windows XP<br />
* vista - Windows Vista<br />
* Win7 - Windows 7<br />
* Win8 - Windows 8<br />
* Win81 - Windows 8.1<br />
* Win10 - Windows 10<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Select.png|thumb|center|600px|]]<br />
<br />
Click "OK", then click "Next" to begin driver installation. A security dialogue may appear; if so, grant permission for the installation to continue. After a few seconds, Windows will display a dialogue confirming that the driver has been installed.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Succesfull_Inst.png|thumb|center|600px|]]<br />
<br />
===Confirming Driver Installation===<br />
To confirm that the driver has been successfully loaded, click "Close" to return to the main Device Manager window. Expand the device category labelled "Universal Serial Bus controllers" and find "Myriad-RF LimeSDR-USB" in the list; its logo should be a USB connector with no exclamation mark or other warning symbol present.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Device_Man_Succ.png|thumb|center|600px|]]<br />
<br />
If the device does not appear, disconnect the LimeSDR from your system and reconnect it to refresh Device Manager. Make sure that both the power and data USB connectors are plugged into your host PC, as inadequate power can cause the LimeSDR USB to fail to operate correctly.<br />
<br />
==Next Steps==<br />
With the driver installed, you can move on to [[LimeSDR Firmware Management]] to learn how to update the firmware and gateware on your LimeSDR.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Firmware_Management&diff=1714
LimeSDR Firmware Management
2018-04-12T07:10:15Z
<p>Ghalfacree: /* Fixing LimeSDR USB FX3 WestBridge Corruption */</p>
<hr />
<div>As well as software running on the host PC, the LimeSDR family of software-defined radios has two user-upgradeable pieces of 'soft' ware running directly on its board: these are the firmware and the gateware, the latter defining how the on-board field programmable gate array (FPGA) should operate.<br />
<br />
It is important that the firmware and gateware be kept up-to-date, especially when installing a new LimeSDR or upgrading Lime Suite on a system with an existing LimeSDR. Using a LimeSDR with a firmware or gateware version that does not match the version expected by Lime Suite or other controlling software can cause errors or other issues with both transmission and reception, and can in some cases result in the LimeSDR failing to operate at all until its firmware and gateware are both updated.<br />
<br />
==Updating the Firmware and Gateware==<br />
The firmware and gateware files for all supported LimeSDR boards are supplied with the Lime Suite software stack. If you have not yet installed Lime Suite, do so by following the guide at [[Getting Started with Lime Suite]].<br />
<br />
The firmware and gateware revisions should match the revisions shipped with Lime Suite; if they do not, Lime Suite will display an error about a version mismatch. Note that this mismatch can occur with firmware and gateware that is older than the version of Lime Suite you are using and that is newer, the latter potentially causing issues if you - for whatever reason - wish to use an older release of Lime Suite with a LimeSDR that has already been updated on a newer Lime Suite installation. In these cases, the term "updating" refers to replacing the existing firmware and gateware on the board with the version supplied with Lime Suite; this can be a newer or older version than is already on the board.<br />
<br />
With LimeSuite installed, open your operating system's command line interface - the Terminal in Linux and macOS and Command Prompt or PowerShell in Windows - and, with the LimeSDR connected to your host PC, run the following command:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
Note the capital letters in "LimeUtil"; these are required in case-sensitive operating systems.<br />
<br />
The update process will take a few minutes to complete, during which time progress information will be printed to the terminal. It is important that the process is allowed to fully complete; during the update process do not close your command line interface window, shut down or suspend your computer, or disconnect any cables connected to the LimeSDR.<br />
<br />
Once the process is complete, the LimeSDR will automatically reboot to load the new firmware and gateware. If you are still receiving an error about version mismatches in Lime Suite at this point, disconnect and reconnect the LimeSDR in order to force a refresh.<br />
<br />
==Obtaining the Latest Firmware and Gateware==<br />
The latest firmware and gateware versions are shipped as standard with each new Lime Suite release. Using firmware and gateware images which are not distributed with Lime Suite - for example, by manually downloading the individual files from the GitHub repository - is not advised, as using a newer release of firmware and gateware with an older version of Lime Suite can cause as many problems as using a newer version of Lime Suite with older firmware and gateware.<br />
<br />
To upgrade your version of Lime Suite and obtain the latest firmware and gateware files, use your operating system's package manager (where available) or download and install the latest version over the top of your existing version using the instructions on the page [[Getting Started with Lime Suite]].<br />
<br />
==Recovering from a Bad Update==<br />
If the firmware and gateware update process is interrupted, restart it by typing:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
This will begin the flash process again, and will overwrite any partial or corrupted flash contents.<br />
<br />
==Fixing LimeSDR USB FX3 WestBridge Corruption==<br />
<br />
If using a LimeSDR USB, an interruption in the firmware and gateware update process can result in the FX3 chip, responsible for USB communications, entering 'bootloader' mode; this is not the case for the LimeSDR Mini, which uses a different USB controller. In this mode, the chip will not communicate with the rest of the LimeSDR USB board. The primary symptom of this is that the LimeSDR disappears from the list of connected devices and is replaced with a device named "WestBridge."<br />
<br />
The FX3 can be forced into bootloader mode by removing the jumper marked "FX3 BOOT" on the top of the board. If your LimeSDR USB is showing as a WestBridge device, first check that the FX3 BOOT jumper is correctly in place; if it is not, replace it so it is bridging the two pins and reconnect the LimeSDR USB to your host device.<br />
<br />
If the FX3 Boot jumper is correctly in place and the LimeSDR USB still shows as a WestBridge device, this indicates corruption in the FX3 firmware. To fix this, first download the [https://github.com/myriadrf/LimeSDR-USB_FX3/blob/master/Debug/LimeSDR-USB_fx3_fw.img latest LimeSDR USB FX3 firmware image]. Next, load Lime Suite GUI and use the following steps to flash the firmware:<br />
<br />
# Load Lime Suite GUI<br />
# In Lime Suite GUI, click "Options," then "Connection Settings," choose "WestBridge" from the list, then finally click "Connect".<br />
# Click "Modules" then "Programming."<br />
# Select "FX3" in the "Device" list, then choose "Firmware to RAM" in the "Programming Mode" list.<br />
# Browse to the firmware file you downloaded, making sure to pick the correct file.<br />
# Click "Program" and allow the flashing process to complete. The LimeSDR USB will restart.<br />
# Return to the "Options" menu, click "Connection Settings, then click "Connect" to re-connect to your LimeSDR USB.<br />
# Click "Modules" then "Programming."<br />
# Select "Automatic" in the "Device" list and "Automatic Update" in the "Programming Mode" list.<br />
# Click "Program" to update the firmware and gateware.<br />
<br />
Your LimeSDR USB will now have the correct firmware and gateware files installed.<br />
<br />
==Next Steps==<br />
If you are following these steps in order to set up your new LimeSDR device, continue on to [[Testing the LimeSDR]].<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Firmware_Management&diff=1713
LimeSDR Firmware Management
2018-04-12T07:09:29Z
<p>Ghalfacree: Added information on the FX3 Boot jumper.</p>
<hr />
<div>As well as software running on the host PC, the LimeSDR family of software-defined radios has two user-upgradeable pieces of 'soft' ware running directly on its board: these are the firmware and the gateware, the latter defining how the on-board field programmable gate array (FPGA) should operate.<br />
<br />
It is important that the firmware and gateware be kept up-to-date, especially when installing a new LimeSDR or upgrading Lime Suite on a system with an existing LimeSDR. Using a LimeSDR with a firmware or gateware version that does not match the version expected by Lime Suite or other controlling software can cause errors or other issues with both transmission and reception, and can in some cases result in the LimeSDR failing to operate at all until its firmware and gateware are both updated.<br />
<br />
==Updating the Firmware and Gateware==<br />
The firmware and gateware files for all supported LimeSDR boards are supplied with the Lime Suite software stack. If you have not yet installed Lime Suite, do so by following the guide at [[Getting Started with Lime Suite]].<br />
<br />
The firmware and gateware revisions should match the revisions shipped with Lime Suite; if they do not, Lime Suite will display an error about a version mismatch. Note that this mismatch can occur with firmware and gateware that is older than the version of Lime Suite you are using and that is newer, the latter potentially causing issues if you - for whatever reason - wish to use an older release of Lime Suite with a LimeSDR that has already been updated on a newer Lime Suite installation. In these cases, the term "updating" refers to replacing the existing firmware and gateware on the board with the version supplied with Lime Suite; this can be a newer or older version than is already on the board.<br />
<br />
With LimeSuite installed, open your operating system's command line interface - the Terminal in Linux and macOS and Command Prompt or PowerShell in Windows - and, with the LimeSDR connected to your host PC, run the following command:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
Note the capital letters in "LimeUtil"; these are required in case-sensitive operating systems.<br />
<br />
The update process will take a few minutes to complete, during which time progress information will be printed to the terminal. It is important that the process is allowed to fully complete; during the update process do not close your command line interface window, shut down or suspend your computer, or disconnect any cables connected to the LimeSDR.<br />
<br />
Once the process is complete, the LimeSDR will automatically reboot to load the new firmware and gateware. If you are still receiving an error about version mismatches in Lime Suite at this point, disconnect and reconnect the LimeSDR in order to force a refresh.<br />
<br />
==Obtaining the Latest Firmware and Gateware==<br />
The latest firmware and gateware versions are shipped as standard with each new Lime Suite release. Using firmware and gateware images which are not distributed with Lime Suite - for example, by manually downloading the individual files from the GitHub repository - is not advised, as using a newer release of firmware and gateware with an older version of Lime Suite can cause as many problems as using a newer version of Lime Suite with older firmware and gateware.<br />
<br />
To upgrade your version of Lime Suite and obtain the latest firmware and gateware files, use your operating system's package manager (where available) or download and install the latest version over the top of your existing version using the instructions on the page [[Getting Started with Lime Suite]].<br />
<br />
==Recovering from a Bad Update==<br />
If the firmware and gateware update process is interrupted, restart it by typing:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
This will begin the flash process again, and will overwrite any partial or corrupted flash contents.<br />
<br />
==Fixing LimeSDR USB FX3 WestBridge Corruption==<br />
<br />
If using a LimeSDR USB, an interruption in the firmware and gateware update process can result in the FX3 chip, responsible for USB communications, entering 'bootloader' mode; this is not the case for the LimeSDR Mini, which uses a different USB controller. In this mode, the chip will not communicate with the rest of the LimeSDR USB board. The primary symptom of this is that the LimeSDR disappears from the list of connected devices and is replaced with a device named "WestBridge."<br />
<br />
The FX3 can be forced into bootloader mode by removing the jumped marked "FX3 BOOT" on the top of the board. If your LimeSDR USB is showing as a WestBridge device, first check that the FX3 BOOT jumper is correctly in place; if it is not, replace it so it is bridging the two pins and reconnect the LimeSDR USB to your host device.<br />
<br />
If the FX3 Boot jumper is correctly in place and the LimeSDR USB still shows as a WestBridge device, this indicates corruption in the FX3 firmware. To fix this, first download the [https://github.com/myriadrf/LimeSDR-USB_FX3/blob/master/Debug/LimeSDR-USB_fx3_fw.img latest LimeSDR USB FX3 firmware image]. Next, load Lime Suite GUI and use the following steps to flash the firmware:<br />
<br />
# Load Lime Suite GUI<br />
# In Lime Suite GUI, click "Options," then "Connection Settings," choose "WestBridge" from the list, then finally click "Connect".<br />
# Click "Modules" then "Programming."<br />
# Select "FX3" in the "Device" list, then choose "Firmware to RAM" in the "Programming Mode" list.<br />
# Browse to the firmware file you downloaded, making sure to pick the correct file.<br />
# Click "Program" and allow the flashing process to complete. The LimeSDR USB will restart.<br />
# Return to the "Options" menu, click "Connection Settings, then click "Connect" to re-connect to your LimeSDR USB.<br />
# Click "Modules" then "Programming."<br />
# Select "Automatic" in the "Device" list and "Automatic Update" in the "Programming Mode" list.<br />
# Click "Program" to update the firmware and gateware.<br />
<br />
Your LimeSDR USB will now have the correct firmware and gateware files installed.<br />
<br />
==Next Steps==<br />
If you are following these steps in order to set up your new LimeSDR device, continue on to [[Testing the LimeSDR]].<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Installing_Lime_Suite_on_Linux&diff=1712
Installing Lime Suite on Linux
2018-04-11T15:23:12Z
<p>Ghalfacree: /* Viewing the Configuration */</p>
<hr />
<div>Lime Suite is a cross-platform software stack for the configuration and use of a range of software defined radio (SDR) platforms, including the LimeSDR family. The following instructions are for users of Linux-based operating systems, and primarily focus on Canonical's Ubuntu Linux distribution.<br />
<br />
==Installing via PPA==<br />
The easiest way to install Lime Suite is via Personal Package Archive (PPA), from the official Myriad-RF repository. This will ensure not only that you are installing the latest version, but that it is kept up-to-date via your operating system's package manager along with all your other software.<br />
<br />
Open a terminal session, and type the following commands to add the PPA and refresh the list of available packages:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To install Lime Suite and its dependencies, type the following command:<br />
<br />
<source lang="bash"><br />
sudo apt install limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
</source><br />
<br />
Once installed, Lime Suite and its dependencies will be automatically updated along with the rest of your software by your package manager. LimeSDR users will still need to manually update the firmware and gateware on their device when an update is made available, as described in [[LimeSDR Firmware Management]].<br />
<br />
===Uninstalling via PPA===<br />
To remove Lime Suite and its dependencies when installed via PPA, type the following commands:<br />
<br />
<source lang="bash"><br />
sudo apt remove limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
sudo add-apt-repository -y -r ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To remove Lime Suite, its dependencies, and all configuration files, substitute "purge" for "remove" in the first command.<br />
<br />
==Building from Source==<br />
For other Linux-based operating systems, Lime Suite should be built from source. Note that this is only required when installing from the official PPA, as above, is not possible; under no circumstances should a system have both a PPA-installed and self-built copy of Lime Suite installed, or errors will almost certainly follow.<br />
<br />
===Installing Dependencies===<br />
Lime Suite depends on a range of additional software and libraries to operate. The majority of these can be installed using your distribution's package manager; in some cases, however, the versions of packages provided in official distribution repositories are too old to function with the latest Lime Suite release. For distributions with PPA support, the following command:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
will add the official Myriad-RF PPA, which includes up-to-date versions of these dependencies, to your system. For distributions without PPA support, the "soapysdr" library should be built and installed from the latest source available on the project's [https://github.com/pothosware/SoapySDR GitHub repository] before attempting to build Lime Suite.<br />
<br />
To install the dependencies use the following command, excluding "libsoapysdr-dev" if you have compiled and installed "soapysdr" from source:<br />
<br />
<source lang="bash"><br />
sudo apt install libsoapysdr-dev libi2c-dev libusb-1.0-0-dev git g++ cmake libsqlite3-dev libwxgtk3.0-dev freeglut3-dev<br />
</source><br />
<br />
For distributions which do not use the apt package manager, install the listed packages with your distribution's own package manager (e.g. yum, pacman.)<br />
<br />
===Downloading the Source===<br />
To obtain the latest Lime Suite source files from the "Stable" branch, clone and checkout the repository using the following command:<br />
<br />
<source lang="bash"><br />
git clone https://github.com/myriadrf/LimeSuite.git<br />
cd LimeSuite<br />
git checkout stable<br />
</source><br />
<br />
If you have previously cloned the repository to install an older release, change to the LimeSuite directory and update the source with the following command instead:<br />
<br />
<source lang="bash"><br />
git pull<br />
cd builddir<br />
make clean<br />
</source><br />
<br />
===Viewing the Configuration===<br />
To create a build directory for Lime Suite, type the following commands:<br />
<br />
<source lang="bash"><br />
mkdir builddir<br />
cd builddir<br />
</source><br />
<br />
To configure the build process, and to see what components are enabled and disabled, use the following command:<br />
<br />
<source lang="bash"><br />
cmake ../<br />
</source><br />
<br />
===Building and Installing Lime Suite===<br />
To begin the build process, type the following command:<br />
<br />
<source lang="bash"><br />
make -j$(nproc)<br />
</source><br />
<br />
The build process can take several minutes to complete, depending on the amount of memory and number of processor cores available on your system. When Lime Suite is built, install it by typing:<br />
<br />
<source lang="bash"><br />
sudo make install<br />
sudo ldconfig<br />
cd ../udev-rules<br />
sudo ./install.sh<br />
</source><br />
<br />
The building and installation process is now complete. You can delete the LimeSuite directory to save space, if required, or keep it to make upgrading to the next release as simple as possible.<br />
<br />
==Next Steps==<br />
If you have installed Lime Suite to use a LimeSDR device, follow the instructions in [[Getting Started with the LimeSDR]] to install, configure, and test your hardware.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Installing_Lime_Suite_on_Linux&diff=1711
Installing Lime Suite on Linux
2018-04-11T15:22:55Z
<p>Ghalfacree: /* Downloading the Source */</p>
<hr />
<div>Lime Suite is a cross-platform software stack for the configuration and use of a range of software defined radio (SDR) platforms, including the LimeSDR family. The following instructions are for users of Linux-based operating systems, and primarily focus on Canonical's Ubuntu Linux distribution.<br />
<br />
==Installing via PPA==<br />
The easiest way to install Lime Suite is via Personal Package Archive (PPA), from the official Myriad-RF repository. This will ensure not only that you are installing the latest version, but that it is kept up-to-date via your operating system's package manager along with all your other software.<br />
<br />
Open a terminal session, and type the following commands to add the PPA and refresh the list of available packages:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To install Lime Suite and its dependencies, type the following command:<br />
<br />
<source lang="bash"><br />
sudo apt install limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
</source><br />
<br />
Once installed, Lime Suite and its dependencies will be automatically updated along with the rest of your software by your package manager. LimeSDR users will still need to manually update the firmware and gateware on their device when an update is made available, as described in [[LimeSDR Firmware Management]].<br />
<br />
===Uninstalling via PPA===<br />
To remove Lime Suite and its dependencies when installed via PPA, type the following commands:<br />
<br />
<source lang="bash"><br />
sudo apt remove limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
sudo add-apt-repository -y -r ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To remove Lime Suite, its dependencies, and all configuration files, substitute "purge" for "remove" in the first command.<br />
<br />
==Building from Source==<br />
For other Linux-based operating systems, Lime Suite should be built from source. Note that this is only required when installing from the official PPA, as above, is not possible; under no circumstances should a system have both a PPA-installed and self-built copy of Lime Suite installed, or errors will almost certainly follow.<br />
<br />
===Installing Dependencies===<br />
Lime Suite depends on a range of additional software and libraries to operate. The majority of these can be installed using your distribution's package manager; in some cases, however, the versions of packages provided in official distribution repositories are too old to function with the latest Lime Suite release. For distributions with PPA support, the following command:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
will add the official Myriad-RF PPA, which includes up-to-date versions of these dependencies, to your system. For distributions without PPA support, the "soapysdr" library should be built and installed from the latest source available on the project's [https://github.com/pothosware/SoapySDR GitHub repository] before attempting to build Lime Suite.<br />
<br />
To install the dependencies use the following command, excluding "libsoapysdr-dev" if you have compiled and installed "soapysdr" from source:<br />
<br />
<source lang="bash"><br />
sudo apt install libsoapysdr-dev libi2c-dev libusb-1.0-0-dev git g++ cmake libsqlite3-dev libwxgtk3.0-dev freeglut3-dev<br />
</source><br />
<br />
For distributions which do not use the apt package manager, install the listed packages with your distribution's own package manager (e.g. yum, pacman.)<br />
<br />
===Downloading the Source===<br />
To obtain the latest Lime Suite source files from the "Stable" branch, clone and checkout the repository using the following command:<br />
<br />
<source lang="bash"><br />
git clone https://github.com/myriadrf/LimeSuite.git<br />
cd LimeSuite<br />
git checkout stable<br />
</source><br />
<br />
If you have previously cloned the repository to install an older release, change to the LimeSuite directory and update the source with the following command instead:<br />
<br />
<source lang="bash"><br />
git pull<br />
cd builddir<br />
make clean<br />
</source><br />
<br />
===Viewing the Configuration===<br />
To create a build directory for Lime Suite, type the following commands:<br />
<br />
<source lang="bash"><br />
cd LimeSuite<br />
mkdir builddir<br />
cd builddir<br />
</source><br />
<br />
To configure the build process, and to see what components are enabled and disabled, use the following command:<br />
<br />
<source lang="bash"><br />
cmake ../<br />
</source><br />
<br />
===Building and Installing Lime Suite===<br />
To begin the build process, type the following command:<br />
<br />
<source lang="bash"><br />
make -j$(nproc)<br />
</source><br />
<br />
The build process can take several minutes to complete, depending on the amount of memory and number of processor cores available on your system. When Lime Suite is built, install it by typing:<br />
<br />
<source lang="bash"><br />
sudo make install<br />
sudo ldconfig<br />
cd ../udev-rules<br />
sudo ./install.sh<br />
</source><br />
<br />
The building and installation process is now complete. You can delete the LimeSuite directory to save space, if required, or keep it to make upgrading to the next release as simple as possible.<br />
<br />
==Next Steps==<br />
If you have installed Lime Suite to use a LimeSDR device, follow the instructions in [[Getting Started with the LimeSDR]] to install, configure, and test your hardware.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Firmware_Management&diff=1710
LimeSDR Firmware Management
2018-04-11T15:19:55Z
<p>Ghalfacree: /* Fixing LimeSDR USB FX3 'WestBridge' Corruption */</p>
<hr />
<div>As well as software running on the host PC, the LimeSDR family of software-defined radios has two user-upgradeable pieces of 'soft' ware running directly on its board: these are the firmware and the gateware, the latter defining how the on-board field programmable gate array (FPGA) should operate.<br />
<br />
It is important that the firmware and gateware be kept up-to-date, especially when installing a new LimeSDR or upgrading Lime Suite on a system with an existing LimeSDR. Using a LimeSDR with a firmware or gateware version that does not match the version expected by Lime Suite or other controlling software can cause errors or other issues with both transmission and reception, and can in some cases result in the LimeSDR failing to operate at all until its firmware and gateware are both updated.<br />
<br />
==Updating the Firmware and Gateware==<br />
The firmware and gateware files for all supported LimeSDR boards are supplied with the Lime Suite software stack. If you have not yet installed Lime Suite, do so by following the guide at [[Getting Started with Lime Suite]].<br />
<br />
The firmware and gateware revisions should match the revisions shipped with Lime Suite; if they do not, Lime Suite will display an error about a version mismatch. Note that this mismatch can occur with firmware and gateware that is older than the version of Lime Suite you are using and that is newer, the latter potentially causing issues if you - for whatever reason - wish to use an older release of Lime Suite with a LimeSDR that has already been updated on a newer Lime Suite installation. In these cases, the term "updating" refers to replacing the existing firmware and gateware on the board with the version supplied with Lime Suite; this can be a newer or older version than is already on the board.<br />
<br />
With LimeSuite installed, open your operating system's command line interface - the Terminal in Linux and macOS and Command Prompt or PowerShell in Windows - and, with the LimeSDR connected to your host PC, run the following command:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
Note the capital letters in "LimeUtil"; these are required in case-sensitive operating systems.<br />
<br />
The update process will take a few minutes to complete, during which time progress information will be printed to the terminal. It is important that the process is allowed to fully complete; during the update process do not close your command line interface window, shut down or suspend your computer, or disconnect any cables connected to the LimeSDR.<br />
<br />
Once the process is complete, the LimeSDR will automatically reboot to load the new firmware and gateware. If you are still receiving an error about version mismatches in Lime Suite at this point, disconnect and reconnect the LimeSDR in order to force a refresh.<br />
<br />
==Obtaining the Latest Firmware and Gateware==<br />
The latest firmware and gateware versions are shipped as standard with each new Lime Suite release. Using firmware and gateware images which are not distributed with Lime Suite - for example, by manually downloading the individual files from the GitHub repository - is not advised, as using a newer release of firmware and gateware with an older version of Lime Suite can cause as many problems as using a newer version of Lime Suite with older firmware and gateware.<br />
<br />
To upgrade your version of Lime Suite and obtain the latest firmware and gateware files, use your operating system's package manager (where available) or download and install the latest version over the top of your existing version using the instructions on the page [[Getting Started with Lime Suite]].<br />
<br />
==Recovering from a Bad Update==<br />
If the firmware and gateware update process is interrupted, restart it by typing:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
This will begin the flash process again, and will overwrite any partial or corrupted flash contents.<br />
<br />
==Fixing LimeSDR USB FX3 WestBridge Corruption==<br />
<br />
If using a LimeSDR USB, an interruption in the firmware and gateware update process can result in the FX3 chip, responsible for USB communications, entering 'bootloader' mode; this is not the case for the LimeSDR Mini, which uses a different USB controller. In this mode, the chip will not communicate with the rest of the LimeSDR USB board.<br />
<br />
The primary symptom of this is that the LimeSDR disappears from the list of connected devices and is replaced with a device named 'WestBridge.' To fix this first download the [https://github.com/myriadrf/LimeSDR-USB_FX3/blob/master/Debug/LimeSDR-USB_fx3_fw.img latest LimeSDR USB FX3 firmware image]. Next, load Lime Suite GUI and use the following steps to flash the firmware:<br />
<br />
# Load Lime Suite GUI<br />
# In Lime Suite GUI, click "Options," then "Connection Settings," choose "WestBridge" from the list, then finally click "Connect".<br />
# Click "Modules" then "Programming."<br />
# Select "FX3" in the "Device" list, then choose "Firmware to RAM" in the "Programming Mode" list.<br />
# Browse to the firmware file you downloaded, making sure to pick the correct file.<br />
# Click "Program" and allow the flashing process to complete. The LimeSDR USB will restart.<br />
# Return to the "Options" menu, click "Connection Settings, then click "Connect" to re-connect to your LimeSDR USB.<br />
# Click "Modules" then "Programming."<br />
# Select "Automatic" in the "Device" list and "Automatic Update" in the "Programming Mode" list.<br />
# Click "Program" to update the firmware and gateware.<br />
<br />
Your LimeSDR USB will now have the correct firmware and gateware files installed.<br />
<br />
==Next Steps==<br />
If you are following these steps in order to set up your new LimeSDR device, continue on to [[Testing the LimeSDR]].<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Firmware_Management&diff=1709
LimeSDR Firmware Management
2018-04-11T15:18:38Z
<p>Ghalfacree: Split out FX3 update information.</p>
<hr />
<div>As well as software running on the host PC, the LimeSDR family of software-defined radios has two user-upgradeable pieces of 'soft' ware running directly on its board: these are the firmware and the gateware, the latter defining how the on-board field programmable gate array (FPGA) should operate.<br />
<br />
It is important that the firmware and gateware be kept up-to-date, especially when installing a new LimeSDR or upgrading Lime Suite on a system with an existing LimeSDR. Using a LimeSDR with a firmware or gateware version that does not match the version expected by Lime Suite or other controlling software can cause errors or other issues with both transmission and reception, and can in some cases result in the LimeSDR failing to operate at all until its firmware and gateware are both updated.<br />
<br />
==Updating the Firmware and Gateware==<br />
The firmware and gateware files for all supported LimeSDR boards are supplied with the Lime Suite software stack. If you have not yet installed Lime Suite, do so by following the guide at [[Getting Started with Lime Suite]].<br />
<br />
The firmware and gateware revisions should match the revisions shipped with Lime Suite; if they do not, Lime Suite will display an error about a version mismatch. Note that this mismatch can occur with firmware and gateware that is older than the version of Lime Suite you are using and that is newer, the latter potentially causing issues if you - for whatever reason - wish to use an older release of Lime Suite with a LimeSDR that has already been updated on a newer Lime Suite installation. In these cases, the term "updating" refers to replacing the existing firmware and gateware on the board with the version supplied with Lime Suite; this can be a newer or older version than is already on the board.<br />
<br />
With LimeSuite installed, open your operating system's command line interface - the Terminal in Linux and macOS and Command Prompt or PowerShell in Windows - and, with the LimeSDR connected to your host PC, run the following command:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
Note the capital letters in "LimeUtil"; these are required in case-sensitive operating systems.<br />
<br />
The update process will take a few minutes to complete, during which time progress information will be printed to the terminal. It is important that the process is allowed to fully complete; during the update process do not close your command line interface window, shut down or suspend your computer, or disconnect any cables connected to the LimeSDR.<br />
<br />
Once the process is complete, the LimeSDR will automatically reboot to load the new firmware and gateware. If you are still receiving an error about version mismatches in Lime Suite at this point, disconnect and reconnect the LimeSDR in order to force a refresh.<br />
<br />
==Obtaining the Latest Firmware and Gateware==<br />
The latest firmware and gateware versions are shipped as standard with each new Lime Suite release. Using firmware and gateware images which are not distributed with Lime Suite - for example, by manually downloading the individual files from the GitHub repository - is not advised, as using a newer release of firmware and gateware with an older version of Lime Suite can cause as many problems as using a newer version of Lime Suite with older firmware and gateware.<br />
<br />
To upgrade your version of Lime Suite and obtain the latest firmware and gateware files, use your operating system's package manager (where available) or download and install the latest version over the top of your existing version using the instructions on the page [[Getting Started with Lime Suite]].<br />
<br />
==Recovering from a Bad Update==<br />
If the firmware and gateware update process is interrupted, restart it by typing:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
This will begin the flash process again, and will overwrite any partial or corrupted flash contents.<br />
<br />
==Fixing LimeSDR USB FX3 'WestBridge' Corruption==<br />
<br />
If using a LimeSDR USB, an interruption in the firmware and gateware update process can result in the FX3 chip, responsible for USB communications, entering 'bootloader' mode; this is not the case for the LimeSDR Mini, which uses a different USB controller. In this mode, the chip will not communicate with the rest of the LimeSDR USB board.<br />
<br />
The primary symptom of this is that the LimeSDR disappears from the list of connected devices and is replaced with a device named 'WestBridge.' To fix this first download the [https://github.com/myriadrf/LimeSDR-USB_FX3/blob/master/Debug/LimeSDR-USB_fx3_fw.img latest LimeSDR USB FX3 firmware image]. Next, load Lime Suite GUI and use the following steps to flash the firmware:<br />
<br />
# Load Lime Suite GUI<br />
# In Lime Suite GUI, click "Options," then "Connection Settings," choose "WestBridge" from the list, then finally click "Connect".<br />
# Click "Modules" then "Programming."<br />
# Select "FX3" in the "Device" list, then choose "Firmware to RAM" in the "Programming Mode" list.<br />
# Browse to the firmware file you downloaded, making sure to pick the correct file.<br />
# Click "Program" and allow the flashing process to complete. The LimeSDR USB will restart.<br />
# Return to the "Options" menu, click "Connection Settings, then click "Connect" to re-connect to your LimeSDR USB.<br />
# Click "Modules" then "Programming."<br />
# Select "Automatic" in the "Device" list and "Automatic Update" in the "Programming Mode" list.<br />
# Click "Program" to update the firmware and gateware.<br />
<br />
Your LimeSDR USB will now have the correct firmware and gateware files installed.<br />
<br />
==Next Steps==<br />
If you are following these steps in order to set up your new LimeSDR device, continue on to [[Testing the LimeSDR]].<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Hardware_Installation&diff=1708
LimeSDR Hardware Installation
2018-04-11T15:04:57Z
<p>Ghalfacree: Updated frequency table.</p>
<hr />
<div>The LimeSDR family of software defined radios are designed to make it as easy as possible to get started in the world of SDR. Before you can begin, though, you'll need to run through some simple steps in order to get your LimeSDR installed and configured correctly.<br />
<br />
==Unpacking==<br />
The LimeSDR family includes the LimeSDR USB and LimeSDR Mini software defined radio devices. Both of these are similar in operation, differing only in their size and base capabilities.<br />
<br />
Begin by removing your LimeSDR from its packaging. Note the anti-static bag, used to protect the LimeSDR during transit. The LimeSDR is a sensitive electronic device, and should be handled with appropriate precautions against electrostatic discharge (ESD); be sure to ground yourself, for example by tapping your finger on the exposed metal of a radiator pipe, before removing it from the anti-static bag, and ensure you hold the board by its edges. Also be careful of components, such as the small male pin headers, which protrude above the surface of the LimeSDR board; these can catch on the edge of the bag.<br />
<br />
==Connecting Antennas==<br />
The LimeSDR family of SDR boards have multiple RF ports, to which antennas appropriate to the frequencies in which you will be operating must be connected. Some hardware bundles include antennas; others come without. The port you use depends on whether you will be receiving or transmitting and at what frequency. The following sections describe the ports and their capabilities.<br />
<br />
When configuring your software, be sure to select the ports to which you have connected antennas; the LimeSDR does not automatically sense if an antenna is connected to a port or not.<br />
<br />
===LimeSDR USB RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR USB has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
===LimeSDR Mini RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR Mini RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - 2GHz - 3.5GHz frequency range<br />
|-<br />
|RX1_W<br />
|Channel 1 RX - 10MHz - 2GHz frequency range<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - 2GHz - 3.5GHz frequency range<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - 10MHz - 2GHz frequency range<br />
|-<br />
|}<br />
<br />
The LimeSDR Mini has SMA connectors for its ports, requiring no additional conversion for connection to external antennas. Depending on desired positioning, however, SMA extension cables will give you increased flexibility in positioning and alignment.<br />
<br />
==Case Assembly==<br />
If you have purchased the official LimeSDR Acrylic Case for the LimeSDR USB, see [https://github.com/myriadrf/LimeSDR-USB_acrylic_case#assembly the assembly instructions on GitHub]. If you have purchased a third-party case, consult the documentation from your case manufacturer for instructions.<br />
<br />
If you do not have a case for your LimeSDR, it can be used without one providing you are careful to ensure that it does not come into contact with electrically conductive surfaces - including metal desk coverings - while in use, or the board may suffer a damaging electrical short.<br />
<br />
==Connecting to a PC==<br />
The LimeSDR USB and LimeSDR Mini both connect to a host computer over a USB 3.0 interface, although both are backwards compatible with older USB 2.0 ports at a reduced rate of operation. The LimeSDR Mini includes a male USB plug in its design; simply insert this directly into a free USB 3.0 Type A port on your host computer or via a good-quality USB 3.0 extension lead for more flexible positioning.<br />
<br />
The LimeSDR USB comes with a USB 3.0 splitter cable. While the LimeSDR USB draws its power entirely via USB, negating the need for an external power supply, it can require more power than a single uSB port can provide. The splitter cable is wired so that the USB plug with a blue inner, in the middle of the cable, has both power and data connections while the USB plug with a white inner, at the far end of the cable, has only power connections.<br />
<br />
Begin by connecting the white, power, USB plug to a free USB 2.0 or 3.0 port on your host computer, then connect the blue, power and data, USB plug to a free USB 3.0 port. The final end of the cable, which is terminated in a USB 3.0 SuperSpeed connector, should finally be inserted into the matching connector on the LimeSDR USB. Note that there is no power switch on the LimeSDR USB; as soon as the cable is connected, the board will become live. Disconnecting the LimeSDR USB should be performed in the opposite order, starting with the USB 3.0 SuperSpeed connector on the LimeSDR USB itself.<br />
<br />
If using the LimeSDR USB with a laptop or all-in-one system, the splitter cable may not reach between USB sockets. If so, attach a good-quality USB extension cable - not supplied - to the white, power-only, connector of the splitter to extend its reach.<br />
<br />
==Next Steps==<br />
Windows users will now need to install the LimeSDR driver, following the instructions on the [[Windows Driver Installation]] page. All other users should move on to [[LimeSDR Firmware Management]] to update their firmware and gateware to the latest releases, without which the LimeSDR may not operate as expected.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Hardware_Installation&diff=1612
LimeSDR Hardware Installation
2018-03-27T14:12:10Z
<p>Ghalfacree: /* LimeSDR USB RF Ports */</p>
<hr />
<div>The LimeSDR family of software defined radios are designed to make it as easy as possible to get started in the world of SDR. Before you can begin, though, you'll need to run through some simple steps in order to get your LimeSDR installed and configured correctly.<br />
<br />
==Unpacking==<br />
The LimeSDR family includes the LimeSDR USB and LimeSDR Mini software defined radio devices. Both of these are similar in operation, differing only in their size and base capabilities.<br />
<br />
Begin by removing your LimeSDR from its packaging. Note the anti-static bag, used to protect the LimeSDR during transit. The LimeSDR is a sensitive electronic device, and should be handled with appropriate precautions against electrostatic discharge (ESD); be sure to ground yourself, for example by tapping your finger on the exposed metal of a radiator pipe, before removing it from the anti-static bag, and ensure you hold the board by its edges. Also be careful of components, such as the small male pin headers, which protrude above the surface of the LimeSDR board; these can catch on the edge of the bag.<br />
<br />
==Connecting Antennas==<br />
The LimeSDR family of SDR boards have multiple RF ports, to which antennas appropriate to the frequencies in which you will be operating must be connected. Some hardware bundles include antennas; others come without. The port you use depends on whether you will be receiving or transmitting and at what frequency. The following sections describe the ports and their capabilities.<br />
<br />
When configuring your software, be sure to select the ports to which you have connected antennas; the LimeSDR does not automatically sense if an antenna is connected to a port or not.<br />
<br />
===LimeSDR USB RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR USB has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
===LimeSDR Mini RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR Mini RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX<br />
|Channel 1 RX - all frequencies<br />
|-<br />
|TX<br />
|Channel 1 TX - all frequencies<br />
|}<br />
<br />
The LimeSDR Mini has SMA connectors for its ports, requiring no additional conversion for connection to external antennas. Depending on desired positioning, however, SMA extension cables will give you increased flexibility in positioning and alignment.<br />
<br />
==Case Assembly==<br />
If you have purchased the official LimeSDR Acrylic Case for the LimeSDR USB, see [https://github.com/myriadrf/LimeSDR-USB_acrylic_case#assembly the assembly instructions on GitHub]. If you have purchased a third-party case, consult the documentation from your case manufacturer for instructions.<br />
<br />
If you do not have a case for your LimeSDR, it can be used without one providing you are careful to ensure that it does not come into contact with electrically conductive surfaces - including metal desk coverings - while in use, or the board may suffer a damaging electrical short.<br />
<br />
==Connecting to a PC==<br />
The LimeSDR USB and LimeSDR Mini both connect to a host computer over a USB 3.0 interface, although both are backwards compatible with older USB 2.0 ports at a reduced rate of operation. The LimeSDR Mini includes a male USB plug in its design; simply insert this directly into a free USB 3.0 Type A port on your host computer or via a good-quality USB 3.0 extension lead for more flexible positioning.<br />
<br />
The LimeSDR USB comes with a USB 3.0 splitter cable. While the LimeSDR USB draws its power entirely via USB, negating the need for an external power supply, it can require more power than a single uSB port can provide. The splitter cable is wired so that the USB plug with a blue inner, in the middle of the cable, has both power and data connections while the USB plug with a white inner, at the far end of the cable, has only power connections.<br />
<br />
Begin by connecting the white, power, USB plug to a free USB 2.0 or 3.0 port on your host computer, then connect the blue, power and data, USB plug to a free USB 3.0 port. The final end of the cable, which is terminated in a USB 3.0 SuperSpeed connector, should finally be inserted into the matching connector on the LimeSDR USB. Note that there is no power switch on the LimeSDR USB; as soon as the cable is connected, the board will become live. Disconnecting the LimeSDR USB should be performed in the opposite order, starting with the USB 3.0 SuperSpeed connector on the LimeSDR USB itself.<br />
<br />
If using the LimeSDR USB with a laptop or all-in-one system, the splitter cable may not reach between USB sockets. If so, attach a good-quality USB extension cable - not supplied - to the white, power-only, connector of the splitter to extend its reach.<br />
<br />
==Next Steps==<br />
Windows users will now need to install the LimeSDR driver, following the instructions on the [[Windows Driver Installation]] page. All other users should move on to [[LimeSDR Firmware Management]] to update their firmware and gateware to the latest releases, without which the LimeSDR may not operate as expected.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Getting_Started_with_Myriad-RF&diff=1611
Getting Started with Myriad-RF
2018-03-27T14:11:42Z
<p>Ghalfacree: /* For LimeSDR Users */</p>
<hr />
<div>Whether you've just picked up a new LimeSDR family software defined radio and need help with installation or are looking to use the Lime Suite software bundle, the following pages will get you up and running.<br />
<br />
==For Lime Suite Users==<br />
Whether you have a LimeSDR or another software defined radio, or even if you're just experimenting with the software environment, you'll find instructions for installing the Lime Suite software stack on [[Getting Started with Lime Suite]].<br />
<br />
==For LimeSDR Users==<br />
If you've purchased a LimeSDR, LimeSDR Mini, or other device from the LimeSDR family and require assistance with installing it, see [[Getting Started with the LimeSDR]]. Note that you should install Lime Suite, as above, as a first step.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Installing_Lime_Suite_on_Linux&diff=1610
Installing Lime Suite on Linux
2018-03-27T14:05:30Z
<p>Ghalfacree: /* Building from Source */</p>
<hr />
<div>Lime Suite is a cross-platform software stack for the configuration and use of a range of software defined radio (SDR) platforms, including the LimeSDR family. The following instructions are for users of Linux-based operating systems, and primarily focus on Canonical's Ubuntu Linux distribution.<br />
<br />
==Installing via PPA==<br />
The easiest way to install Lime Suite is via Personal Package Archive (PPA), from the official Myriad-RF repository. This will ensure not only that you are installing the latest version, but that it is kept up-to-date via your operating system's package manager along with all your other software.<br />
<br />
Open a terminal session, and type the following commands to add the PPA and refresh the list of available packages:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To install Lime Suite and its dependencies, type the following command:<br />
<br />
<source lang="bash"><br />
sudo apt install limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
</source><br />
<br />
Once installed, Lime Suite and its dependencies will be automatically updated along with the rest of your software by your package manager. LimeSDR users will still need to manually update the firmware and gateware on their device when an update is made available, as described in [[LimeSDR Firmware Management]].<br />
<br />
===Uninstalling via PPA===<br />
To remove Lime Suite and its dependencies when installed via PPA, type the following commands:<br />
<br />
<source lang="bash"><br />
sudo apt remove limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
sudo add-apt-repository -y -r ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To remove Lime Suite, its dependencies, and all configuration files, substitute "purge" for "remove" in the first command.<br />
<br />
==Building from Source==<br />
For other Linux-based operating systems, Lime Suite should be built from source. Note that this is only required when installing from the official PPA, as above, is not possible; under no circumstances should a system have both a PPA-installed and self-built copy of Lime Suite installed, or errors will almost certainly follow.<br />
<br />
===Installing Dependencies===<br />
Lime Suite depends on a range of additional software and libraries to operate. The majority of these can be installed using your distribution's package manager; in some cases, however, the versions of packages provided in official distribution repositories are too old to function with the latest Lime Suite release. For distributions with PPA support, the following command:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
will add the official Myriad-RF PPA, which includes up-to-date versions of these dependencies, to your system. For distributions without PPA support, the "soapysdr" library should be built and installed from the latest source available on the project's [https://github.com/pothosware/SoapySDR GitHub repository] before attempting to build Lime Suite.<br />
<br />
To install the dependencies use the following command, excluding "libsoapysdr-dev" if you have compiled and installed "soapysdr" from source:<br />
<br />
<source lang="bash"><br />
sudo apt install libsoapysdr-dev libi2c-dev libusb-1.0-0-dev git g++ cmake libsqlite3-dev libwxgtk3.0-dev freeglut3-dev<br />
</source><br />
<br />
For distributions which do not use the apt package manager, install the listed packages with your distribution's own package manager (e.g. yum, pacman.)<br />
<br />
===Downloading the Source===<br />
To obtain the latest Lime Suite source files, clone the repository using the following command:<br />
<br />
<source lang="bash"><br />
git clone https://github.com/myriadrf/LimeSuite.git<br />
</source><br />
<br />
If you have previously cloned the repository to install an older release, change to the LimeSuite directory and update the source with the following command instead:<br />
<br />
<source lang="bash"><br />
git pull<br />
cd builddir<br />
make clean<br />
</source><br />
<br />
===Viewing the Configuration===<br />
To create a build directory for Lime Suite, type the following commands:<br />
<br />
<source lang="bash"><br />
cd LimeSuite<br />
mkdir builddir<br />
cd builddir<br />
</source><br />
<br />
To configure the build process, and to see what components are enabled and disabled, use the following command:<br />
<br />
<source lang="bash"><br />
cmake ../<br />
</source><br />
<br />
===Building and Installing Lime Suite===<br />
To begin the build process, type the following command:<br />
<br />
<source lang="bash"><br />
make -j$(nproc)<br />
</source><br />
<br />
The build process can take several minutes to complete, depending on the amount of memory and number of processor cores available on your system. When Lime Suite is built, install it by typing:<br />
<br />
<source lang="bash"><br />
sudo make install<br />
sudo ldconfig<br />
cd ../udev-rules<br />
sudo ./install.sh<br />
</source><br />
<br />
The building and installation process is now complete. You can delete the LimeSuite directory to save space, if required, or keep it to make upgrading to the next release as simple as possible.<br />
<br />
==Next Steps==<br />
If you have installed Lime Suite to use a LimeSDR device, follow the instructions in [[Getting Started with the LimeSDR]] to install, configure, and test your hardware.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Installing_Lime_Suite_on_Linux&diff=1609
Installing Lime Suite on Linux
2018-03-27T14:04:46Z
<p>Ghalfacree: Replace "apt-get" with "apt"</p>
<hr />
<div>Lime Suite is a cross-platform software stack for the configuration and use of a range of software defined radio (SDR) platforms, including the LimeSDR family. The following instructions are for users of Linux-based operating systems, and primarily focus on Canonical's Ubuntu Linux distribution.<br />
<br />
==Installing via PPA==<br />
The easiest way to install Lime Suite is via Personal Package Archive (PPA), from the official Myriad-RF repository. This will ensure not only that you are installing the latest version, but that it is kept up-to-date via your operating system's package manager along with all your other software.<br />
<br />
Open a terminal session, and type the following commands to add the PPA and refresh the list of available packages:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To install Lime Suite and its dependencies, type the following command:<br />
<br />
<source lang="bash"><br />
sudo apt install limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
</source><br />
<br />
Once installed, Lime Suite and its dependencies will be automatically updated along with the rest of your software by your package manager. LimeSDR users will still need to manually update the firmware and gateware on their device when an update is made available, as described in [[LimeSDR Firmware Management]].<br />
<br />
===Uninstalling via PPA===<br />
To remove Lime Suite and its dependencies when installed via PPA, type the following commands:<br />
<br />
<source lang="bash"><br />
sudo apt remove limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
sudo add-apt-repository -y -r ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To remove Lime Suite, its dependencies, and all configuration files, substitute "purge" for "remove" in the first command.<br />
<br />
==Building from Source==<br />
For other Linux-based operating systems, Lime Suite should be built from source. Note that this is only required when installint from the official PPA, as above, is not possible; under no circumstances should a system have both a PPA-installed and self-built copy of Lime Suite installed, or errors will almost certainly follow.<br />
<br />
===Installing Dependencies===<br />
Lime Suite depends on a range of additional software and libraries to operate. The majority of these can be installed using your distribution's package manager; in some cases, however, the versions of packages provided in official distribution repositories are too old to function with the latest Lime Suite release. For distributions with PPA support, the following command:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
will add the official Myriad-RF PPA, which includes up-to-date versions of these dependencies, to your system. For distributions without PPA support, the "soapysdr" library should be built and installed from the latest source available on the project's [https://github.com/pothosware/SoapySDR GitHub repository] before attempting to build Lime Suite.<br />
<br />
To install the dependencies use the following command, excluding "libsoapysdr-dev" if you have compiled and installed "soapysdr" from source:<br />
<br />
<source lang="bash"><br />
sudo apt install libsoapysdr-dev libi2c-dev libusb-1.0-0-dev git g++ cmake libsqlite3-dev libwxgtk3.0-dev freeglut3-dev<br />
</source><br />
<br />
For distributions which do not use the apt package manager, install the listed packages with your distribution's own package manager (e.g. yum, pacman.)<br />
<br />
===Downloading the Source===<br />
To obtain the latest Lime Suite source files, clone the repository using the following command:<br />
<br />
<source lang="bash"><br />
git clone https://github.com/myriadrf/LimeSuite.git<br />
</source><br />
<br />
If you have previously cloned the repository to install an older release, change to the LimeSuite directory and update the source with the following command instead:<br />
<br />
<source lang="bash"><br />
git pull<br />
cd builddir<br />
make clean<br />
</source><br />
<br />
===Viewing the Configuration===<br />
To create a build directory for Lime Suite, type the following commands:<br />
<br />
<source lang="bash"><br />
cd LimeSuite<br />
mkdir builddir<br />
cd builddir<br />
</source><br />
<br />
To configure the build process, and to see what components are enabled and disabled, use the following command:<br />
<br />
<source lang="bash"><br />
cmake ../<br />
</source><br />
<br />
===Building and Installing Lime Suite===<br />
To begin the build process, type the following command:<br />
<br />
<source lang="bash"><br />
make -j$(nproc)<br />
</source><br />
<br />
The build process can take several minutes to complete, depending on the amount of memory and number of processor cores available on your system. When Lime Suite is built, install it by typing:<br />
<br />
<source lang="bash"><br />
sudo make install<br />
sudo ldconfig<br />
cd ../udev-rules<br />
sudo ./install.sh<br />
</source><br />
<br />
The building and installation process is now complete. You can delete the LimeSuite directory to save space, if required, or keep it to make upgrading to the next release as simple as possible.<br />
<br />
==Next Steps==<br />
If you have installed Lime Suite to use a LimeSDR device, follow the instructions in [[Getting Started with the LimeSDR]] to install, configure, and test your hardware.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Firmware_Management&diff=1607
LimeSDR Firmware Management
2018-03-21T16:08:49Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>As well as software running on the host PC, the LimeSDR family of software-defined radios has two user-upgradeable pieces of 'soft' ware running directly on its board: these are the firmware and the gateware, the latter defining how the on-board field programmable gate array (FPGA) should operate.<br />
<br />
It is important that the firmware and gateware be kept up-to-date, especially when installing a new LimeSDR or upgrading Lime Suite on a system with an existing LimeSDR. Using a LimeSDR with a firmware or gateware version that does not match the version expected by Lime Suite or other controlling software can cause errors or other issues with both transmission and reception, and can in some cases result in the LimeSDR failing to operate at all until its firmware and gateware are both updated.<br />
<br />
==Updating the Firmware and Gateware==<br />
The firmware and gateware files for all supported LimeSDR boards are supplied with the Lime Suite software stack. If you have not yet installed Lime Suite, do so by following the guide at [[Getting Started with Lime Suite]].<br />
<br />
The firmware and gateware revisions should match the revisions shipped with Lime Suite; if they do not, Lime Suite will display an error about a version mismatch. Note that this mismatch can occur with firmware and gateware that is older than the version of Lime Suite you are using and that is newer, the latter potentially causing issues if you - for whatever reason - wish to use an older release of Lime Suite with a LimeSDR that has already been updated on a newer Lime Suite installation. In these cases, the term "updating" refers to replacing the existing firmware and gateware on the board with the version supplied with Lime Suite; this can be a newer or older version than is already on the board.<br />
<br />
With LimeSuite installed, open your operating system's command line interface - the Terminal in Linux and macOS and Command Prompt or PowerShell in Windows - and, with the LimeSDR connected to your host PC, run the following command:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
Note the capital letters in "LimeUtil"; these are required in case-sensitive operating systems.<br />
<br />
The update process will take a few minutes to complete, during which time progress information will be printed to the terminal. It is important that the process is allowed to fully complete; during the update process do not close your command line interface window, shut down or suspend your computer, or disconnect any cables connected to the LimeSDR.<br />
<br />
Once the process is complete, the LimeSDR will automatically reboot to load the new firmware and gateware. If you are still receiving an error about version mismatches in Lime Suite at this point, disconnect and reconnect the LimeSDR in order to force a refresh.<br />
<br />
==Obtaining the Latest Firmware and Gateware==<br />
The latest firmware and gateware versions are shipped as standard with each new Lime Suite release. Using firmware and gateware images which are not distributed with Lime Suite - for example, by manually downloading the individual files from the GitHub repository - is not advised, as using a newer release of firmware and gateware with an older version of Lime Suite can cause as many problems as using a newer version of Lime Suite with older firmware and gateware.<br />
<br />
To upgrade your version of Lime Suite and obtain the latest firmware and gateware files, use your operating system's package manager (where available) or download and install the latest version over the top of your existing version using the instructions on the page [[Getting Started with Lime Suite]].<br />
<br />
==Recovering from a Bad Update==<br />
If the firmware and gateware update process is interrupted, restart it by typing:<br />
<br />
<source lang="bash"><br />
LimeUtil --update<br />
</source><br />
<br />
If using a LimeSDR USB, an interruption in the firmware and gateware update process can result in the FX3 chip, responsible for USB communications, entering 'bootloader' mode; this is not the case for the LimeSDR Mini, which uses a different USB controller. In this mode, the chip will not communicate with the rest of the LimeSDR USB board. To fix this first download the [https://github.com/myriadrf/LimeSDR-USB_FX3/blob/master/Debug/LimeSDR-USB_fx3_fw.img latest LimeSDR USB FX3 firmware image]. Next, load Lime Suite GUI and use the following steps to flash the firmware:<br />
<br />
# Connect the LimeSDR USB board, if disconnected.<br />
# In Lime Suite GUI, click "Options," then "Connection Settings," then finally "Connect".<br />
# Click "Modules" then "Programming."<br />
# Select "FX3" in the "Device" list, then choose "Firmware to RAM" in the "Programming Mode" list.<br />
# Browse to the firmware file you downloaded, making sure to pick the correct file.<br />
# Click "Program" and allow the flashing process to complete. The LimeSDR USB will restart.<br />
# Return to the "Options" menu, click "Connection Settings, then click "Connect" to re-connect to your LimeSDR USB.<br />
# Click "Modules" then "Programming."<br />
# Select "Automatic" in the "Device" list and "Automatic Update" in the "Programming Mode" list.<br />
# Click "Program" to update the firmware and gateware.<br />
<br />
Your LimeSDR USB will now have the correct firmware and gateware files installed.<br />
<br />
==Next Steps==<br />
If you are following these steps in order to set up your new LimeSDR device, continue on to [[Testing the LimeSDR]].<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Windows_Driver_Installation&diff=1606
LimeSDR Windows Driver Installation
2018-03-21T16:06:59Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>The LimeSDR family of software defined radio boards requires drivers to be installed before it can be used on platforms running the Microsoft Windows family of operating systems. Follow these instructions to download and install the driver before trying to use the LimeSDR for the first time.<br />
<br />
Those using LimeSDR hardware on Linux or macOS can skip this step and move on to [[LimeSDR Firmware Management]] to upgrade the LimeSDR's firmware and gateware.<br />
<br />
==Downloading and Extracting the Driver==<br />
Download the latest version of the LimeSDR from the Myriad-RF GitHub repository using [https://github.com/myriadrf/Windows-drivers/archive/master.zip this link]. The name of the archive will be Windows-drivers-master.zip. Extract the archive using Windows' built-in archive management or the archive tool of your choice.<br />
<br />
==Loading Device Manager==<br />
Connect your LimeSDR to your host PC, if you have not already done so. Wait a few seconds for Windows to detect the device, then click on the Start Menu or press the Super key on your keyboard and type "Device Manager" followed by the Enter Key.<br />
<br />
In the list of device categories in the Device Manager window, expand "Other devices" and find "LimeSDR-USB" or "LimeSDR Mini" in the list. Right-click on this device then left-click on "Update Driver Software" to load the driver installation dialogue.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Update_Software.png|thumb|center|600px|]]<br />
<br />
==Manually Installing the Driver==<br />
To ensure that Windows loads the correct driver, choose "Browse my computer for driver software" from the window that appears. Click the "Browse" button, then browse to the folder to which you extracted the driver archive followed by the sub-folder which matches your Windows version:<br />
<br />
* wxp - Windows XP<br />
* vista - Windows Vista<br />
* Win7 - Windows 7<br />
* Win8 - Windows 8<br />
* Win81 - Windows 8.1<br />
* Win10 - Windows 10<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Select.png|thumb|center|600px|]]<br />
<br />
Click "OK", then click "Next" to begin driver installation. After a few seconds, Windows will display a dialogue confirming that the driver has been installed.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Succesfull_Inst.png|thumb|center|600px|]]<br />
<br />
==Confirming Driver Installation==<br />
To confirm that the driver has been successfully loaded, click "Close" to return to the main Device Manager window. Expand the device category labelled "Universal Serial Bus controllers" and find "Myriad-RF LimeSDR-USB" or "Myriad-RF LimeSDR Mini" in the list; its logo should be a USB connector with no exclamation mark or other warning symbol present.<br />
<br />
[[File:LimeSDR-USB_1v4_Drivers_Device_Man_Succ.png|thumb|center|600px|]]<br />
<br />
If the device does not appear, disconnect the LimeSDR from your system and reconnect it to refresh Device Manager. If using the LimeSDR USB, make sure that both the power and data USB connectors are plugged into your host PC, as inadequate power can cause the LimeSDR USB to fail to operate correctly.<br />
<br />
==Next Steps==<br />
With the driver installed, you can move on to [[LimeSDR Firmware Management]] to learn how to update the firmware and gateware on your LimeSDR.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Hardware_Installation&diff=1605
LimeSDR Hardware Installation
2018-03-21T16:06:13Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>The LimeSDR family of software defined radios are designed to make it as easy as possible to get started in the world of SDR. Before you can begin, though, you'll need to run through some simple steps in order to get your LimeSDR installed and configured correctly.<br />
<br />
==Unpacking==<br />
The LimeSDR family includes the LimeSDR USB and LimeSDR Mini software defined radio devices. Both of these are similar in operation, differing only in their size and base capabilities.<br />
<br />
Begin by removing your LimeSDR from its packaging. Note the anti-static bag, used to protect the LimeSDR during transit. The LimeSDR is a sensitive electronic device, and should be handled with appropriate precautions against electrostatic discharge (ESD); be sure to ground yourself, for example by tapping your finger on the exposed metal of a radiator pipe, before removing it from the anti-static bag, and ensure you hold the board by its edges. Also be careful of components, such as the small male pin headers, which protrude above the surface of the LimeSDR board; these can catch on the edge of the bag.<br />
<br />
==Connecting Antennas==<br />
The LimeSDR family of SDR boards have multiple RF ports, to which antennas appropriate to the frequencies in which you will be operating must be connected. Some hardware bundles include antennas; others come without. The port you use depends on whether you will be receiving or transmitting and at what frequency. The following sections describe the ports and their capabilities.<br />
<br />
When configuring your software, be sure to select the ports to which you have connected antennas; the LimeSDR does not automatically sense if an antenna is connected to a port or not.<br />
<br />
===LimeSDR USB RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
The LimeSDR USB has U.FL connectors for its RF ports. These can be used with U.FL to SMA 'pigtail' cables to allow for connection to external antennas. Take care when connecting the U.FL end of the pigtail to avoid damage to either connector, and be sure that there is no strain on the cable when the SMA connector is linked to its antenna.<br />
<br />
Note that, in all cases, optimal receive performance is obtained by using the *_H and *_L ports within the frequency bands listed. Secondary transmit ports for each channel, where available, can be used with power amplifiers covering different bands or for loopback and other tasks.<br />
<br />
===LimeSDR USB RF Ports===<br />
{| class="wikitable"<br />
|+LimeSDR Mini RF Ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX<br />
|Channel 1 RX - all frequencies<br />
|-<br />
|TX<br />
|Channel 1 TX - all frequencies<br />
|}<br />
<br />
The LimeSDR Mini has SMA connectors for its ports, requiring no additional conversion for connection to external antennas. Depending on desired positioning, however, SMA extension cables will give you increased flexibility in positioning and alignment.<br />
<br />
==Case Assembly==<br />
If you have purchased the official LimeSDR Acrylic Case for the LimeSDR USB, see [https://github.com/myriadrf/LimeSDR-USB_acrylic_case#assembly the assembly instructions on GitHub]. If you have purchased a third-party case, consult the documentation from your case manufacturer for instructions.<br />
<br />
If you do not have a case for your LimeSDR, it can be used without one providing you are careful to ensure that it does not come into contact with electrically conductive surfaces - including metal desk coverings - while in use, or the board may suffer a damaging electrical short.<br />
<br />
==Connecting to a PC==<br />
The LimeSDR USB and LimeSDR Mini both connect to a host computer over a USB 3.0 interface, although both are backwards compatible with older USB 2.0 ports at a reduced rate of operation. The LimeSDR Mini includes a male USB plug in its design; simply insert this directly into a free USB 3.0 Type A port on your host computer or via a good-quality USB 3.0 extension lead for more flexible positioning.<br />
<br />
The LimeSDR USB comes with a USB 3.0 splitter cable. While the LimeSDR USB draws its power entirely via USB, negating the need for an external power supply, it can require more power than a single uSB port can provide. The splitter cable is wired so that the USB plug with a blue inner, in the middle of the cable, has both power and data connections while the USB plug with a white inner, at the far end of the cable, has only power connections.<br />
<br />
Begin by connecting the white, power, USB plug to a free USB 2.0 or 3.0 port on your host computer, then connect the blue, power and data, USB plug to a free USB 3.0 port. The final end of the cable, which is terminated in a USB 3.0 SuperSpeed connector, should finally be inserted into the matching connector on the LimeSDR USB. Note that there is no power switch on the LimeSDR USB; as soon as the cable is connected, the board will become live. Disconnecting the LimeSDR USB should be performed in the opposite order, starting with the USB 3.0 SuperSpeed connector on the LimeSDR USB itself.<br />
<br />
If using the LimeSDR USB with a laptop or all-in-one system, the splitter cable may not reach between USB sockets. If so, attach a good-quality USB extension cable - not supplied - to the white, power-only, connector of the splitter to extend its reach.<br />
<br />
==Next Steps==<br />
Windows users will now need to install the LimeSDR driver, following the instructions on the [[Windows Driver Installation]] page. All other users should move on to [[LimeSDR Firmware Management]] to update their firmware and gateware to the latest releases, without which the LimeSDR may not operate as expected.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Getting_Started_with_the_LimeSDR&diff=1604
Getting Started with the LimeSDR
2018-03-21T16:05:22Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>The LimeSDR family of software defined radios are designed to make it as easy as possible to get started in the world of SDR. Before you can begin, though, you'll need to run through some simple steps in order to get your LimeSDR installed and configured correctly.<br />
<br />
==Installing Lime Suite==<br />
Before installing your LimeSDR, make sure you have the latest drivers and software stack installed by following the instructions on [[Getting Started with Lime Suite]]. This installation should take place before you attempt to connect the LimeSDR to your PC, and Lime Suite will be required for testing the LimeSDR once installed.<br />
<br />
==Unpacking and Connecting the Hardware==<br />
Full instructions on unpacking the LimeSDR USB and LimeSDR Mini, connecting antennas, and connecting them to a host PC can be found on [[LimeSDR Hardware Installation]].<br />
<br />
==Installing the Windows Driver==<br />
If you are using your LimeSDR with Microsoft's Windows platform, follow the instructions on [[LimeSDR Windows Driver Installation]]. Users of Linux or macOS operating systems can skip this step.<br />
<br />
==Updating the Firmware and Gateware==<br />
The code running on the LimeSDR itself - known as "firmware" and "gateware" - needs to be kept up-to-date. Read [[LimeSDR Firmware Management]] to find out how to update these, and how to recover them if anything ever goes wrong.<br />
<br />
==Testing the LimeSDR==<br />
To confirm that your LimeSDR is properly installed and operational, follow the instructions on [[Testing the LimeSDR]]. Once the test is complete, your new LimeSDR is ready to use.<br />
<br />
==Further Reading==<br />
For inspiration, and for more details on the LimeSDR and how it works, take a look at [https://myriadrf.org/blog/limesdr-made-simple-part-1/ Karl Woodward's LimeSDR Made Simple series] on the [https://myriadrf.org/blog/ Myriad-RF blog].<br />
<br />
For technical details on the LimeSDR family, see the [https://wiki.myriadrf.org/LimeSDR LimeSDR wiki page].<br />
<br />
For community support and discussion, visit the [https://discourse.myriadrf.org/ Myriad-RF forum].<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Installing_Lime_Suite_on_Windows&diff=1603
Installing Lime Suite on Windows
2018-03-21T16:03:49Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>Lime Suite is a cross-platform software stack for the configuration and use of a range of software defined radio (SDR) platforms, including the LimeSDR family. The following instructions are for users of Microsoft's Windows operating system.<br />
<br />
==Installing via Binaries==<br />
A precompiled version of Lime Suite, ready to use, is provided as part of the [https://github.com/pothosware/PothosSDR/wiki Pothos SDR development environment bundle], along with a range of other useful software defined radio utilities. This is the recommended way to install Lime Suite on Windows.<br />
<br />
Begin by downloading the latest build from the [http://downloads.myriadrf.org/builds/PothosSDR/?C=M;O=D Myriad-RF website]; this will be the entry at the very top of the list, which is sorted by date. Once downloaded, double-click on the installation file, confirm that you wish to open it, and follow the installation wizard's instructions to install the bundle on your system.<br />
<br />
Once installation is complete, Lime Suite will be available on the Start Menu under "Pothos SDR environment", labelled as "LMS7 Suite."<br />
<br />
===Uninstalling via Binaries===<br />
To uninstall Lime Suite when installed through the Pothos SDR development environment bundle, use Windows's Add/Remove Programs or Apps & Features utility depending on your version of Windows. Note that this will also uninstall the other tools included in the Pothos SDR development environment bundle.<br />
<br />
==Building from Source==<br />
Where a newer version of Lime Suite is required than is provided in the Pothos SDR development environment bundle, Lime Suite can be built from the latest source files.<br />
<br />
===Installing Dependencies===<br />
Compiling Lime Suite on Windows requires the installation of the following dependencies:<br />
<br />
* [https://www.visualstudio.com/downloads/ A recent Visual Studio release]<br />
* [https://gitforwindows.org/ Git for Windows]<br />
* [https://cmake.org/download/ CMake]<br />
* [https://www.wxwidgets.org/downloads/ wxWidgets]<br />
* [http://www.cypress.com/documentation/software-and-drivers/ez-usb-fx3-software-development-kit Cypress' EZ-USB FX3 USB Suite] (cy\_ssusbsuite\_v1.3.3.zip)<br />
* [http://downloads.myriadrf.org/builds/PothosSDR/?C=M;O=D SoapySDR via the Pothos SDR bundle]<br />
<br />
Make sure that all these dependencies are installed and functioning before attempting the build process.<br />
<br />
===Downloading the Source===<br />
To obtain the latest Lime Suite source files, clone the repository using the following in a Command Prompt window:<br />
<br />
<source><br />
git clone https://github.com/myriadrf/LimeSuite.git<br />
</source><br />
<br />
If you have previously cloned the repository to install an older release, change to the LimeSuite directory and update the source with the following command instead:<br />
<br />
<source><br />
git pull<br />
</source><br />
<br />
===Building and Installing Lime Suite===<br />
To create a build directory for Lime Suite, type the following commands:<br />
<br />
<source><br />
cd LimeSuite<br />
mkdir builddir<br />
cd builddir<br />
</source><br />
<br />
To configure the build process use the following command:<br />
<br />
<source><br />
cmake ../ -G "Visual Studio 14 2015 Win64" ^<br />
-DWX_ROOT_DIR=C:/wxWidgets-3.1.0 ^<br />
-DwxWidgets_ROOT_DIR=C:/wxWidgets-3.1.0 ^<br />
-DwxWidgets_LIB_DIR=C:/wxWidgets-3.1.0/lib/vc140_x64_lib ^<br />
-DFX3_SDK_PATH="C:/EZ-USB FX3 SDK/1.3" ^<br />
-DSoapySDR_DIR=C:/PothosSDR<br />
</source><br />
<br />
Note that the paths to the dependencies may differ depending on how they were installed.<br />
<br />
To begin the build process and install Lime Suite, use the following two commands:<br />
<br />
<source><br />
cmake --build . --config Release<br />
cmake --build . --config Release --target install<br />
</source><br />
<br />
This will install Lime Suite into the folder specified in the CMAKE\_INSTALL\_PREFIX variable. The build process can take several minutes to complete, depending on the amount of memory and number of processor cores available on your system.<br />
<br />
==Next Steps==<br />
If you have installed Lime Suite to use a LimeSDR device, follow the instructions in [[Getting Started with the LimeSDR]] to install, configure, and test your hardware.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Installing_Lime_Suite_on_macOS&diff=1602
Installing Lime Suite on macOS
2018-03-21T16:02:37Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>Lime Suite is a cross-platform software stack for the configuration and use of a range of software defined radio (SDR) platforms, including the LimeSDR family. The following instructions are for users of Apple's macOS operating system, and use the [https://github.com/pothosware/homebrew-pothos/wiki Pothos Homebrew tap].<br />
<br />
==Installing via Homebrew==<br />
The easiest way to install Lime Suite is via the [https://brew.sh/ Homebrew package management system]. Begin by installing the Apple Xcode Command Line Tools by opening a terminal and typing the following command:<br />
<br />
<source lang="bash"><br />
xcode-select --install<br />
</source><br />
<br />
Click "Install" in the dialogue that appears, then wait while the Xcode tools are downloaded and installed. When the process has completed, install Homebrew with the following command:<br />
<br />
<source lang="bash"><br />
/usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)"<br />
</source><br />
<br />
Finally, install Lime Suite by typing the following two commands:<br />
<br />
<source lang="bash"><br />
brew update<br />
brew install limesuite<br />
</source><br />
<br />
===Uninstalling via Homebrew===<br />
To remove Lime Suite and its dependencies when installed via Homebrew, type the following command:<br />
<br />
<source lang="bash"><br />
brew uninstall limesuite<br />
</source><br />
<br />
==Next Steps==<br />
If you have installed Lime Suite to use a LimeSDR device, follow the instructions in [[Getting Started with the LimeSDR]] to install, configure, and test your hardware.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Installing_Lime_Suite_on_Linux&diff=1601
Installing Lime Suite on Linux
2018-03-21T16:01:41Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>Lime Suite is a cross-platform software stack for the configuration and use of a range of software defined radio (SDR) platforms, including the LimeSDR family. The following instructions are for users of Linux-based operating systems, and primarily focus on Canonical's Ubuntu Linux distribution.<br />
<br />
==Installing via PPA==<br />
The easiest way to install Lime Suite is via Personal Package Archive (PPA), from the official Myriad-RF repository. This will ensure not only that you are installing the latest version, but that it is kept up-to-date via your operating system's package manager along with all your other software.<br />
<br />
Open a terminal session, and type the following commands to add the PPA and refresh the list of available packages:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To install Lime Suite and its dependencies, type the following command:<br />
<br />
<source lang="bash"><br />
sudo apt-get install limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
</source><br />
<br />
Once installed, Lime Suite and its dependencies will be automatically updated along with the rest of your software by your package manager. LimeSDR users will still need to manually update the firmware and gateware on their device when an update is made available, as described in [[LimeSDR Firmware Management]].<br />
<br />
===Uninstalling via PPA===<br />
To remove Lime Suite and its dependencies when installed via PPA, type the following commands:<br />
<br />
<source lang="bash"><br />
sudo apt-get remove limesuite liblimesuite-dev limesuite-udev limesuite-images soapysdr soapysdr-module-lms7<br />
sudo add-apt-repository -y -r ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
To remove Lime Suite, its dependencies, and all configuration files, substitute "purge" for "remove" in the first command.<br />
<br />
==Building from Source==<br />
For other Linux-based operating systems, Lime Suite should be built from source. Note that this is only required when installint from the official PPA, as above, is not possible; under no circumstances should a system have both a PPA-installed and self-built copy of Lime Suite installed, or errors will almost certainly follow.<br />
<br />
===Installing Dependencies===<br />
Lime Suite depends on a range of additional software and libraries to operate. The majority of these can be installed using your distribution's package manager; in some cases, however, the versions of packages provided in official distribution repositories are too old to function with the latest Lime Suite release. For distributions with PPA support, the following command:<br />
<br />
<source lang="bash"><br />
sudo add-apt-repository -y ppa:myriadrf/drivers<br />
sudo apt update<br />
</source><br />
<br />
will add the official Myriad-RF PPA, which includes up-to-date versions of these dependencies, to your system. For distributions without PPA support, the "soapysdr" library should be built and installed from the latest source available on the project's [https://github.com/pothosware/SoapySDR GitHub repository] before attempting to build Lime Suite.<br />
<br />
To install the dependencies use the following command, excluding "libsoapysdr-dev" if you have compiled and installed "soapysdr" from source:<br />
<br />
<source lang="bash"><br />
sudo apt install libsoapysdr-dev libi2c-dev libusb-1.0-0-dev git g++ cmake libsqlite3-dev libwxgtk3.0-dev freeglut3-dev<br />
</source><br />
<br />
For distributions which do not use the apt package manager, install the listed packages with your distribution's own package manager (e.g. yum, pacman.)<br />
<br />
===Downloading the Source===<br />
To obtain the latest Lime Suite source files, clone the repository using the following command:<br />
<br />
<source lang="bash"><br />
git clone https://github.com/myriadrf/LimeSuite.git<br />
</source><br />
<br />
If you have previously cloned the repository to install an older release, change to the LimeSuite directory and update the source with the following command instead:<br />
<br />
<source lang="bash"><br />
git pull<br />
cd builddir<br />
make clean<br />
</source><br />
<br />
===Viewing the Configuration===<br />
To create a build directory for Lime Suite, type the following commands:<br />
<br />
<source lang="bash"><br />
cd LimeSuite<br />
mkdir builddir<br />
cd builddir<br />
</source><br />
<br />
To configure the build process, and to see what components are enabled and disabled, use the following command:<br />
<br />
<source lang="bash"><br />
cmake ../<br />
</source><br />
<br />
===Building and Installing Lime Suite===<br />
To begin the build process, type the following command:<br />
<br />
<source lang="bash"><br />
make -j$(nproc)<br />
</source><br />
<br />
The build process can take several minutes to complete, depending on the amount of memory and number of processor cores available on your system. When Lime Suite is built, install it by typing:<br />
<br />
<source lang="bash"><br />
sudo make install<br />
sudo ldconfig<br />
cd ../udev-rules<br />
sudo ./install.sh<br />
</source><br />
<br />
The building and installation process is now complete. You can delete the LimeSuite directory to save space, if required, or keep it to make upgrading to the next release as simple as possible.<br />
<br />
==Next Steps==<br />
If you have installed Lime Suite to use a LimeSDR device, follow the instructions in [[Getting Started with the LimeSDR]] to install, configure, and test your hardware.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Getting_Started_with_Lime_Suite&diff=1600
Getting Started with Lime Suite
2018-03-21T15:59:33Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>Lime Suite is the name given to a collection of software supporting several hardware platforms including the LimeSDR, drivers for the LMS7002M transceiver RFIC, and other tools for developing with LMS7-based hardware. Installing the Lime Suite enables many SDR applications such as GQRX to work with supported hardware through the bundled SoapySDR support module, and should be the first step for anyone who has purchased a new LimeSDR device.<br />
<br />
==Lime Suite Components==<br />
The Lime Suite software stack is split into four main sections:<br />
<br />
* LMS7 Drivers<br />
** High-level API calls<br />
** C and C++ API<br />
** Self-calibration<br />
* Board Support<br />
** LimeSDR, EVB7<br />
** Novena + LMS7<br />
** Extensible API<br />
* Lime Suite GUI<br />
** Debug registers<br />
** Live Fast Fourier Transform (FFT) plotting<br />
** Firmware and gateware updates<br />
* SDR Interfaces<br />
** Stream and control API<br />
** SoapySDR support<br />
** SDR application ecosystem<br />
<br />
==Installing Lime Suite==<br />
Lime Suite is a cross-platform bundle, available for Linux, macOS, and Windows.<br />
<br />
===Installing on Linux===<br />
Lime Suite is available for Linux via PPA or source, with full instructions on the [[Installing Lime Suite on Linux]] page.<br />
<br />
===Installing on macOS===<br />
Lime Suite is available for macOS via the Homebrew package manager, with full instructions on the [[Installing Lime Suite on macOS]] page.<br />
<br />
===Installing on Windows===<br />
Lime Suite is available for Windows via precompiled binary or source, with full instructions on the [[Installing Lime Suite on Windows]] page.<br />
<br />
==Further Reading==<br />
More information on Lime Suite is available on the [https://myriadrf.org/projects/lime-suite/ project page], while the latest source code is always available on the [https://github.com/myriadrf/LimeSuite Myriad-RF GitHub repository].<br />
<br />
For community support and discussion, visit the [https://discourse.myriadrf.org/ Myriad-RF forum].<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=Getting_Started_with_Myriad-RF&diff=1599
Getting Started with Myriad-RF
2018-03-21T15:56:46Z
<p>Ghalfacree: Initial Page Creation</p>
<hr />
<div>Whether you've just picked up a new LimeSDR family software defined radio and need help with installation or are looking to use the Lime Suite software bundle, the following pages will get you up and running.<br />
<br />
==For Lime Suite Users==<br />
Whether you have a LimeSDR or another software defined radio, or even if you're just experimenting with the software environment, you'll find instructions for installing the Lime Suite software stack on [[Getting Started with Lime Suite]].<br />
<br />
==For LimeSDR Users==<br />
If you've purchased a LimeSDR, LimeSDR Mini, or other device from the LimeSDR family and require assistance with installing it, see [[Getting Started with LimeSDR]]. Note that you should install Lime Suite, as above, as a first step.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR-USB_Quick_Test&diff=1459
LimeSDR-USB Quick Test
2018-02-21T14:38:29Z
<p>Ghalfacree: Changed 'Packets MIMO' to 'LMS MIMO' to match latest Lime Suite GUI.</p>
<hr />
<div>== Introduction ==<br />
<br />
The [[Lime Suite]] GUI is a powerful tool for configuring and debugging hardware platforms that are based around the [[LimeMicro:LMS7002M_Datasheet|LMS7002M transceiver chip]]. It allows you to view, edit, save and load the state of LMS7002M registers, perform board microcontroller firmware and FPGA gateware updates, and view FFT plots and configure various other on-board modules. <br />
<br />
This guide shows how Lime Suite GUI can be used to configure the LMS7002M on a [[LimeSDR|LimeSDR-USB]] and:<br />
<br />
* generate a WCDMA signal and then display this via RF loopback;<br />
* display a received signal via the FFTviewer module;<br />
* transmit a test signal which can be observed on a spectrum analyser. <br />
<br />
<br />
Thereby confirming operation of the board — with appropriate firmware and gateware loaded — O/S drivers and Lime Suite.<br />
<br />
''Please note that this does not confirm the availability and correct operation of APIs exposed by components sitting above Lime Suite in the software stack, such as SoapySDR, UHD and gr-osmosdr etc. These must be tested separately''.<br />
<br />
== Download test files ==<br />
<br />
First you need to download two transceiver configuration files and example waveforms.<br />
<br />
* LMS7002M configs:<br />
** [https://raw.githubusercontent.com/myriadrf/LimeSDR-USB/master/test/limesuite/self_test.ini self_test.ini]<br />
** [https://raw.githubusercontent.com/myriadrf/LimeSDR-USB/master/test/limesuite/example.ini example.ini]<br />
* [http://downloads.myriadrf.org/waveforms/wfm/lms7suite_wfm.tgz waveform files]<br />
<br />
<br />
Note that the waveform files should be extracted to a directory called '''lms7suite_wfm'''.<br />
<br />
== Loopback test ==<br />
<br />
In this test:<br />
<br />
* A waveform is sent from the host computer to the LimeSDR-USB board<br />
* WCDMA signal is generated in the FPGA<br />
* An on-board RF switch connects TX to RX<br />
* The received signal is displayed by the FFT viewer<br />
<br />
=== Connect to board ===<br />
<br />
1. Launch Lime Suite GUI (LimeSuiteGUI.exe on Windows or just ‘LimeSuiteGUI’ on Linux)<br />
<br />
2. From menu bar select: ‘Options->ConnectionSettings’<br />
<br />
[[File:LimeSDR-USB_Quick_Test_Fig1.png]]<br />
<br />
3. Select the device and click the “Connect” button<br />
<br />
[[File:LimeSDR-USB Quick Test Fig2.png]]<br />
<br />
=== Load the configuration file ===<br />
<br />
1. In LimeSuite GUI click the ‘Open’ button<br />
<br />
[[File:LimeSDR-USB Quick Test Fig3.png]]<br />
<br />
2. Navigate and select self test INI file ‘self_test.ini’<br />
<br />
3. Lime Suite GUI should be updated with values loaded from INI file.<br />
<br />
4. Select GUI->Chip<br />
<br />
=== Configure SXT ===<br />
<br />
1. Go to the “SXT” tab.<br />
<br />
2. Press the ‘Calculate’ button. <br />
<br />
3. Press the ‘Tune’ button.<br />
<br />
=== Configure CLKGEN ===<br />
<br />
1. Go to the “CLKGEN” tab.<br />
<br />
2. Press the ‘Calculate’ button. <br />
<br />
3. Press the ‘Tune’ button.<br />
<br />
=== Enable RF loopback ===<br />
<br />
1. From the menu bar select: ‘Modules->Board controls’<br />
<br />
2. Tick RF loopback Ch.A and RF loopback Ch.B<br />
<br />
[[File:LimeSDR-USB_BoardControls.jpg]]<br />
<br />
=== Load WCDMA waveform ===<br />
<br />
1. From the menu bar select: ‘Modules->FPGA controls’.<br />
<br />
2. Tick ‘MIMO ‘.<br />
<br />
3. Click ‘W-CMDA ‘.<br />
<br />
[[File:LimeSDR-USB FPGAControls.jpg]]<br />
<br />
=== Viewing the signal using FFT viewer ===<br />
<br />
1. From the menu bar select: ‘Modules->FFTviewer’.<br />
<br />
2. Select ’Data reading’ -> ’LMS MIMO’.<br />
<br />
3. Select ’Graphs'->’Display channel’->’A&B’.<br />
<br />
4. Click “Start” button to start receiving samples.<br />
<br />
[[File:LimeSDR-USB SelfTest FFT.jpg]]<br />
<br />
== Receiving a signal ==<br />
<br />
=== Connect to board ===<br />
<br />
1. Launch the Lime Suite GUI as before.<br />
<br />
2. From menu bar select: ‘Options->ConnectionSettings’<br />
<br />
3. Select the device and click the “Connect” button<br />
<br />
=== Load the configuration file ===<br />
<br />
1. In LimeSuite GUI click the ‘Open’ button.<br />
<br />
2. Navigate and select example INI file ‘example.ini’<br />
<br />
3. Lime Suite GUI should be updated with values loaded from INI file.<br />
<br />
=== Change the carrier frequency ===<br />
<br />
In ‘example.ini’ the receiver frequency is set to 800 MHz. To change the receiver frequency:<br />
<br />
1. Go to the “SXR” tab in Lime Suite GUI<br />
<br />
2. Enter desired RX frequency in the field labelled “Frequency, MHz”. <br />
<br />
3. Press the ‘Calculate’ button. <br />
<br />
[[File:LimeSDR-USB_Quick_Test_Fig4.png]]<br />
<br />
NOTE: The minimum allowed frequency is 30 MHz.<br />
<br />
=== Change the sampling rate ===<br />
<br />
The sampling rate set in the ‘example.ini’ configuration file is 10 MHz.<br />
<br />
The simplest way to change the sampling rate without changing any dividers:<br />
<br />
1. Go to the “CLKGEN” tab.<br />
<br />
2. Adjust the “CLK_H (MHz)” value so that it is 8 times the desired sample rate. E.g. 80 MHz CLK_H will result in 10 MHz sample rate (10 MHz RF bandwidth).<br />
<br />
3. Click the “Calculate” button.<br />
<br />
[[File:LimeSDR-USB Quick Test Fig5.png ]]<br />
<br />
=== Viewing the signal using FFT viewer ===<br />
<br />
Once the receiver frequency and sampling rate is configured, the RF signal can be observed using FFT viewer. In the ‘example.ini’ file the receiver is configured to use ‘RX1_L’ input and so the antenna should be connected to this port.<br />
<br />
1. From the menu bar select: ‘Modules->FFTviewer’<br />
<br />
[[File:LimeSDR-USB_Quick_Test_Fig6.png]]<br />
<br />
2. Click “Start” button to start receiving samples<br />
<br />
[[File:LimeSDR-USB Quick Test Fig7.png]]<br />
<br />
=== Receiving test signal ===<br />
<br />
To enable test signal RX go to “RxTSP” tab and set input source to “Test signal”.<br />
<br />
[[File:LimeSDR-USB Quick Test Fig8.png]]<br />
<br />
You can try playing around with test signal by changing TSGFCW, TSGMODE, TSGFC, CMIX values.<br />
<br />
=== Changing RX gain ===<br />
<br />
Rx gains can be adjusted in the “RFE” tab by changing ‘LNA’ and the ‘TIA’ values (Figure 9), and in the “RBB” tab by changing ‘PGA gain’ value.<br />
<br />
[[File:LimeSDR-USB Quick Test Fig9.png]]<br />
<br />
[[File:LimeSDR-USB_Quick_Test_Fig10.png]]<br />
<br />
== Transmitting a signal ==<br />
<br />
=== Connect to the board ===<br />
<br />
1. Launch the Lime Suite GUI as before.<br />
<br />
2. From the menu bar select: ‘Options→ConnectionSettings’<br />
<br />
3. Select the device to connect to and click the “Connect” button.<br />
<br />
=== Load the configuration file ===<br />
<br />
1. In Lime Suite GUI click the ‘Open’ button.<br />
<br />
2. Navigate and select the example INI file ‘example.ini’<br />
<br />
3. Lime Suite GUI should be updated with values loaded from the INI file.<br />
<br />
=== Change the carrier frequency ===<br />
<br />
In ‘example.ini’ the transmitter frequency is set to 850 MHz. To change the transmitter frequency:<br />
<br />
1. Go to the “SXT” tab in Lime Suite GUI<br />
<br />
2. Enter the desired TX frequency in the field labelled “Frequency, MHz”. Note that the minimum allowed frequency is 30 MHz.<br />
<br />
3. Press the ‘Calculate’ button. <br />
<br />
[[File:LimeSDR-USB Quick Test Fig11.png]]<br />
<br />
4. A spectrum analyser can be used to view the TX carrier signal<br />
<br />
[[File:LimeSDR-USB_Quick_Test_Fig12.png]]<br />
<br />
=== Transmitting test signal ===<br />
<br />
To enable TX test signal go to the “TxTSP” tab and set the input source to “Test signal”.<br />
<br />
[[File:LimeSDR-USB_Quick_Test_Fig13.png]]<br />
<br />
A spectrum analyzer can be used to view the TX test signal.<br />
<br />
[[File:LimeSDR-USB_Quick_Test_Fig14.png]]<br />
<br />
=== Changing TX gain ===<br />
<br />
Tx gain can be adjusted in the “TBB” tab by changing the ‘Frontend gain’ value.<br />
<br />
[[File:LimeSDR-USB Quick Test Fig15.png]]<br />
<br />
==Document Version ==<br />
<br />
Based on LimeSDR-USB Quick Test v1.1 document.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeSDR_Quick_Start&diff=1458
LimeSDR Quick Start
2018-02-21T13:50:45Z
<p>Ghalfacree: Update for physical cabling, firmware update, and other additional details.</p>
<hr />
<div>This page is designed to help new owners of LimeSDR hardware get started as quickly as possible. <br />
<br />
== Assembling the hardware ==<br />
<br />
[[File:LimeSDR-USB_acrylic_case_asembly.jpg|700px]]<br />
<br />
The LimeSDR comes with multiple RF ports, to which U.FL to SMA cables can be connected. Not all of these ports need to be used simultaneously, and your first step is to decide which of the ports you need to connect for your particular use case - along with, optionally, choosing a case compatible with the number of ports you are going to use.<br />
<br />
The below table explains the difference between each port on the LimeSDR.<br />
<br />
{| class="wikitable"<br />
|+LimeSDR-USB RF ports<br />
|-<br />
! Label<br />
! Description<br />
|-<br />
|RX1_H<br />
|Channel 1 RX - frequencies above 1.5GHz<br />
|-<br />
|RX2_H<br />
|Channel 2 RX - frequencies above 1.5GHz <br />
|-<br />
|RX1_L<br />
|Channel 1 RX - frequencies below 1.5GHz<br />
|-<br />
|RX2_L<br />
|Channel 2 RX - frequencies below 1.5GHz <br />
|-<br />
|RX1_W<br />
|Channel 1 RX - wideband<br />
|-<br />
|RX2_W<br />
|Channel 2 RX - wideband<br />
|-<br />
|TX1_1<br />
|Channel 1 TX - primary (all frequencies)<br />
|-<br />
|TX2_1<br />
|Channel 2 TX - primary (all frequencies)<br />
|-<br />
|TX1_2<br />
|Channel 1 TX - secondary (all frequencies)<br />
|-<br />
|TX2_2<br />
|Channel 2 TX - secondary (all frequencies)<br />
|}<br />
<br />
Note that: <br />
<br />
* Optimal RX performance is provided by using the *_H and *_L ports with the frequency bands shown;<br />
* The secondary TX ports for each channel can be used with power amplifiers covering different bands as well as for loopback, etc.;<br />
* You will need to select which ports you have chosen when configuring your software.<br />
<br />
<br />
If you have the official LimeSDR Acrylic Case, see the [https://github.com/myriadrf/LimeSDR-USB_acrylic_case#assembly assembly instructions here].<br />
<br />
== Connecting to your computer ==<br />
<br />
[[File:USB3 cable.jpg]]<br />
<br />
Depending on which LimeSDR board variant you have, it will require one of the following '''USB 3.0''' cables:<br />
<br />
* Type A plug to Type Micro B plug<br />
* Type A plug to A socket<br />
<br />
Note that the LimeSDR is a powerful device, and may not receive the power it needs from a single USB port. The use of a Y-splitter, which uses one Type A plug for power and data and a second Type A plug for additional power, is recommended; users of portable devices like the Apple MacBook Air or Microsoft Surface families, which have USB ports on opposite sides of the device, may also require a USB extension cable which should be connected to the secondary, power-only, leg of the Y-splitter.<br />
<br />
== Install Lime Suite ==<br />
<br />
[[File:lime_suite_comps.png|700px]]<br />
<br />
Lime Suite provides an SDR driver and a configuration interface along with numerous utilities. Support is provided for the following platforms:<br />
<br />
* GNU/Linux, including official packages for Ubuntu Linux;<br />
* Apple macOS via Homebrew;<br />
* Microsoft Windows via the PothosSDR Installer.<br />
<br />
Lime Suite can be installed by compiling from source or via binary packages. Note that in the case of Windows a hardware driver must also be installed as a separate part of the process.<br />
<br />
For further details see the [[Lime Suite|Lime Suite documentation]].<br />
<br />
== Testing the LimeSDR ==<br />
<br />
[[File:LimeSDR-USB SelfTest FFT.jpg|700px]]<br />
<br />
=== Updating the firmware and gateware ===<br />
<br />
The LimeSDR relies on firmware and gateware loaded onto its FPGA to operate, collectively known as the firmware. This firmware is constantly updated to improve the LimeSDR's functionality and reliability, and running the latest version is recommended.<br />
<br />
To update the LimeSDR's firmware, as well as to test the communication between the host PC and the LimeSDR, open your operating system's command-line interface and run the following command:<br />
<br />
<code><br />
LimeUtil --update<br />
</code><br />
<br />
This will update both the firmware and the gateware on the LimeSDR to the version supplied with your copy of Lime Suite. Do not disconnect the LimeSDR during the update process.<br />
<br />
=== Testing basic operations ===<br />
<br />
Instructions for carrying out a loopback test using Lime Suite are available on the page [[LimeSDR-USB Quick Test]]. This loopback test is the simplest and most direct way of confirming that you have a functioning board with appropriate USB controller firmware and FPGA gateware loaded.<br />
<br />
=== Testing via SoapySDR ===<br />
<br />
The [[Lime_Suite#Device_enumeration|Lime Suite wiki page]] explains how LimeUtil can be used to get a list of available devices and SoapySDRUtil to verify that it will be available to SDR ecosystem applications via SoapySDR. Providing the LimeSDR is listed by SoapySDRUtil, you are ready to begin working with it using the compatible software of your choice.<br />
<br />
{{Community}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeADPD&diff=1067
LimeADPD
2017-06-03T22:16:58Z
<p>Ghalfacree: Capitalisation correction.</p>
<hr />
<div>==Introduction==<br />
Power amplifiers (PA) are nonlinear devices and their linearisation is highly desired for a number of reasons. In case of radiofrequency (RF) PAs, linearisation improves power efficiency and subsequently reduces running cost of the wireless infrastructure.<br />
<br />
Considering the PA performance for a given air interface, adjacent channel power ratio (ACPR) and error vector magnitude (EVM) are the key considerations to provide support for sophisticated modulation schemes, multicarrier signals, and high modulation bandwidths.<br />
<br />
Here we present the Lime Microsystems solution for PA linearisation, based on adaptive digital predistortion (ADPD), for which the complete solution is Open Source and will be made available on GitHub and the LimeNET app store.<br />
<br />
==LimeADPD structure==<br />
===Indirect learning architecture===<br />
The simplified block diagram of an indirect learning architecture is given below. Please note that RF part in neither the TX (up to PA input) nor in RX (back to base band frequency) paths are shown for simplicity.<br />
<br />
Delay line compensates ADPD loop (<math>{yp(n)}</math> to <math>{x(n)}</math>) delay. Postdistorter is trained to be inverse of power amplifier. Predistorter is simple copy of postdistorter. When converged:<br />
<br />
<math><br />
\begin{align}<br />
\varepsilon {(n)} = 0, {yp(n)} = {y(n)} => {x(n)} = {xp(n)}<br />
\end{align}<br />
</math><br />
<br />
Hence, PA is linearised.<br />
<br />
[[File:Adpd-indirect-learning-architecture-block-diagram.png|center|550px|ADPD indirect learning architecture block diagram]]<br />
<br />
===Complex valued memory polynomial===<br />
The LimeADPD algorithm is based on modelling nonlinear system (PA and its inverse, in this case) by complex valued memory polynomials. These are, in fact, cut versions of Volterra series, an approach well known for general nonlinear system modelling and identification. Here, "cut version" means the system can efficiently be implemented in real life applications.<br />
<br />
For a given complex input:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{x} {(n)} = {x_{I}(n)} + \mathbf{j} {x_{Q}(n)},<br />
\end{align}<br />
</math><br />
<br />
complex valued memory polynomial produces complex output:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y} {(n)} = {y_{I}(n)} + \mathbf{j} {y_{Q}(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y} {(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{x} ({n} - {i}) {e} ({n} - {i})^{j},<br />
\end{align}<br />
</math><br />
<br />
where:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{a}_{ij} = a_{ij} + \mathbf{j} {b_{ij}},<br />
\end{align}<br />
</math><br />
<br />
are the polynomial coefficients while <math>{e(n)}</math> is the envelope of the input. For the envelope calculation two options are considered, the usual one:<br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = \sqrt{{x}_{I}({n})^2 + {x}_{Q}({n})^2},<br />
\end{align}<br />
</math><br />
<br />
and the squared one:<br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = {x_{I}(n)}^2 + {x_{Q}(n)}^2.<br />
\end{align}<br />
</math><br />
<br />
Typically, the squared option is used in ADPD applications since it is simpler to calculate and in most cases provides better results.<br />
<br />
In the above equations, <math>{N}</math> is memory length while <math>{M}</math> represents nonlinearity order. Hence, complex valued memory polynomial can take into account both system memory effects and system nonlinearity.<br />
<br />
===LimeADPD equations===<br />
Based on discussions given in previous sections and using the signal notations of the above figure, the ADPD predistorter implements the following equations:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{yp}{(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{xp}{(n} - {i)ep(n} - {i)}^{j},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{xp}{(n)} = {xp}_{I}{(n)} + \mathbf{j} {xp}_{Q}{(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
{ep(n)} = {xp}_{I}{(n)}^2 + {xp}_{Q}{(n)}^2,<br />
\end{align}<br />
</math><br />
<br />
while the postdistorter does similar:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y}{(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{x}{(n} - {i)e(n} - {i)}^{j},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{x}{(n)} = {x}_{I}{(n)} + \mathbf{j} {x}_{Q}{(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = {x}_{I}{(n)}^2 + {x}_{Q}{(n)}^2.<br />
\end{align}<br />
</math><br />
<br />
Note that predistorter and postdistorter share the same set of complex coefficients <math>\mathbf{a}_{ij}</math>. The delay line is simple and its output is given by:<br />
<br />
<math><br />
\begin{align}<br />
{u(n)} = \mathbf{yp}{(n} - {nd)}.<br />
\end{align}<br />
</math><br />
<br />
===Training algorithm===<br />
The ADPD training algorithm alters complex valued memory polynomial coefficients <math>\mathbf{a}_{ij}</math> in order to minimise the difference between PA input <math>\mathbf{yp}{(n)}</math> and PA output <math>\mathbf{x}{(n)}</math>, ignoring the delay and gain difference between the two signals. Instantaneous error shown in the above figure is calculated as:<br />
<br />
<math><br />
\begin{align}<br />
\varepsilon {(n)} = \sqrt{\big({u_{I}(n)} - {y_{I}(n)}\big)^2 + \big({u_{Q}(n)} - {y_{Q}(n)}\big)^2}.<br />
\end{align}<br />
</math><br />
<br />
Training is based on minimising Recursive Least Square (RLS) <math>{E(n)}</math> error:<br />
<br />
<math><br />
\begin{align}<br />
{E(n)} = \frac{1}{2} \sum_{m=0}^{n} \lambda^{n-m} \varepsilon {(m)}^2 , \lambda < 1,<br />
\end{align}<br />
</math><br />
<br />
by solving a linear system of equations:<br />
<br />
<math><br />
\begin{align}<br />
{\partial E(n) \over \partial a_{kl}} = 0, {\partial E(n) \over \partial b_{kl}} = 0; k = 0,1,\ldots,N; l=0,1,\ldots,M.<br />
\end{align}<br />
</math><br />
<br />
Any linear equation system solving algorithm can be used. LimeADPD involves LU decomposition, however iterative techniques such as Gauss-Seidel and Gradient Descent have been evaluated as well. LU decomposition is adopted in order to get faster adaptation and tracking of the ADPD loop.<br />
<br />
==Implementation platform==<br />
The ADPD algorithm is implemented using a LimeSDR-QPCIe board, a high level block diagram of which is shown below. The LimeSDR-QPCIe board has a lot more options than shown, including two LMS7002M chips, a USB interface, GPS receiver…) The LMS7002M itself is a 2T-2R RF IC. For clarity, the block diagram shows the minimum hardware options required to illustrate the LimeADPD implementation. Regarding the implementation, the same signal names as in the previous figure are used here.<br />
<br />
[[File:Adpd-implementation-on-limesdr-qpcie-board-block-diagram.png|center|550px|An ADPD implementation block diagram, based on the LimeSDR-QPCIe board]]<br />
<br />
For development or demonstration, a test waveform is uploaded first and played from the WFM RAM Block. Initially, the predistorter is bypassed - i.e. <math>{yp_{I}=xp_{I}}</math>, <math>{yp_{Q}=xp_{Q}}</math>. The predistorter has provision for SPI in order to update the coefficients during the training. Signals <math>\mathbf{xp}</math>, <math>\mathbf{yp}</math>, and <math>\mathbf{x}</math> are captured using Data Capture RAM Blocks. Captured data is made available to the (Intel Motherboard) CPU Core via the PCIe interface. The CPU implements the postdistorter block, delay line, and the rest of training algorithm. After each adaptation step the CPU updates predistorter parameters via PCIe/Stream SPI.<br />
<br />
In real applications WFM and <math>\mathbf{xp}</math> Capture RAM blocks are not required. The algorithm needs only <math>\mathbf{yp}</math> and <math>\mathbf{x}</math> as shown in [[#LimeADPD_structure|LimeADPD structure]]. The CPU Core performs both ADPD adaptation, as explained above, and baseband (BB) digital modem functions which are application specific, for example Long Term Evolution (LTE).<br />
<br />
As shown in the block diagram above, frequency conversion from BB to RF is performed by LMS7002M transmitter chains. Frequency down conversion from RF to BB is implemented by only one LMS7002M receive chain dedicated to ADPD; in other words, one receiver of the available RF RX chains is allocated as ADPD monitoring path. In case of MIMO applications, the same ADPD monitoring path is used as time sharing recourse to linearise multiple PAs which saves power consumption as well as on board RF resources.<br />
<br />
Regarding data converters, the LimeSDR-QPCIe board offers two options: to use LMS7002M on-chip DACs/ADCs, or external ones. On-chip data converters are 12-bit devices, while external ones are 14-bit. 14-bit data converters are more suitable for ADPD if one wants to cancel IMD3 and IMD5 as well as to support wide band modulation schemes. If external data converters are used, the LMS7002M on-chip Transceiver Signal Processing blocks (TXTSP and RXTSP) are bypassed. In this case, minimum functionality required for ADPD to function is implemented by external counterparts shown as ExtTXTSP and ExtRXTSP in the block diagram above.<br />
<br />
WFM and Data capture RAM Blocks are implemented using Altera Cyclone V FPGA resources and on-board RAM. More importantly, the same FPGA also implements predistorter, ExtTXTSP, ExtRXTSP blocks, PCIe, and other glue logic required to interconnect LimeSDR-QPCIe on board components including the two LMS7002M ICs to the CPU Core.<br />
<br />
==Measured Results==<br />
Before implementation and measurements, the ADPD algorithm has been thoroughly simulated. Simulation results are omitted from this document for clarity. ADPD performance has been measured and the results for two cases presented in this section.<br />
<br />
'''Test Case 1:'''<br />
: Moderate output power amplifier device Maxim Integrated MAX2612.<br />
: Psat ~ 19dBm.<br />
<br />
'''Test Case 2:'''<br />
: MAX2612 is used as preamplifier stage followed by a Class-J GaN HEMPT amplifier.<br />
: GaN amplifier drain efficiency ~ 70%.<br />
: Psat ~ 40dBm.<br />
<br />
Single carrier WCDMA Test Model 1 is used as test signal in both cases. ADPD memory and nonlinearity orders are set to <math>{N=3}</math>, <math>{M=3}</math>.<br />
<br />
===Test case 1: Maxim Integrated MAX2612 PA===<br />
[[#ADPD_signals_before_training|ADPD signals before training]] and [[#ADPD_signals_after_training|ADPD signals after training]] show important ADPD signals before and after the algorithm convergence. Signals are captured by a graphical user interface (GUI) executed by the CPU Core.<br />
<br />
Before training ([[#ADPD_signals_before_training|ADPD signals before training]]), predistorter signals <math>\mathbf{yp}</math> and <math>\mathbf{xp}</math> are equal (plot 1). <math>\mathbf{x}</math> as a measure of PA output is distorted (plot 3). Waveforms <math>\mathbf{y}</math> and <math>\mathbf{u}</math> are very different (plot 2), resulting in huge error (plot 4) which ADPD has to minimise.<br />
<br />
After ADPD training ([[#ADPD_signals_after_training|ADPD signals after training]]), signal <math>\mathbf{yp}</math> (plot 1) is predistorted in order to cancel PA distortion components. <math>\mathbf{x}</math> as a measure of PA output is now linearised (plot 3). There is an excellent match between <math>\mathbf{y}</math> and <math>\mathbf{u}</math> waveforms in both time and amplitude scale (plot 2). ADPD error (plot 4) is minimised. Improvement in PA linearisation can be seen by comparing the <math>\mathbf{yp}</math> and <math>\mathbf{x}</math> spectra of plot 3.<br />
<br />
====ADPD signals before training====<br />
[[File:Adpd-test-case-1-signals-before-training.png|center|550px|ADPD test case 1, signals before training]]<br />
<br />
====ADPD signals after training====<br />
[[File:Adpd-test-case-1-signals-after-training.png|center|550px|ADPD test case 1, signals after training]]<br />
<br />
RF PA output measurements are shown below.<br />
<br />
====PA output spectrum====<br />
[[File:Adpd-test-case-1-pa-output-spectrum.png|center|550px|ADPD test case 1, PA output spectrum]]<br />
No ADPD – yellow trace. With ADPD – blue trace. <br />
IMD3 and IMD5 distortion components at the PA output reduced by almost 20 dB.<br />
<br />
====ACPR without ADPD====<br />
[[File:Adpd-test-case-1-acpr-without-adpd.png|center|550px|ADPD test case 1, ACPR without ADPD]]<br />
ACPR1 = -34 dBc, ACPR2 = -54 dBc.<br />
<br />
====ACPR with ADPD====<br />
[[File:Adpd-test-case-1-acpr-with-adpd.png|center|550px|ADPD test case 1, ACPR with ADPD]]<br />
ACPR1 = -51 dBc, ACPR2 = -52 dBc.<br />
<br />
====EVM without ADPD====<br />
[[File:Adpd-test-case-1-evm-without-adpd.png|center|550px|ADPD test case 1, EVM without ADPD]]<br />
Measured at 6.58%.<br />
<br />
====EVM with ADPD====<br />
[[File:Adpd-test-case-1-evm-with-adpd.png|center|550px|ADPD test case 1, EVM with ADPD]]<br />
Measured at 3.24%.<br />
<br />
===Test case 2: Class-J GaN HEMPT amplifier===<br />
====ACPR without ADPD====<br />
[[File:Adpd-test-case-2-acpr-without-adpd.png|center|550px|ADPD test case 2, ACPR without ADPD]]<br />
ACPR1 = -43 dBc, ACPR2 = -58dBc.<br />
<br />
====ACPR with ADPD====<br />
[[File:Adpd-test-case-2-acpr-with-adpd.png|center|550px|ADPD test case 2, ACPR with ADPD]]<br />
ACPR1 = -53 dBc, ACPR2 = -58dBc.<br />
<br />
==Conclusion==<br />
The LimeADPD algorithm has been confirmed by measured results. ADPD is capable of cancelling any distortion above system (DACs -> TX -> PA -> Coupler -> Attenuator -> RX -> ADCs) noise floor.<br />
<br />
For [[#Test_case_1:_Maxim_Integrated_MAX2612_PA|test case 1]], at antenna point (PA output) ACPR is improved from -34 dBc (out of spec.) to -51 dBc (well within the spec.) EVM is improved from 6.58% to 3.24%.<br />
<br />
As far as linearisation is concerned, [[#Test_case_2:_Class-J_GaN_HEMPT_amplifier|test case 2]] is more challenging since there are two PA stages (MAX2612 followed by a Class-J GaN HEMPT amplifier) and both stages are nonlinear. Even in this case LimeADPD gives excellent results, i.e. ACPR is improved from -43 dBc (out of spec.) to -53 dBc (well within the spec.)<br />
<br />
==Work underway==<br />
* Test ADPD algorithm with 10W PAs covering different frequency bands.<br />
* Check the performance with more demanding modulation schemes; using 5MHz, 10MHz, 15MHz, and 20MHz LTE as the test signal, for example.<br />
* Modify the algorithm to linearise more than one PA for MIMO applications using single ADPD monitoring path.<br />
* Test the algorithm performance in real applications, i.e. within the base station during voice, video, and data calls.<br />
<br />
==Document version==<br />
Based on Adaptive Digital Predistortion of RF Power Amplifiers Application Note v3r00.<br />
<br />
Changes since document generation:<br />
* Minor typographical and grammatical changes.<br />
<br />
{{LimeMicro}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeADPD&diff=1066
LimeADPD
2017-06-03T22:16:09Z
<p>Ghalfacree: Changed comma to full stop.</p>
<hr />
<div>==Introduction==<br />
Power amplifiers (PA) are nonlinear devices and their linearisation is highly desired for a number of reasons. In case of radiofrequency (RF) PAs, linearisation improves power efficiency and subsequently reduces running cost of the wireless infrastructure.<br />
<br />
Considering the PA performance for a given air interface, adjacent channel power ratio (ACPR) and error vector magnitude (EVM) are the key considerations to provide support for sophisticated modulation schemes, multicarrier signals, and high modulation bandwidths.<br />
<br />
Here we present the Lime Microsystems solution for PA linearisation, based on adaptive digital predistortion (ADPD), for which the complete solution is Open Source and will be made available on GitHub and the LimeNET app store.<br />
<br />
==LimeADPD structure==<br />
===Indirect learning architecture===<br />
The simplified block diagram of an indirect learning architecture is given below. Please note that RF part in neither the TX (up to PA input) nor in RX (back to base band frequency) paths are shown for simplicity.<br />
<br />
Delay line compensates ADPD loop (<math>{yp(n)}</math> to <math>{x(n)}</math>) delay. Postdistorter is trained to be inverse of power amplifier. Predistorter is simple copy of postdistorter. When converged:<br />
<br />
<math><br />
\begin{align}<br />
\varepsilon {(n)} = 0, {yp(n)} = {y(n)} => {x(n)} = {xp(n)}<br />
\end{align}<br />
</math><br />
<br />
Hence, PA is linearised.<br />
<br />
[[File:Adpd-indirect-learning-architecture-block-diagram.png|center|550px|ADPD indirect learning architecture block diagram]]<br />
<br />
===Complex valued memory polynomial===<br />
The LimeADPD algorithm is based on modelling nonlinear system (PA and its inverse, in this case) by complex valued memory polynomials. These are, in fact, cut versions of Volterra series, an approach well known for general nonlinear system modelling and identification. Here, "cut version" means the system can efficiently be implemented in real life applications.<br />
<br />
For a given complex input:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{x} {(n)} = {x_{I}(n)} + \mathbf{j} {x_{Q}(n)},<br />
\end{align}<br />
</math><br />
<br />
complex valued memory polynomial produces complex output:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y} {(n)} = {y_{I}(n)} + \mathbf{j} {y_{Q}(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y} {(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{x} ({n} - {i}) {e} ({n} - {i})^{j},<br />
\end{align}<br />
</math><br />
<br />
where:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{a}_{ij} = a_{ij} + \mathbf{j} {b_{ij}},<br />
\end{align}<br />
</math><br />
<br />
are the polynomial coefficients while <math>{e(n)}</math> is the envelope of the input. For the envelope calculation two options are considered, the usual one:<br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = \sqrt{{x}_{I}({n})^2 + {x}_{Q}({n})^2},<br />
\end{align}<br />
</math><br />
<br />
and the squared one:<br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = {x_{I}(n)}^2 + {x_{Q}(n)}^2.<br />
\end{align}<br />
</math><br />
<br />
Typically, the squared option is used in ADPD applications since it is simpler to calculate and in most cases provides better results.<br />
<br />
In the above equations, <math>{N}</math> is memory length while <math>{M}</math> represents nonlinearity order. Hence, complex valued memory polynomial can take into account both system memory effects and system nonlinearity.<br />
<br />
===LimeADPD Equations===<br />
Based on discussions given in previous sections and using the signal notations of the above figure, the ADPD predistorter implements the following equations:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{yp}{(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{xp}{(n} - {i)ep(n} - {i)}^{j},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{xp}{(n)} = {xp}_{I}{(n)} + \mathbf{j} {xp}_{Q}{(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
{ep(n)} = {xp}_{I}{(n)}^2 + {xp}_{Q}{(n)}^2,<br />
\end{align}<br />
</math><br />
<br />
while the postdistorter does similar:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y}{(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{x}{(n} - {i)e(n} - {i)}^{j},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{x}{(n)} = {x}_{I}{(n)} + \mathbf{j} {x}_{Q}{(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = {x}_{I}{(n)}^2 + {x}_{Q}{(n)}^2.<br />
\end{align}<br />
</math><br />
<br />
Note that predistorter and postdistorter share the same set of complex coefficients <math>\mathbf{a}_{ij}</math>. The delay line is simple and its output is given by:<br />
<br />
<math><br />
\begin{align}<br />
{u(n)} = \mathbf{yp}{(n} - {nd)}.<br />
\end{align}<br />
</math><br />
<br />
===Training algorithm===<br />
The ADPD training algorithm alters complex valued memory polynomial coefficients <math>\mathbf{a}_{ij}</math> in order to minimise the difference between PA input <math>\mathbf{yp}{(n)}</math> and PA output <math>\mathbf{x}{(n)}</math>, ignoring the delay and gain difference between the two signals. Instantaneous error shown in the above figure is calculated as:<br />
<br />
<math><br />
\begin{align}<br />
\varepsilon {(n)} = \sqrt{\big({u_{I}(n)} - {y_{I}(n)}\big)^2 + \big({u_{Q}(n)} - {y_{Q}(n)}\big)^2}.<br />
\end{align}<br />
</math><br />
<br />
Training is based on minimising Recursive Least Square (RLS) <math>{E(n)}</math> error:<br />
<br />
<math><br />
\begin{align}<br />
{E(n)} = \frac{1}{2} \sum_{m=0}^{n} \lambda^{n-m} \varepsilon {(m)}^2 , \lambda < 1,<br />
\end{align}<br />
</math><br />
<br />
by solving a linear system of equations:<br />
<br />
<math><br />
\begin{align}<br />
{\partial E(n) \over \partial a_{kl}} = 0, {\partial E(n) \over \partial b_{kl}} = 0; k = 0,1,\ldots,N; l=0,1,\ldots,M.<br />
\end{align}<br />
</math><br />
<br />
Any linear equation system solving algorithm can be used. LimeADPD involves LU decomposition, however iterative techniques such as Gauss-Seidel and Gradient Descent have been evaluated as well. LU decomposition is adopted in order to get faster adaptation and tracking of the ADPD loop.<br />
<br />
==Implementation platform==<br />
The ADPD algorithm is implemented using a LimeSDR-QPCIe board, a high level block diagram of which is shown below. The LimeSDR-QPCIe board has a lot more options than shown, including two LMS7002M chips, a USB interface, GPS receiver…) The LMS7002M itself is a 2T-2R RF IC. For clarity, the block diagram shows the minimum hardware options required to illustrate the LimeADPD implementation. Regarding the implementation, the same signal names as in the previous figure are used here.<br />
<br />
[[File:Adpd-implementation-on-limesdr-qpcie-board-block-diagram.png|center|550px|An ADPD implementation block diagram, based on the LimeSDR-QPCIe board]]<br />
<br />
For development or demonstration, a test waveform is uploaded first and played from the WFM RAM Block. Initially, the predistorter is bypassed - i.e. <math>{yp_{I}=xp_{I}}</math>, <math>{yp_{Q}=xp_{Q}}</math>. The predistorter has provision for SPI in order to update the coefficients during the training. Signals <math>\mathbf{xp}</math>, <math>\mathbf{yp}</math>, and <math>\mathbf{x}</math> are captured using Data Capture RAM Blocks. Captured data is made available to the (Intel Motherboard) CPU Core via the PCIe interface. The CPU implements the postdistorter block, delay line, and the rest of training algorithm. After each adaptation step the CPU updates predistorter parameters via PCIe/Stream SPI.<br />
<br />
In real applications WFM and <math>\mathbf{xp}</math> Capture RAM blocks are not required. The algorithm needs only <math>\mathbf{yp}</math> and <math>\mathbf{x}</math> as shown in [[#LimeADPD_structure|LimeADPD structure]]. The CPU Core performs both ADPD adaptation, as explained above, and baseband (BB) digital modem functions which are application specific, for example Long Term Evolution (LTE).<br />
<br />
As shown in the block diagram above, frequency conversion from BB to RF is performed by LMS7002M transmitter chains. Frequency down conversion from RF to BB is implemented by only one LMS7002M receive chain dedicated to ADPD; in other words, one receiver of the available RF RX chains is allocated as ADPD monitoring path. In case of MIMO applications, the same ADPD monitoring path is used as time sharing recourse to linearise multiple PAs which saves power consumption as well as on board RF resources.<br />
<br />
Regarding data converters, the LimeSDR-QPCIe board offers two options: to use LMS7002M on-chip DACs/ADCs, or external ones. On-chip data converters are 12-bit devices, while external ones are 14-bit. 14-bit data converters are more suitable for ADPD if one wants to cancel IMD3 and IMD5 as well as to support wide band modulation schemes. If external data converters are used, the LMS7002M on-chip Transceiver Signal Processing blocks (TXTSP and RXTSP) are bypassed. In this case, minimum functionality required for ADPD to function is implemented by external counterparts shown as ExtTXTSP and ExtRXTSP in the block diagram above.<br />
<br />
WFM and Data capture RAM Blocks are implemented using Altera Cyclone V FPGA resources and on-board RAM. More importantly, the same FPGA also implements predistorter, ExtTXTSP, ExtRXTSP blocks, PCIe, and other glue logic required to interconnect LimeSDR-QPCIe on board components including the two LMS7002M ICs to the CPU Core.<br />
<br />
==Measured Results==<br />
Before implementation and measurements, the ADPD algorithm has been thoroughly simulated. Simulation results are omitted from this document for clarity. ADPD performance has been measured and the results for two cases presented in this section.<br />
<br />
'''Test Case 1:'''<br />
: Moderate output power amplifier device Maxim Integrated MAX2612.<br />
: Psat ~ 19dBm.<br />
<br />
'''Test Case 2:'''<br />
: MAX2612 is used as preamplifier stage followed by a Class-J GaN HEMPT amplifier.<br />
: GaN amplifier drain efficiency ~ 70%.<br />
: Psat ~ 40dBm.<br />
<br />
Single carrier WCDMA Test Model 1 is used as test signal in both cases. ADPD memory and nonlinearity orders are set to <math>{N=3}</math>, <math>{M=3}</math>.<br />
<br />
===Test case 1: Maxim Integrated MAX2612 PA===<br />
[[#ADPD_signals_before_training|ADPD signals before training]] and [[#ADPD_signals_after_training|ADPD signals after training]] show important ADPD signals before and after the algorithm convergence. Signals are captured by a graphical user interface (GUI) executed by the CPU Core.<br />
<br />
Before training ([[#ADPD_signals_before_training|ADPD signals before training]]), predistorter signals <math>\mathbf{yp}</math> and <math>\mathbf{xp}</math> are equal (plot 1). <math>\mathbf{x}</math> as a measure of PA output is distorted (plot 3). Waveforms <math>\mathbf{y}</math> and <math>\mathbf{u}</math> are very different (plot 2), resulting in huge error (plot 4) which ADPD has to minimise.<br />
<br />
After ADPD training ([[#ADPD_signals_after_training|ADPD signals after training]]), signal <math>\mathbf{yp}</math> (plot 1) is predistorted in order to cancel PA distortion components. <math>\mathbf{x}</math> as a measure of PA output is now linearised (plot 3). There is an excellent match between <math>\mathbf{y}</math> and <math>\mathbf{u}</math> waveforms in both time and amplitude scale (plot 2). ADPD error (plot 4) is minimised. Improvement in PA linearisation can be seen by comparing the <math>\mathbf{yp}</math> and <math>\mathbf{x}</math> spectra of plot 3.<br />
<br />
====ADPD signals before training====<br />
[[File:Adpd-test-case-1-signals-before-training.png|center|550px|ADPD test case 1, signals before training]]<br />
<br />
====ADPD signals after training====<br />
[[File:Adpd-test-case-1-signals-after-training.png|center|550px|ADPD test case 1, signals after training]]<br />
<br />
RF PA output measurements are shown below.<br />
<br />
====PA output spectrum====<br />
[[File:Adpd-test-case-1-pa-output-spectrum.png|center|550px|ADPD test case 1, PA output spectrum]]<br />
No ADPD – yellow trace. With ADPD – blue trace. <br />
IMD3 and IMD5 distortion components at the PA output reduced by almost 20 dB.<br />
<br />
====ACPR without ADPD====<br />
[[File:Adpd-test-case-1-acpr-without-adpd.png|center|550px|ADPD test case 1, ACPR without ADPD]]<br />
ACPR1 = -34 dBc, ACPR2 = -54 dBc.<br />
<br />
====ACPR with ADPD====<br />
[[File:Adpd-test-case-1-acpr-with-adpd.png|center|550px|ADPD test case 1, ACPR with ADPD]]<br />
ACPR1 = -51 dBc, ACPR2 = -52 dBc.<br />
<br />
====EVM without ADPD====<br />
[[File:Adpd-test-case-1-evm-without-adpd.png|center|550px|ADPD test case 1, EVM without ADPD]]<br />
Measured at 6.58%.<br />
<br />
====EVM with ADPD====<br />
[[File:Adpd-test-case-1-evm-with-adpd.png|center|550px|ADPD test case 1, EVM with ADPD]]<br />
Measured at 3.24%.<br />
<br />
===Test case 2: Class-J GaN HEMPT amplifier===<br />
====ACPR without ADPD====<br />
[[File:Adpd-test-case-2-acpr-without-adpd.png|center|550px|ADPD test case 2, ACPR without ADPD]]<br />
ACPR1 = -43 dBc, ACPR2 = -58dBc.<br />
<br />
====ACPR with ADPD====<br />
[[File:Adpd-test-case-2-acpr-with-adpd.png|center|550px|ADPD test case 2, ACPR with ADPD]]<br />
ACPR1 = -53 dBc, ACPR2 = -58dBc.<br />
<br />
==Conclusion==<br />
The LimeADPD algorithm has been confirmed by measured results. ADPD is capable of cancelling any distortion above system (DACs -> TX -> PA -> Coupler -> Attenuator -> RX -> ADCs) noise floor.<br />
<br />
For [[#Test_case_1:_Maxim_Integrated_MAX2612_PA|test case 1]], at antenna point (PA output) ACPR is improved from -34 dBc (out of spec.) to -51 dBc (well within the spec.) EVM is improved from 6.58% to 3.24%.<br />
<br />
As far as linearisation is concerned, [[#Test_case_2:_Class-J_GaN_HEMPT_amplifier|test case 2]] is more challenging since there are two PA stages (MAX2612 followed by a Class-J GaN HEMPT amplifier) and both stages are nonlinear. Even in this case LimeADPD gives excellent results, i.e. ACPR is improved from -43 dBc (out of spec.) to -53 dBc (well within the spec.)<br />
<br />
==Work underway==<br />
* Test ADPD algorithm with 10W PAs covering different frequency bands.<br />
* Check the performance with more demanding modulation schemes; using 5MHz, 10MHz, 15MHz, and 20MHz LTE as the test signal, for example.<br />
* Modify the algorithm to linearise more than one PA for MIMO applications using single ADPD monitoring path.<br />
* Test the algorithm performance in real applications, i.e. within the base station during voice, video, and data calls.<br />
<br />
==Document version==<br />
Based on Adaptive Digital Predistortion of RF Power Amplifiers Application Note v3r00.<br />
<br />
Changes since document generation:<br />
* Minor typographical and grammatical changes.<br />
<br />
{{LimeMicro}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeADPD&diff=1065
LimeADPD
2017-06-03T22:05:05Z
<p>Ghalfacree: Initial page creation.</p>
<hr />
<div>==Introduction==<br />
Power amplifiers (PA) are nonlinear devices and their linearisation is highly desired for a number of reasons. In case of radiofrequency (RF) PAs, linearisation improves power efficiency and subsequently reduces running cost of the wireless infrastructure.<br />
<br />
Considering the PA performance for a given air interface, adjacent channel power ratio (ACPR) and error vector magnitude (EVM) are the key considerations to provide support for sophisticated modulation schemes, multicarrier signals, and high modulation bandwidths.<br />
<br />
Here we present the Lime Microsystems solution for PA linearisation, based on adaptive digital predistortion (ADPD), for which the complete solution is Open Source and will be made available on GitHub and the LimeNET app store.<br />
<br />
==LimeADPD structure==<br />
===Indirect learning architecture===<br />
The simplified block diagram of an indirect learning architecture is given below. Please note that RF part in neither the TX (up to PA input) nor in RX (back to base band frequency) paths are shown for simplicity.<br />
<br />
Delay line compensates ADPD loop (<math>{yp(n)}</math> to <math>{x(n)}</math>) delay. Postdistorter is trained to be inverse of power amplifier. Predistorter is simple copy of postdistorter. When converged:<br />
<br />
<math><br />
\begin{align}<br />
\varepsilon {(n)} = 0, {yp(n)} = {y(n)} => {x(n)} = {xp(n)}<br />
\end{align}<br />
</math><br />
<br />
Hence, PA is linearised.<br />
<br />
[[File:Adpd-indirect-learning-architecture-block-diagram.png|center|550px|ADPD indirect learning architecture block diagram]]<br />
<br />
===Complex valued memory polynomial===<br />
The LimeADPD algorithm is based on modelling nonlinear system (PA and its inverse, in this case) by complex valued memory polynomials. These are, in fact, cut versions of Volterra series, an approach well known for general nonlinear system modelling and identification. Here, "cut version" means the system can efficiently be implemented in real life applications.<br />
<br />
For a given complex input:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{x} {(n)} = {x_{I}(n)} + \mathbf{j} {x_{Q}(n)},<br />
\end{align}<br />
</math><br />
<br />
complex valued memory polynomial produces complex output:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y} {(n)} = {y_{I}(n)} + \mathbf{j} {y_{Q}(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y} {(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{x} ({n} - {i}) {e} ({n} - {i})^{j},<br />
\end{align}<br />
</math><br />
<br />
where:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{a}_{ij} = a_{ij} + \mathbf{j} {b_{ij}},<br />
\end{align}<br />
</math><br />
<br />
are the polynomial coefficients while <math>{e(n)}</math> is the envelope of the input. For the envelope calculation two options are considered, the usual one:<br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = \sqrt{{x}_{I}({n})^2 + {x}_{Q}({n})^2},<br />
\end{align}<br />
</math><br />
<br />
and the squared one:<br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = {x_{I}(n)}^2 + {x_{Q}(n)}^2.<br />
\end{align}<br />
</math><br />
<br />
Typically, the squared option is used in ADPD applications since it is simpler to calculate and in most cases provides better results.<br />
<br />
In the above equations, <math>{N}</math> is memory length while <math>{M}</math> represents nonlinearity order. Hence, complex valued memory polynomial can take into account both system memory effects and system nonlinearity.<br />
<br />
===LimeADPD Equations===<br />
Based on discussions given in previous sections and using the signal notations of the above figure, the ADPD predistorter implements the following equations:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{yp}{(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{xp}{(n} - {i)ep(n} - {i)}^{j},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{xp}{(n)} = {xp}_{I}{(n)} + \mathbf{j} {xp}_{Q}{(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
{ep(n)} = {xp}_{I}{(n)}^2 + {xp}_{Q}{(n)}^2,<br />
\end{align}<br />
</math><br />
<br />
while the postdistorter does similar:<br />
<br />
<math><br />
\begin{align}<br />
\mathbf{y}{(n)} = \sum_{i=0}^{N} \sum_{j=0}^{M} \mathbf{a}_{ij} \mathbf{x}{(n} - {i)e(n} - {i)}^{j},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
\mathbf{x}{(n)} = {x}_{I}{(n)} + \mathbf{j} {x}_{Q}{(n)},<br />
\end{align}<br />
</math><br />
<br />
<math><br />
\begin{align}<br />
{e(n)} = {x}_{I}{(n)}^2 + {x}_{Q}{(n)}^2,<br />
\end{align}<br />
</math><br />
<br />
Note that predistorter and postdistorter share the same set of complex coefficients <math>\mathbf{a}_{ij}</math>. The delay line is simple and its output is given by:<br />
<br />
<math><br />
\begin{align}<br />
{u(n)} = \mathbf{yp}{(n} - {nd)}.<br />
\end{align}<br />
</math><br />
<br />
===Training algorithm===<br />
The ADPD training algorithm alters complex valued memory polynomial coefficients <math>\mathbf{a}_{ij}</math> in order to minimise the difference between PA input <math>\mathbf{yp}{(n)}</math> and PA output <math>\mathbf{x}{(n)}</math>, ignoring the delay and gain difference between the two signals. Instantaneous error shown in the above figure is calculated as:<br />
<br />
<math><br />
\begin{align}<br />
\varepsilon {(n)} = \sqrt{\big({u_{I}(n)} - {y_{I}(n)}\big)^2 + \big({u_{Q}(n)} - {y_{Q}(n)}\big)^2}.<br />
\end{align}<br />
</math><br />
<br />
Training is based on minimising Recursive Least Square (RLS) <math>{E(n)}</math> error:<br />
<br />
<math><br />
\begin{align}<br />
{E(n)} = \frac{1}{2} \sum_{m=0}^{n} \lambda^{n-m} \varepsilon {(m)}^2 , \lambda < 1,<br />
\end{align}<br />
</math><br />
<br />
by solving a linear system of equations:<br />
<br />
<math><br />
\begin{align}<br />
{\partial E(n) \over \partial a_{kl}} = 0, {\partial E(n) \over \partial b_{kl}} = 0; k = 0,1,\ldots,N; l=0,1,\ldots,M.<br />
\end{align}<br />
</math><br />
<br />
Any linear equation system solving algorithm can be used. LimeADPD involves LU decomposition, however iterative techniques such as Gauss-Seidel and Gradient Descent have been evaluated as well. LU decomposition is adopted in order to get faster adaptation and tracking of the ADPD loop.<br />
<br />
==Implementation platform==<br />
The ADPD algorithm is implemented using a LimeSDR-QPCIe board, a high level block diagram of which is shown below. The LimeSDR-QPCIe board has a lot more options than shown, including two LMS7002M chips, a USB interface, GPS receiver…) The LMS7002M itself is a 2T-2R RF IC. For clarity, the block diagram shows the minimum hardware options required to illustrate the LimeADPD implementation. Regarding the implementation, the same signal names as in the previous figure are used here.<br />
<br />
[[File:Adpd-implementation-on-limesdr-qpcie-board-block-diagram.png|center|550px|An ADPD implementation block diagram, based on the LimeSDR-QPCIe board]]<br />
<br />
For development or demonstration, a test waveform is uploaded first and played from the WFM RAM Block. Initially, the predistorter is bypassed - i.e. <math>{yp_{I}=xp_{I}}</math>, <math>{yp_{Q}=xp_{Q}}</math>. The predistorter has provision for SPI in order to update the coefficients during the training. Signals <math>\mathbf{xp}</math>, <math>\mathbf{yp}</math>, and <math>\mathbf{x}</math> are captured using Data Capture RAM Blocks. Captured data is made available to the (Intel Motherboard) CPU Core via the PCIe interface. The CPU implements the postdistorter block, delay line, and the rest of training algorithm. After each adaptation step the CPU updates predistorter parameters via PCIe/Stream SPI.<br />
<br />
In real applications WFM and <math>\mathbf{xp}</math> Capture RAM blocks are not required. The algorithm needs only <math>\mathbf{yp}</math> and <math>\mathbf{x}</math> as shown in [[#LimeADPD_structure|LimeADPD structure]]. The CPU Core performs both ADPD adaptation, as explained above, and baseband (BB) digital modem functions which are application specific, for example Long Term Evolution (LTE).<br />
<br />
As shown in the block diagram above, frequency conversion from BB to RF is performed by LMS7002M transmitter chains. Frequency down conversion from RF to BB is implemented by only one LMS7002M receive chain dedicated to ADPD; in other words, one receiver of the available RF RX chains is allocated as ADPD monitoring path. In case of MIMO applications, the same ADPD monitoring path is used as time sharing recourse to linearise multiple PAs which saves power consumption as well as on board RF resources.<br />
<br />
Regarding data converters, the LimeSDR-QPCIe board offers two options: to use LMS7002M on-chip DACs/ADCs, or external ones. On-chip data converters are 12-bit devices, while external ones are 14-bit. 14-bit data converters are more suitable for ADPD if one wants to cancel IMD3 and IMD5 as well as to support wide band modulation schemes. If external data converters are used, the LMS7002M on-chip Transceiver Signal Processing blocks (TXTSP and RXTSP) are bypassed. In this case, minimum functionality required for ADPD to function is implemented by external counterparts shown as ExtTXTSP and ExtRXTSP in the block diagram above.<br />
<br />
WFM and Data capture RAM Blocks are implemented using Altera Cyclone V FPGA resources and on-board RAM. More importantly, the same FPGA also implements predistorter, ExtTXTSP, ExtRXTSP blocks, PCIe, and other glue logic required to interconnect LimeSDR-QPCIe on board components including the two LMS7002M ICs to the CPU Core.<br />
<br />
==Measured Results==<br />
Before implementation and measurements, the ADPD algorithm has been thoroughly simulated. Simulation results are omitted from this document for clarity. ADPD performance has been measured and the results for two cases presented in this section.<br />
<br />
'''Test Case 1:'''<br />
: Moderate output power amplifier device Maxim Integrated MAX2612.<br />
: Psat ~ 19dBm.<br />
<br />
'''Test Case 2:'''<br />
: MAX2612 is used as preamplifier stage followed by a Class-J GaN HEMPT amplifier.<br />
: GaN amplifier drain efficiency ~ 70%.<br />
: Psat ~ 40dBm.<br />
<br />
Single carrier WCDMA Test Model 1 is used as test signal in both cases. ADPD memory and nonlinearity orders are set to <math>{N=3}</math>, <math>{M=3}</math>.<br />
<br />
===Test case 1: Maxim Integrated MAX2612 PA===<br />
[[#ADPD_signals_before_training|ADPD signals before training]] and [[#ADPD_signals_after_training|ADPD signals after training]] show important ADPD signals before and after the algorithm convergence. Signals are captured by a graphical user interface (GUI) executed by the CPU Core.<br />
<br />
Before training ([[#ADPD_signals_before_training|ADPD signals before training]]), predistorter signals <math>\mathbf{yp}</math> and <math>\mathbf{xp}</math> are equal (plot 1). <math>\mathbf{x}</math> as a measure of PA output is distorted (plot 3). Waveforms <math>\mathbf{y}</math> and <math>\mathbf{u}</math> are very different (plot 2), resulting in huge error (plot 4) which ADPD has to minimise.<br />
<br />
After ADPD training ([[#ADPD_signals_after_training|ADPD signals after training]]), signal <math>\mathbf{yp}</math> (plot 1) is predistorted in order to cancel PA distortion components. <math>\mathbf{x}</math> as a measure of PA output is now linearised (plot 3). There is an excellent match between <math>\mathbf{y}</math> and <math>\mathbf{u}</math> waveforms in both time and amplitude scale (plot 2). ADPD error (plot 4) is minimised. Improvement in PA linearisation can be seen by comparing the <math>\mathbf{yp}</math> and <math>\mathbf{x}</math> spectra of plot 3.<br />
<br />
====ADPD signals before training====<br />
[[File:Adpd-test-case-1-signals-before-training.png|center|550px|ADPD test case 1, signals before training]]<br />
<br />
====ADPD signals after training====<br />
[[File:Adpd-test-case-1-signals-after-training.png|center|550px|ADPD test case 1, signals after training]]<br />
<br />
RF PA output measurements are shown below.<br />
<br />
====PA output spectrum====<br />
[[File:Adpd-test-case-1-pa-output-spectrum.png|center|550px|ADPD test case 1, PA output spectrum]]<br />
No ADPD – yellow trace. With ADPD – blue trace. <br />
IMD3 and IMD5 distortion components at the PA output reduced by almost 20 dB.<br />
<br />
====ACPR without ADPD====<br />
[[File:Adpd-test-case-1-acpr-without-adpd.png|center|550px|ADPD test case 1, ACPR without ADPD]]<br />
ACPR1 = -34 dBc, ACPR2 = -54 dBc.<br />
<br />
====ACPR with ADPD====<br />
[[File:Adpd-test-case-1-acpr-with-adpd.png|center|550px|ADPD test case 1, ACPR with ADPD]]<br />
ACPR1 = -51 dBc, ACPR2 = -52 dBc.<br />
<br />
====EVM without ADPD====<br />
[[File:Adpd-test-case-1-evm-without-adpd.png|center|550px|ADPD test case 1, EVM without ADPD]]<br />
Measured at 6.58%.<br />
<br />
====EVM with ADPD====<br />
[[File:Adpd-test-case-1-evm-with-adpd.png|center|550px|ADPD test case 1, EVM with ADPD]]<br />
Measured at 3.24%.<br />
<br />
===Test case 2: Class-J GaN HEMPT amplifier===<br />
====ACPR without ADPD====<br />
[[File:Adpd-test-case-2-acpr-without-adpd.png|center|550px|ADPD test case 2, ACPR without ADPD]]<br />
ACPR1 = -43 dBc, ACPR2 = -58dBc.<br />
<br />
====ACPR with ADPD====<br />
[[File:Adpd-test-case-2-acpr-with-adpd.png|center|550px|ADPD test case 2, ACPR with ADPD]]<br />
ACPR1 = -53 dBc, ACPR2 = -58dBc.<br />
<br />
==Conclusion==<br />
The LimeADPD algorithm has been confirmed by measured results. ADPD is capable of cancelling any distortion above system (DACs -> TX -> PA -> Coupler -> Attenuator -> RX -> ADCs) noise floor.<br />
<br />
For [[#Test_case_1:_Maxim_Integrated_MAX2612_PA|test case 1]], at antenna point (PA output) ACPR is improved from -34 dBc (out of spec.) to -51 dBc (well within the spec.) EVM is improved from 6.58% to 3.24%.<br />
<br />
As far as linearisation is concerned, [[#Test_case_2:_Class-J_GaN_HEMPT_amplifier|test case 2]] is more challenging since there are two PA stages (MAX2612 followed by a Class-J GaN HEMPT amplifier) and both stages are nonlinear. Even in this case LimeADPD gives excellent results, i.e. ACPR is improved from -43 dBc (out of spec.) to -53 dBc (well within the spec.)<br />
<br />
==Work underway==<br />
* Test ADPD algorithm with 10W PAs covering different frequency bands.<br />
* Check the performance with more demanding modulation schemes; using 5MHz, 10MHz, 15MHz, and 20MHz LTE as the test signal, for example.<br />
* Modify the algorithm to linearise more than one PA for MIMO applications using single ADPD monitoring path.<br />
* Test the algorithm performance in real applications, i.e. within the base station during voice, video, and data calls.<br />
<br />
==Document version==<br />
Based on Adaptive Digital Predistortion of RF Power Amplifiers Application Note v3r00.<br />
<br />
Changes since document generation:<br />
* Minor typographical and grammatical changes.<br />
<br />
{{LimeMicro}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-2-acpr-with-adpd.png&diff=1064
File:Adpd-test-case-2-acpr-with-adpd.png
2017-06-03T21:55:52Z
<p>Ghalfacree: ADPD test case 2, ACRP with ADPD.</p>
<hr />
<div>ADPD test case 2, ACRP with ADPD.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-2-acpr-without-adpd.png&diff=1063
File:Adpd-test-case-2-acpr-without-adpd.png
2017-06-03T21:55:35Z
<p>Ghalfacree: ADPD test case 2, ACPR without ADPD.</p>
<hr />
<div>ADPD test case 2, ACPR without ADPD.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-1-evm-with-adpd.png&diff=1062
File:Adpd-test-case-1-evm-with-adpd.png
2017-06-03T21:52:18Z
<p>Ghalfacree: ADPD test case 1, EVM with ADPD.</p>
<hr />
<div>ADPD test case 1, EVM with ADPD.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-1-evm-without-adpd.png&diff=1061
File:Adpd-test-case-1-evm-without-adpd.png
2017-06-03T21:51:31Z
<p>Ghalfacree: ADPD test case 1, EVM without ADPD.</p>
<hr />
<div>ADPD test case 1, EVM without ADPD.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-1-acpr-with-adpd.png&diff=1060
File:Adpd-test-case-1-acpr-with-adpd.png
2017-06-03T21:50:10Z
<p>Ghalfacree: ADPD test case 1, ACPR with ADPD.</p>
<hr />
<div>ADPD test case 1, ACPR with ADPD.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-1-acpr-without-adpd.png&diff=1059
File:Adpd-test-case-1-acpr-without-adpd.png
2017-06-03T21:48:24Z
<p>Ghalfacree: ADPD test case 1, ACPR without ADPD.</p>
<hr />
<div>ADPD test case 1, ACPR without ADPD.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-1-pa-output-spectrum.png&diff=1058
File:Adpd-test-case-1-pa-output-spectrum.png
2017-06-03T21:46:46Z
<p>Ghalfacree: ADPD test case 1, PA output spectrum.</p>
<hr />
<div>ADPD test case 1, PA output spectrum.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-1-signals-after-training.png&diff=1057
File:Adpd-test-case-1-signals-after-training.png
2017-06-03T21:44:57Z
<p>Ghalfacree: ADPD test case 1, signals after training.</p>
<hr />
<div>ADPD test case 1, signals after training.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-test-case-1-signals-before-training.png&diff=1056
File:Adpd-test-case-1-signals-before-training.png
2017-06-03T21:42:55Z
<p>Ghalfacree: ADPD test case 1, signals before training.</p>
<hr />
<div>ADPD test case 1, signals before training.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-implementation-on-limesdr-qpcie-board-block-diagram.png&diff=1055
File:Adpd-implementation-on-limesdr-qpcie-board-block-diagram.png
2017-06-03T21:17:11Z
<p>Ghalfacree: An ADPD implementation block diagram, based on the LimeSDR-QPCIe board.</p>
<hr />
<div>An ADPD implementation block diagram, based on the LimeSDR-QPCIe board.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Adpd-indirect-learning-architecture-block-diagram.png&diff=1054
File:Adpd-indirect-learning-architecture-block-diagram.png
2017-06-03T14:30:34Z
<p>Ghalfacree: ADPD indirect learning architecture, block diagram.</p>
<hr />
<div>ADPD indirect learning architecture, block diagram.</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeMicro:LMS7002M_Datasheet&diff=829
LimeMicro:LMS7002M Datasheet
2016-06-03T14:43:37Z
<p>Ghalfacree: /* MCU boot-up and EEPROM programming */</p>
<hr />
<div>==Features summary==<br />
* Field Programmable Radio Frequency (FPRF) chip<br />
* Dual transceiver, ideal for MIMO<br />
* User programmable on-the-fly<br />
* Continuous coverage of the 100 kHz - 3.8 GHz RF frequency range<br />
* Digital interface to baseband with on-chip integrated 12 bit D/A and A/D converters<br />
* Programmable RF modulation bandwidth up to 160 MHz using analog interface<br />
* Programmable RF modulation bandwidth up to 60 MHz using digital interface<br />
* Supports both TDD and full duplex FDD<br />
* LimeLight™ digital IQ interface – JEDEC JESD207 TDD and FDD compliant<br />
* Transceiver Signal Processor block employs advanced techniques for enhanced performance<br />
* Single chip supports 2x2 MIMO. Multiple chips can be used to implement higher order MIMO<br />
* On-chip RF calibration circuitry<br />
* Fully differential baseband signals, analog IQ<br />
* Few external components<br />
* Low voltage operation, 1.25 V, 1.4 V, and 1.8 V. Integrated LDOs to run on a single 1.8 V supply voltage<br />
* On-chip integrated microcontroller for simplified calibration, tuning and control<br />
* Integrated clock PLL for flexible clock generation and distribution<br />
* User definable analogue and digital filters for customised filtering<br />
* RF and baseband Received Signal Strength Indicator (RSSI)<br />
* 261-pin aQFN 11.5x11.5 mm package<br />
* Power-down option<br />
* Serial port interface<br />
* Low power consumption, typically 880 mW in full 2x2 MIMO mode (550 mW in SISO mode) using external LDOs<br />
* Multiple bypass modes for greater flexibility<br />
<br />
==Applications==<br />
* Broadband wireless communications <br />
* GSM, CDMA2000, TD-SCDMA, WCDMA/HSPA, LTE<br />
* IEEE® xxx.xxx radios<br />
* Wi-Fi operating in the Whitespace frequencies<br />
* Software Defined Radio (SDR)<br />
* Cognitive Radio<br />
* Unmanned Aerial Vehicle (UAV)<br />
* Other Whitespace applications<br />
<br />
==Functional block diagram==<br />
[[File:Lms7002m-functional-block-diagram.png|center|550px|LMS7002M functional block diagram]]<br />
<br />
==General description==<br />
The LMS7002M is a fully-integrated, multi-band, multi-standard RF transceiver that is highly programmable. It combines Low Noise Amplifiers (RXLNA), TX Power Amplifier Drivers (TXPAD) receiver/transmitter (RX/TX) mixers, RX/TX filters, synthesisers, RX gain control, TX power control, analogue-to-digital and digital-to-analogue converters (ADC/DACs) and has been designed to require very few external components.<br />
<br />
The top level architecture of LMS7002M transceiver is shown in the [[#Functional_block_diagram|functional block diagram]]. The chip contains two transmit and two receive chains for achieving a Multiple In Multiple Out (MIMO) platform. Both transmitters share one PLL and both receivers share another. Transmit and receive chains are all implemented as Zero Intermediate Frequency (Zero IF or ZIF) architectures providing up to 160MHz RF modulation bandwidth (equivalent to 80MHz baseband IQ bandwidth). For the purpose of simplifying this document, the explanation for the functionality and performance of the chip is based on one transmit and one receive circuitry, given that the other two work in exact the same manner.<br />
<br />
On the transmit side, In-phase and Quadrature IQ DAC data samples from the base band processor are provided to the LMS7002M via the LimeLight™ digital IQ interface. LimeLight™ implements the JESD207 standard IQ interface protocol as well as de facto IQ multiplexed standard. JESD207 is Double Data Rate (DDR) by definition. In IQ multiplexed mode LimeLight™ also supports Single Data Rate (SDR). The IQ samples are then preprocessed by the digital Transceiver Signal Processor (TSP) for minimum analogue and RF distortion and applied to the on-chip transmit DACs. The DACs generate analogue IQ signals which are provided for further processing to the analogue/RF section. Transmit low-pass filters (TXLPF) remove the images generated by zero-hold effect of the DACs as well as the DAC out-of-band noise. The analogue IQ signals are then mixed with the transmit PLL (TXPLL) output to produce a modulated RF signal. This RF signal is then amplified by one of two separate, selectable power amplifier drivers and two open-drain differential outputs are provided as RF output for each MIMO path.<br />
<br />
The LMS7002M provides an RF loopback option which enables the TX RF signal to be fed back into the baseband for calibration and test purposes. The RF loopback signal is amplified by the loopback amplifier in order to increase the dynamic range of the loop.<br />
<br />
There are two additional loopback options implemented: one is an analogue baseband (BB) loopback; the other is a digital loopback (DLB). The analogue loop back is intended for testing while the DLB can be used to verify the LMS7002M connectivity to baseband, FPGA, DSP, or any other digital circuitry.<br />
<br />
On the receive side three separate inputs are provided, each with a dedicated LNA optimised for narrow or wideband operation. Each port RF signal is first amplified by a programmable low-noise amplifier (RXLNA). The RF signal is then mixed with the receive PLL (RXPLL) output to directly down-convert to baseband. AGC steps can be implemented by a BB trans-impedance amplifier (RXTIA) prior to the programmable bandwidth low pass channel select/antialias filters (RXLPF). The received IQ signal is further amplified by a programmable gain amplifier (RXPGA). DC offset is applied at the input of RXTIA to prevent saturation and to preserve the receive ADC’s dynamic range. The resulting analogue receive IQ signals are converted into the digital domain with on-chip receive ADCs. Following the ADCs, the signal conditioning is performed by the digital Transceiver Signal Processor (TSP) and the resulting signals are then provided to the BB via the LimeLight™ digital IQ interface.<br />
<br />
The analog receive signals can also be provided off-chip at the RXOUTI and RXOUTQ pins by closing the RXOUT switch. In this case it is possible to power down the on chip ADCs/TSP and use external parts, which can be very useful for more resource-demanding applications or where higher signal resolution is required. A similar option is also available on the TX side where the analogue signal can be processed by external components: the on-chip DACs/TSP can be powered down and analogue inputs can be provided at TXINI and TXINQ pins.<br />
<br />
==General specifications==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Operating temperature range || -40 || 25 || 85 || °C || <br />
|-<br />
|Storage temperature range || -65 || 25 || 125 || °C || <br />
|-<br />
|Operating frequency range || 30<br />0.1 || || 3800<br />3800 || MHz || <br />Extended by TSP NCOs<br />
|-<br />
|RF modulation bandwidth || || || 60<br />160 || MHZ || Through digital interface<br />Through analogue interface<br />
|-<br />
|Frequency resolution || || || 24.8 || Hz || Using 52MHZ PLL reference clock<br />
|-<br />
|Analogue supply voltage, high (VDDAH) || 1.71 || 1.8 || 1.89 || V || Used for TXPAD<br />
|-<br />
|Analogue supply voltage, medium (VDDAM) || 1.33 || 1.4 || 1.47 || V || Generated using integrated low-dropout regulators (LDOs)<br />
|-<br />
|Analogue supply voltage, low (VDDAL) || 1.2 || 1.25 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Digital core supply voltage || 1.1 || 1.2 || 1.3 || V || <br />
|-<br />
|TX supply current || || 350 || || mA || At -7 dBm output power, 2x2 MIMO, including the DACs and TSP<br />
|-<br />
|RX supply current || || 420 || || mA || For 2x2 MIMO, including the ADCs and TSP<br />
|-<br />
|Maximum RF output power || || 0 || || dBm || Continuous wave<br />
|-<br />
|PLL reference clock || 10 || || 52 || MHz ||<br />
|-<br />
|Interpolation/decimation digital filters stop band suppression || || || 108 || dB || <br />
|}<br />
<br />
==General RF specifications==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|RF channel frequency range || 30<br />0.1 || || 3800<br />3800 || MHz || <br />Extended by TSP NCOs<br />
|-<br />
|Transmit analogue input impedance || || 400 || || Ohms || Differential, programmable<br />
|-<br />
|Transmit load impedance at the output pins || || 40 || || Ohms || Differential, for maximum OIP3<br />
|-<br />
|Transmit differential I and Q input current || || 625 || || μA || Differential, common mode<br />
|-<br />
|Transmit gain control range || || 70 || || dB || TXTSP and TXPAD combined<br />
|-<br />
|Transmit gain control step || || 1 || || dB || <br />
|-<br />
|TX local oscillator (LO) leakage || || -60 || || dBc || Calibrated<br />
|-<br />
|RXLNAL frequency range || 0.1 || || 2000 || MHz || Narrowband tunable, set by external matching circuit<br />
|-<br />
|RXLNAH frequency range || 0.1 || || 3800 || MHz || Narrowband tunable, set by external matching circuit<br />
|-<br />
|RXLNAW frequency range || 0.1 || || 3800 || MHz || Broadband tunable, set by external matching circuit<br />
|-<br />
|Noise figure || || 2.0<br />2.5<br />3.5 || || dB || at 0.95GHz<br />at 2GHz<br />at 3.8GHz<br />
|-<br />
|2nd order input intercept point || || 50 || || dBm || Total receiver gain ~50 dB or more. Noise figure <3.5 dB in all bands. Two tone signals out of band.<br />
|-<br />
|3rd order input intercept point || || 4 || || dBM || Total receiver gain ~50 dB or more. Noise figure <3.5 dB in all bands. Two tone signals out of band.<br />
|-<br />
|Receive gain control range || || 70 || || dB || RXLNA, RXTIA, RXPGA, and RXTSP combined<br />
|-<br />
|Receive gain control step || 0.5 || 1 || 1.5 || dB || <br />
|}<br />
<br />
Two transmitter outputs (TXOUT1, TXOUT2) and three receiver inputs (RXINL, RXINH, RXINW) are provided to facilitate multi-band multi-standard operation. <br />
The functionality of the LMS7002M is fully controlled by a set of internal registers which can be accessed through a serial port and rapidly reprogrammed on the fly for advanced system architectures. In order to enable full duplex operation, LMS7002M contains two separate synthesisers (TXPLL, RXPLL), both usually driven from the same reference clock source PLLCLK.<br />
<br />
==Gain control==<br />
===TX gain control===<br />
[[File:Lms7002m-analogue-gain-control-architecture.png|center|550px|LMS7002M analogue/RF gain control architecture diagram.]]<br />
<br />
The LMS7002M transmitter has two programmable gain stages, where the TSP provides digital gain control and the TXPAD gives programmable gain of the RF signal.<br />
<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Digital TSP gain control range || || 15 || || dB || In steps of 1 LSB digital gain control<br />
|-<br />
|TXPAD gain control range || || 55 || || dB ||<br />
|-<br />
|TXPAD gain step size || || 1 || || dB || For the higher 10 steps<br />
|-<br />
|TXPAD gain step size || || 2 || || dB || For the lower 20 steps<br />
|}<br />
<br />
===RX gain control===<br />
[[File:Lms7002m-rx-gain-control-architecture.png|center|550px|LMS7002M RX gain control architecture diagram.]]<br />
<br />
The LMS7002M receiver has three gain control elements, RXLNA, RXTIA, and RXPGA. If required, additional gain control can be implemented by RXTSP in digital domain. RXLNA gain control consists of 30 dB with 1 dB steps at high gain settings and 3 dB steps at low gain settings for AGC when large adjacent channel blockers are present and a reduction in system noise figure (NF) is acceptable. RXTIA offers 3 dB of control range. RXTIA is intended for AGC steps needed to reduce system gain prior to the channel filters when large in band blockers are present. This gain can be under the control of the baseband or fixed on calibration. RXPGA provides gain control for the AGC if a constant RX signal level at the ADC input is required. It has a 32 dB gain range control in 1 dB steps.<br />
<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Digital TSP gain control range || || 15 || || dB || In steps of 1 LSB digital gain control<br />
|-<br />
|RXLNA gain control range || || 30 || || dB || 1 and 3 dB steps<br />
|-<br />
|RXTIA gain control range || || 3 || || dB || <br />
|-<br />
|RXPGA gain control range || || 32 || || dB || <br />
|-<br />
|RXPGA gain step size || || 1 || || dB || <br />
|}<br />
<br />
==Synthesisers==<br />
The LMS7002M has two low phase noise synthesisers to enable full-duplex operation, and both are capable of output frequencies up to 3.8 GHz. Each synthesiser uses a fractional-N PLL architecture. The same reference frequency can be used for both synthesisers and is flexible between 10 to 52 MHz clock frequency. The synthesisers produce complex outputs with levels suitable to drive IQ mixers in both the TX and the RX paths. The transmit PLL could also be routed via switches to the receive PLL so as to offer phase-coherent operation in TDD mode.<br />
<br />
===PLL reference clock===<br />
[[File:Lms7002m-pll-architecture.png|center|550px|LMS7002M PLL architecture diagram.]]<br />
The LMS7002M can accept clipped sine as well as CMOS level signals for the PLL reference clock. Both DC and AC coupling are supported as shown in Figure 5. Internal buffer self-biasing must be enabled for AC coupling mode. The PLL reference clock input can also be low voltage CMOS (<1.2V) which is implemented by lowering the clock buffer supply. <br />
<br />
====DC coupled====<br />
[[File:Lms7002m-pll-reference-clock-input-buffer-dc-coupled.png|center|550px|LMS7002M PLL reference clock input buffer, DC coupled.]]<br />
<br />
====AC coupled====<br />
[[File:Lms7002m-pll-reference-clock-input-buffer-ac-coupled.png|center|550px|LMS7002M PLL reference clock input buffer, AC coupled.]]<br />
<br />
===Synthesiser specifications===<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Output frequency range || 30 || || 3800 || MHz || <br />
|-<br />
|Reference amplitude || 0.2 || 0.8 || 2.5 || Vpp || At PVDD >2.5 V<br />
|-<br />
|Reference frequency || 10 || || 52 || MHz || For continuous LO frequency range<br />
|-<br />
|Frequency resolution || || || 2.4 || Hz || Using 52 MHz PLL reference clock<br />
|-<br />
|850 MHz Phase Noise<br />1 kHz offset<br />5 kHz offset<br />10 kHz offset<br />100 kHz offset<br />1 MHz offset<br />30 MHz offset || || <br />-96<br />-97<br />-99<br />-107<br />-131<br />-158 || || dBc/Hz || <br />
|-<br />
|2.0 GHz Phase Noise<br />1 kHz offset<br />5 kHz offset<br />10 kHz offset<br />100 kHz offset<br />1 MHz offset<br />30 MHz offset || || <br />-91<br />-92<br />-92<br />-102<br />-127<br />-158 || || dBc/Hz || <br />
|-<br />
|2.7 GHz Phase Noise<br />1 kHz offset<br />5 kHz offset<br />10 kHz offset<br />100 kHz offset<br />1 MHz offset<br />30 MHz offset || || <br />-87<br />-88<br />-92<br />-98<br />-123<br />-158 || || dBc/Hz || <br />
|-<br />
|3.5 GHz Phase Noise<br />1 kHz offset<br />5 kHz offset<br />10 kHz offset<br />100 kHz offset<br />1 MHz offset<br />30 MHz offset || || <br />-84<br />-85<br />-86<br />-89<br />-113<br />-152 || || dBc/Hz || <br />
|- <br />
|Reference spurious outputs || || -70 || -68 || dBc || <br />
|-<br />
|Other spurious outputs || || -60 || -55 || dBc || <br />
|-<br />
|850 MHz IQ phase error || || 0.8 || 1 || degrees || rowspan="4"|After calibration<br />
|-<br />
|2000 MHz IQ phase error || || 2 || || degrees<br />
|-<br />
|3500 MHz IQ phase error || || 3 || || degrees<br />
|-<br />
|IQ amplitude error || || ±0.1 || ±0.2 || dB<br />
|-<br />
|PLL setting time || || 50 || 150 || μS || Loop BW=70 kHz<br />
|}<br />
<br />
==RF ports==<br />
The LMS7002M has two transmitter outputs and three receiver inputs for each of the dual transceivers. The optimum transmitter output load is 40 Ω differential at the output pads. The final stage amplifiers are open drain and require +1.8V voltage supply. The receiver inputs are common-source with different inductive degeneration, optimised for different frequency bands. They need to be externally matched for optimised narrowband performance or broadband utilising a wideband transformer.<br />
<br />
==TX and RX low-pass filters==<br />
The LMS7002M integrates selective low-pass filters in both the TX and RX paths. These filters have a programmable pass band in order to provide more flexibility on the DAC/ADC clock frequency and also to provide adjacent channel rejection in the receive chain. The complete filtering function is a combination of analogue filtering and digital TSP filtering. RX analogue filters are tunable from 0.7 MHz to 80 MHz. The digital filters provide a lower pass band of 0.7 MHz. Using such mixed mode filtering (digital and analogue) provides 60 dB antialias performance and 40 dB adjacent channel rejection as the worst case scenario. The TX filtering chain pass band is tunable from 2 MHz to 80 MHz. When combined with TX digital filters the chain offers enhanced performance in a similar way to the RX analogue/digital filtering chain.<br />
<br />
===TX analogue filter chain===<br />
[[File:Lms7002m-tx-analogue-filter-chain.png|center|550px|LMS7002M TX analogue filter chain]]<br />
<br />
The transmitter baseband has three independently controlled low pass filter stages:<br />
# 4th order ladder filter (TXLPFLAD)<br />
# 1st order real pole filter (TXLPFS5)<br />
# 2nd order high-band filter (TXLPFH)<br />
<br />
The low-band filter (TXLPFL) path pass band is tunable from 2 MHz to 20 MHz and is comprised of two filter stages: 4th order low pass ladder filter (TXLPFLAD) and 1st order low pass real pole filter (TXLPFS5). The real pole stage filters the BB noise at the duplex frequency to meet the far-end noise specifications in some FDD systems. The high-band filter (TXLPFH) pass band is tunable from 20 MHz up to 80 MHz and is comprised of a single 2nd order low pass stage. Only one path (TXLPFL or TXLPH) can be active at the same time.<br />
<br />
===RX analogue filter chain===<br />
[[File:Lms7002m-rx-analogue-filter-chain.png|center|550px|LMS7002M RX analogue filter chain]]<br />
<br />
The receiver baseband has three independently controlled low pass filter stages:<br />
# 1st order single pole filter (RXTIA)<br />
# 2nd order low band filter (RXLPFL)<br />
# 2nd order high band filter (RXLPFH)<br />
<br />
The initial filtering is done by the transimpedance amplifier (RXTIA), which acts as a single-pole low-pass filter. The RXTIA output is routed to one of two filter stages. Low band filter pass band is tunable from 0.75 MHz up to 20 MHz. High band filter pass band is tunable from 20 MHz up to 80 MHz. Both low band and high band stages are 2nd order low pass filters. Paired with the RXTIA, these stages produce a 3rd order low pass filter response. Only one path (RXLPFL or RXLPH) can be active at the same time.<br />
<br />
===Analogue TX LPFH amplitude response===<br />
[[File:Lms7002m-analogue-tx-lpfh-amplitude.png|center|550px|LMS7002M analogue TX LPFH amplitude graph]]<br />
<br />
===Analogue TX LPFL amplitude response===<br />
[[File:Lms7002m-analogue-tx-lpfl-amplitude.png|center|550px|LMS7002M analogue TX LPFL amplitude graph]]<br />
<br />
===Analogue RX LPFH amplitude response===<br />
[[File:Lms7002m-analogue-rx-lpfh-amplitude.png|center|550px|LMS7002M analogue RX LPFH amplitude graph]]<br />
<br />
===Analogue RX LPFL amplitude response===<br />
[[File:Lms7002m-analogue-rx-lpfl-amplitude.png|center|550px|LMS7002M analogue RX LPFH amplitude graph]]<br />
<br />
==Transceiver signal processor==<br />
[[File:Lms7002m-tsp.png|center|550px|LMS7002M Transceiver Signal Processor (TSP) block diagram]]<br />
<br />
The LMS7002M includes a high digital gate count within the Transceiver Signal Processor (TSP) block. The function of the TSP is to employ advanced digital signal processing techniques to enhance the performance of the analogue/RF parts. This results in improved performance of the overall system and a saving on total current consumption. The TSP is placed between the data converters and the LimeLight™ digital IQ interface. Functionally, the [[#RXTSP structure|RX]] and [[#TXTSP structure|TX]] parts of the TSP are similar<br />
<br />
In both the TX and RX TSP blocks there are three general-purpose finite impulse response (FIR) filters, G.P. FIR 1, G.P. FIR 2, and G.P. FIR 3. The filter coefficients are fully programmable and the implementation does not force their impulse response to be symmetrical.<br />
<br />
On the TX side one of these filters could be used as a phase equaliser, which is a requirement in some communication standards such as CDMA2000. Another can be used to flatten the amplitude response of the TXLPF, while the third FIR could be used to further enhance the channel filtering function of the BB modem. If phase equalisation is not required then one filter can be used to minimise group delay variation of the analog TXLPF. Possible applications of the G.P. FIR filters on the RX side are similar. One could be used to minimise group delay variation of the analogue RXLPF while another could help to improve RXLPF adjacent channel rejection performance.<br />
<br />
The interpolation block within the TXTSP takes IQ data from the BB modem and increases the data sample rate. The advantages of having interpolation are as follows: for narrow band systems (GSM/EDGE) or even moderately broad band (WCDMA, CDMA2000) modulation standards the BB modem does not need to interpolate IQ data to the target system clock. The base band can provide output data at a much lower sample rate saving on power at the digital interface. Having a low data rate interface also simplifies the PCB design. However, the interpolator block generates data samples at the system clock rate, so the DACs run at a high sampling rate. As the DACs are running at a high frequency, it means that the quantisation noise is spread over a wider frequency range which results in a better overall SNR. Also, the image generated by the DAC zero hold effect is further away from the wanted signal hence the specification for the TXLPF can be relaxed.<br />
<br />
The reason for having decimation in the RXTSP is similar to that of interpolation in TXTSP. The ADCs can run at high frequency, and the specification of the RXLPF used as an anti-alias filter in this case is relaxed, the G.P. FIR improves adjacent channel rejection and the decimation circuit reduces the received data sample rate before sending the data to the BB modem.<br />
<br />
The two Numerically Controlled Oscillators (NCO) and digital complex mixer (CMIX) in the TXTSP and RXTSP paths enable the LMS7002M to run in low digital IF.<br />
<br />
Inverse sinc filters (INVSINC) within the TXTSP chain compensate for sinx/x amplitude roll off imposed by the DACs themselves.<br />
<br />
The Tx DC Corr block is used to cancel residual DC offset of TXLPF. It is also used to cancel TX LO leakage feed-through as mentioned earlier.<br />
<br />
There are three sources of the DC component at the RX output. These are the residual DC offset of the RXPGA and RXLPF, RX LO leakage feed-through and second order distortion (IP2). The Rx DC Corr blocks compensate for all of these sources of offset. The block is implemented as a real time tracking loop so any change of the RX DC due to either the signal level change, or due to RX gain change as well as any temperature effect will be tracked and cancelled automatically.<br />
<br />
The IQ Gain Corr and IQ Phase Corr blocks correct IQ imbalance in both TXTSP and RXTSP in order to minimise the level of unwanted sideband (image) component.<br />
<br />
The last stage in the RXTSP path is a digital implementation of an Adaptive Gain Control (AGC) loop. Assuming that the BB modem does not require 12-bit full scale ADC outputs, the digital AGC block can provide a certain level of automatic gain control before the BB involves RF and IF gain stages.<br />
<br />
===RXTSP structure===<br />
[[File:Lms7002m-tsp-rx.png|center|550px|LMS7002M RXTSP structure diagram]]<br />
<br />
===TXTSP structure===<br />
[[File:Lms7002m-tsp-tx.png|center|550px|LMS7002M TXTSP structure diagram]]<br />
<br />
===IQ gain correction===<br />
[[File:Lms7002m-tsp-iq-gain-correction.png|center|550px|LMS7002M IQ gain correction diagram]]<br />
This block implements the following equation:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{Iout} = \mathit{Iin} * \mathit{G\_I} \\<br />
\mathit{Qout} = \mathit{Qin} * \mathit{G\_Q}<br />
\end{align}<br />
</math><br />
<br />
<math>\mathit{G\_I}</math> and <math>\mathit{G\_Q}</math> are programmable correction factors which are altered by the BB modem to minimise any unwanted sideband component. The BB modem can combine IQ gain correction and digital gain control using the same module by calculating <math>\mathit{G\_I}</math> and <math>\mathit{G\_Q}</math> in the following way:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{G\_I} = \mathit{G\_I\_corr} * \mathit{G\_digi}\\<br />
\mathit{G\_Q} = \mathit{G\_Q\_corr} * \mathit{G\_digi}<br />
\end{align}<br />
</math><br />
<br />
where <math>\mathit{G\_I\_corr}</math> and <math>\mathit{G\_Q\_corr}</math> are IQ gain correction factors and <math>\mathit{G\_digi}</math> is the desired digital gain.<br />
<br />
===IQ phase correction===<br />
[[File:Lms7002m-tsp-iq-phase-correction.png|center|550px|LMS7002M IQ phase correction diagram]]<br />
<br />
IQ phase correction is in fact equivalent to vector rotation. If the quadrature phase error is <math>\alpha</math> then the I and Q vectors are both rotated by <math>\alpha/2</math> but in opposite directions, hence IQ outputs of the corrector circuit are 90&deg; phase shifted. IQ phase correction equations are given below:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{Iout} = \mathit{Iin} + \mathit{Qin} * \tan \biggl( {\alpha \over 2} \biggr) \\<br />
\mathit{Qout} = \mathit{Qin} + \mathit{Iin} * \tan \biggl( {\alpha \over 2} \biggr)<br />
\end{align}<br />
</math><br />
<br />
The value of <math>\tan(\alpha/2)</math> should be stored in the configuration register as a programmable correction parameter. The BB modem should adjust this value to minimise the unwanted side band component. The BB modem can also use the following approximation formula:<br />
<br />
<math><br />
\begin{align}<br />
\tan \biggl( {\alpha \over 2} \biggr) \approx {\alpha \over 2}<br />
\end{align}<br />
</math><br />
<br />
when <math>\alpha</math> is small, which is usually the case. The IQ phase corrector of the LMS7002M is designed to correct an IQ phase error up to ±20&deg;.<br />
<br />
===TX DC correction===<br />
[[File:Lms7002m-tsp-dc-offset.png|center|550px|LMS7002M DC offset diagram]]<br />
<br />
DC offset correction in the TXTSP path is achieved by using the following equation:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{Iout} = \mathit{Iin} + \mathit{DC_I} \\<br />
\mathit{Qout} = \mathit{Qin} + \mathit{DC_Q}<br />
\end{align}<br />
</math><br />
<br />
Here <math>\mathit{DC_I}</math> and <math>\mathit{DC_Q}</math> are programmable DC offset correction parameters which the BB modem should adjust to minimise the TX DC and TX LO leakage feed-through.<br />
<br />
===RX DC correction===<br />
[[File:Lms7002m-tsp-rx-dc-correction.png|center|550px|LMS7002M RX DC correction diagram]]<br />
<br />
As mentioned previously, there are multiple reasons for DC to appear at the RX output. The most difficult to correct, in a static manner, is the second order distortion (IP2) component which changes with the RX input level as well as the RX gain set up. A compensation loop running in real time is required to track and correct the DC at the RX output. A simple digital implementation of such a loop is given above.<br />
<br />
The averaging (COMB) filter calculates the DC of the corrector input and subtracts it to cancel out the offset. The loop is running all the time so any change of the RX DC due to the signal level change, RX gain change, or temperature will be tracked and cancelled automatically. The only programmable parameter in the loop is DCAVG which defines the averaging window size.<br />
<br />
===Inverse SINC filter===<br />
The inverse sinc filter compensates for sinx/x amplitude roll off imposed by the DAC. The filter is designed to compensate from DC to 0.35fs where fs is the DAC sampling frequency. Impulse and amplitude responses are shown in Figure 19 and Figure 20.a respectively. Figure 20.b plots the equivalent DAC amplitude response with the inverse sinc function compensation applied. The in band (0 – 0.35fs ) amplitude ripple is less than +/- 0.04 dB.<br />
<br />
====INVSINC impulse response====<br />
<nowiki>h( 0) = 0.0101318 = h( 4)<br />
h( 1) = -0.0616455 = h( 3)<br />
h( 2) = 0.855469</nowiki><br />
<br />
====INVSINC (a) and equivalent DAC (b) amplitude response====<br />
[[File:Lms7002m-tsp-invsinc-dac-amplitude.png|center|550px|LMS7002M INVSINC (a) and corresponding DAC (b) amplitude response graph]]<br />
<br />
===Complex mixer===<br />
The complex mixer used in the RXTSP and TXTSP is designed to implement the following set of equations:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{Iout} = \mathit{Iin} \cos \omega _{\mathit{c}} \mathit{t} \mp \mathit{Qin} \sin \omega_{\mathit{c}} \mathit{t} \\<br />
\mathit{Qout} = \mathit{Iin} \sin \omega _{\mathit{c}} \mathit{t} + \mathit{Qin} \cos \omega_{\mathit{c}} \mathit{t}<br />
\end{align}<br />
</math><br />
<br />
where <math>\mathit{Iin}</math> and <math>\mathit{Qin}</math> are provided from the IQ pre-processing stages while cosine and sine signals are generated by the NCO. An option to choose the sign in the mixing equations is implemented which gives the ability to do up-mixing or down-mixing in both TX and RX chains.<br />
<br />
===Numerically-controlled oscillator===<br />
[[File:Lms7002m-tsp-nco-architecture.png|center|550px|LMS7002M NCO architecture diagram]]<br />
<br />
The quadrature carrier signal, required to implement low digital IF, is generated by the local NCO. The internal NCO design is based on a Direct Digital Frequency Synthesis (DDFS) algorithm with a 32-bit phase accumulator with 19-bit phase precision and provides 14-bit digital sine and cosine waveforms with spurious performance better than –114 dBc.<br />
<br />
The carrier frequency<math>\mathit{f_c}</math> generated by the NCO is defined using the following formula:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{f_c} = {\mathit{fcw} \over 2^{32}} \mathit{f_{clk}}<br />
\end{align}<br />
</math><br />
<br />
where <math>\mathit{fcw}</math> represents the decimal value of the 32-bit frequency control word and <math>\mathit{f_{clk}}</math> is the NCO clock frequency.<br />
<br />
Carrier phase offset can also be adjusted using the 16-bit configuration parameter <math>\mathit{pho}</math>. The carrier phase shift is calculated as follows:<br />
<br />
<math><br />
\begin{align}<br />
\phi = 2 \pi {\mathit{pho} \over 2^{16}}<br />
\end{align}<br />
</math><br />
<br />
with <math>\mathit{pho}</math> being the decimal value stored in the carrier phase offset register.<br />
<br />
Both frequency control and phase control words are easily accessible via SPI, therefore NCOs can be modulated by direct symbol insertion. Up to 16FSK or 16PSK modulations are supported.<br />
<br />
===Interpolation===<br />
[[File:Lms7002m-tsp-interpolation-filters.png|center|550px|LMS7002M interpolation filters diagram]]<br />
<br />
Interpolation within the TXTSP channel is implemented using the chain of five fixed coefficients half band FIR filters. Each sub-filter in the chain interpolates by two. The interpolation ratio of the overall filter is set by selecting one of the sub-filter outputs and adjusting the clock rates accordingly. Hence, the interpolation ratio <math>\mathit{K}</math> can be programmed to be:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{K} = 1, 2, 4, 8, 16, \mathrm{or}\ 32<br />
\end{align}<br />
</math><br />
<br />
Interpolation by 1 is achieved by bypassing all the interpolation filters. The filters are designed to provide a wide signal pass band from DC to <math>\mathit{f_p}</math> where:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{f_p} = x \cdot {\mathit{f_{clk}} \over \mathit{K}}<br />
\end{align}<br />
</math><br />
<br />
Scaling factor <math>x</math> in the equation above, for <math>\mathit{K}</math> = 2, 4, 8, 16, or 32, should be set to one of the following values:<br />
<br />
: <math>x</math> <= 0.27 for >= 108dB interpolation image suppression<br />
: <math>x</math> <= 0.30 for >= 75dB interpolation image suppression<br />
: <math>x</math> <= 0.32 for >= 60dB interpolation image suppression<br />
<br />
<math>x</math> can be used to trade off interpolation image suppression for the interpolation filter pass band.<br />
<br />
For <math>\mathit{K}=1</math>, <math>x</math> should be set to <math>x < 0.5</math> to limit the signal BW below the Nyquist limit, making room for analogue TX filters to operate. There is no interpolation image in this case hence more flexibility to set <math>x</math> for higher IF/RF bandwidth.<br />
<br />
Only two different configurations are used within the filtering chain of the NCO implementation: HB1 and HB2. The [[#HB1_impulse_response|impulse]] and [[#HB1_amplitude_response|amplitude response]] of HB1 are provided below. The remaining three filters (HB2A, HB2B and HB2C) are all the same with their [[#HB2_impulse_response|coefficients]] and [[#HB2_amplitude_response|amplitude response]] also given below. The overall interpolator can provide image suppression of better than –108 dB with negligible amplitude distortion (pass band ripple less than 10<sup>-5</sup> dB).<br />
<br />
====HB1 impulse response====<br />
<nowiki>h( 0) = -4.673e-05 = h(30)<br />
h( 1) = 0 = h(29)<br />
h( 2) = 0.000392914 = h(28)<br />
h( 3) = 0 = h(27)<br />
h( 4) = -0.00181007 = h(26)<br />
h( 5) = 0 = h(25)<br />
h( 6) = 0.00600147 = h(24)<br />
h( 7) = 0 = h(23)<br />
h( 8) = -0.0160789 = h(22)<br />
h( 9) = 0 = h(21)<br />
h(10) = 0.0378866 = h(20)<br />
h(11) = 0 = h(19)<br />
h(12) = -0.0882454 = h(18)<br />
h(13) = 0 = h(17)<br />
h(14) = 0.3119 = h(16)<br />
h(15) = 0.5</nowiki><br />
<br />
====HB1 amplitude response====<br />
[[File:Lms7002m-tsp-hb1-amplitude-response.png|center|550px|LMS7002M HB1 amplitude response graph]]<br />
<br />
====HB2 impulse response====<br />
<nowiki>h( 0) = -0.00164032 = h(14)<br />
h( 1) = 0 = h(13)<br />
h( 2) = 0.0138855 = h(12)<br />
h( 3) = 0 = h(11)<br />
h( 4) = -0.0630875 = h(10)<br />
h( 5) = 0 = h( 9)<br />
h( 6) = 0.300842 = h( 8)<br />
h( 7) = 0.5</nowiki><br />
<br />
<br />
====HB2 amplitude response====<br />
[[File:Lms7002m-tsp-hb2-amplitude-response.png|center|550px|LMS7002M HB2 amplitude response graph]]<br />
<br />
===Decimation===<br />
[[File:Lms7002m-tsp-decimation-filters.png|center|550px|LMS7002M decimation filter chain diagram]]<br />
<br />
The decimation function is implemented using the same filters as in the case for interpolation although the hardware is simplified slightly by taking advantage of only having to provide every second sample at the sub-filters output. Decimation ratio <math>\mathit{K}</math> can be programmed to be:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{K} = 1, 2, 4, 8, 16, \mathrm{or}\ 32<br />
\end{align}<br />
</math><br />
<br />
Decimation by 1 is achieved by bypassing all the decimation filters. Decimator performance is the same as the performance of the interpolator i.e. pass band is:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{f_p} = x \cdot {\mathit{f_{clk}} \over \mathit{K}}<br />
\end{align}<br />
</math><br />
<br />
As before, scaling factor <math>x</math> in the equation above, for <math>\mathit{K}</math> = 2, 4, 8, 16, or 32, should be set to one of the following values:<br />
<br />
: <math>x</math> <= 0.27 for >= 108dB decimation alias suppression<br />
: <math>x</math> <= 0.30 for >= 75dB decimation alias suppression<br />
: <math>x</math> <= 0.32 for >= 60dB decimation alias suppression<br />
<br />
Again, <math>x</math> can be used to trade off decimation alias suppression for the decimation filter pass band.<br />
<br />
For <math>\mathit{K}=1</math>, <math>x</math> should be set to <math>x < 0.5</math> to limit the signal BW below the Nyquist limit, making room for additional filtering in BB, if required. There is no decimation alias in this case hence more flexibility to set <math>x</math> for higher IF/RF bandwidth.<br />
<br />
===General-purpose FIR filters===<br />
[[File:Lms7002m-tsp-fir-memory-banks.png|center|550px|LMS7002M FIR memory bank diagram]]<br />
<br />
The LMS7002M features general-purpose filters 1 and 2, which are based on a Multiply and Accumulate (MAC) FIR architecture. They can implement up to a 40-tap filtering function and the coefficients are fully programmable via SPI. The hardware implementation does not impose the constraint for the filter impulse response to be symmetrical hence the filter phase response can but does not need to be ideally linear. Therefore it can be used in general filtering as well as nonlinear applications which can be used to implement phase equalisation.<br />
<br />
The filter coefficients are stored in five 8x16-bit internal memory banks as two’s complement signed integers, where <math>\mathit{L}</math> is related to the filter length <math>\mathit{N}</math> as follows:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{L} = \left[ {\mathit{N} \over 5} \right]<br />
\end{align}<br />
</math><br />
<br />
Grey locations in the above memory bank diagram highlight the memory registers which are set to zero for <math>5 \mathit{L} > \mathit{N}</math>. Evidently, the number of the filter taps <math>\mathit{N}</math> is limited by the size of the coefficients memory to:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{N} \le 5 * 8 = 40<br />
\end{align}<br />
</math><br />
<br />
The following relationship should be satisfied:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{L} \le \mathit{K}<br />
\end{align}<br />
</math><br />
<br />
<math>\mathit{K}</math> being the interpolation or decimation ratio, for the MAC hardware to be able to produce output samples on time.<br />
<br />
General purpose FIR filter 3 hardware is composed of three filters (each equivalent to G.P. FIR 1 or 2) running in parallel in order to increase its processing power, hence it can implement the filters with:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{N} \le 3 * 40 = 120<br />
\end{align}<br />
</math><br />
<br />
It can be used as a channel select filter or for any other purpose which requires a larger number of filtering taps.<br />
<br />
===Received signal strength indicators===<br />
A digital received signal strength indicator (RSSI) circuit calculates the level of the received complex signal (<math>\mathit{I} + \mathrm{j}\mathit{Q}</math>) as follows:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{RSSI} = \sqrt{\mathit{I}^2 + \mathit{Q}^2}<br />
\end{align}<br />
</math><br />
<br />
The following approximation of the square root is implemented in the chip:<br />
<br />
<math><br />
\begin{align}<br />
\sqrt{a^2 + b^2} \approx \mathrm{max} \left( \left( \left( \mathit{M} - 0.125 \mathit{M} \right) + 0.5 \mathit{N} \right) , \mathit{M} \right)<br />
\end{align}<br />
</math><br />
<br />
where:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{M} = \mathrm{max} \left( \vert a \vert , \vert b \vert \right) \\<br />
\mathit{N} = \mathrm{min} \left( \vert a \vert , \vert b \vert \right)<br />
\end{align}<br />
</math><br />
<br />
The same RSSI block is used within the digital AGC loop. If digital AGC is not required then the RSSI output, after being averaged by the COMB filter, can be provided back to the BB modem via SPI as shown under [[#Automatic_gain_control|automatic gain control]]. In this way the BB can control RF and IF gain stages to implement analogue AGC in which case the AGC loop is closed via the BB modem.<br />
<br />
There is also an RF RSSI block implemented in the RF front end connected to the input of the wideband LNA. This block can be used to detect the presence of large interferers so the BB modem can adjust RX gain stages very quickly to counteract such scenarios. The RF RSSI output is routed to I ADCs of RX channel 1 or RX channel 2. When the RSSI output is to be read, the main RX path of that channel should be disabled. Also, RF RSSI analog output can be provided off-chip at the test pin and further processed by external circuits. In this case none of the RX paths needs to be disabled. The RSSI detects the input from -70 dBm to -20 dBm, corresponding to the full dynamic range of the ADC.<br />
<br />
===Automatic gain control===<br />
[[File:Lms7002m-tsp-agc.png|center|550px|LMS7002M automatic gain control architecture diagram]]<br />
<br />
The AGC loop functions as follows:<br />
<br />
* “Square root of two” (RSSI) block calculates the RMS of the AGC output.<br />
* This signal is averaged by the COMB filter. The averaging window size AVG is programmable via SPI.<br />
* An error signal is then calculated as the difference between the desired output signal level and the measured one. The desired amplitude level ADESIRED is programmable via SPI.<br />
* After the loop gain stage, the error is integrated to construct the digital VGAs gain control signal. Loop gain K is programmable via SPI.<br />
* VGAs gain cannot be negative and should not be zero either, hence max(1,x) module is provided in the feedback path.<br />
<br />
====Possible applications====<br />
[[File:Lms7002m-tsp-agc-truncation.png|center|550px|LMS7002M AGC truncation application example diagram]]<br />
<br />
The first example (a) shows the case where the BB modem expects 4 bits instead of full 12-bit ADC output. In this case, the ADESIRED loop parameter is set as shown in the figure, the gain of RF and IF stages are set for ADC not to produce full scale but ADESIRED level instead. The middle 4 bits are provided to BB. If the RF input signal level goes higher or lower, AGC will adapt the gain to keep its output at ADESIRED value so bits 7 to 4 will always contain 4 MSBs of the received signal. Since we have 4 bits on top and 4 bits below the middle 4 bits, the loop itself provides ±24 dB automatic gain control range without using RF and IF gain stages. The second example shown (b) is a more general case. The BB modem will receive 10 bits while the loop provides ±6 dB gain control range without engaging RF and IF gain blocks.<br />
<br />
==LimeLight™ digital IQ data interface==<br />
The LMS7002M implements a LimeLight™ digital IQ interface to the BB modem. LimeLight™ can be configured to run in one of the following three modes:<br />
<br />
# JESD207 mode<br />
# TRXIQ double data rate (DDR) mode<br />
# TRXIQ single data rate (SDR) mode<br />
<br />
All three modes are capable of supporting both TDD and FDD operation. The data throughput of JESD207 and TRX DDR is high enough to connect to up to 2x2 MIMO BB modems. TRXIQ SDR mode is backward compatible to the LMS6002D digital IQ interface.<br />
<br />
===JESD mode===<br />
[[File:Lms7002m-limelight-jesd-mode.png|center|550px|LMS7002M LimeLight port, JESD mode]]<br />
<br />
This figure shows typical connectivity between the LMS7002M and the BB modem with LimeLight™ running in JESD207 mode. LimeLight™ uses two such ports to support FDD. Signalling is defined by the JESD207 standard itself as specified by JEDEC.<br />
<br />
===TRIXIQ mode===<br />
Connectivity in TRXIQ DDR and SDR modes is the same. The only difference is that in DDR mode the BB and RF chips sample at both edges of FCLK/MCLK.<br />
<br />
====TRXIQ-TX mode====<br />
[[File:Lms7002m-limelight-trxiq-tx-mode.png|center|550px|LMS7002M LimeLight port, TRXIQ-TX mode]]<br />
<br />
In TRXIQ-TX mode the BB modem provides IQSEL, DIO[11:0] and FCLK. The LMS7002M captures data using one or both edges of FCLK.<br />
<br />
====TRXIQ-RX mode====<br />
[[File:Lms7002m-limelight-trxiq-rx-mode.png|center|550px|LMS7002M LimeLight port, TRXIQ-RX mode]]<br />
<br />
In TRXIQ-RX mode, the LMS7002M provides IQSEL, DIO[11:0] and MCLK. The BB modem captures data using one or both edges of MCLK.<br />
<br />
===Timing diagrams===<br />
<br />
====Data path transmit burst start, JESD207 mode====<br />
[[File:Lms7002m-limelight-jesd207-transmit-burst-start.png|center|550px|LMS7002M LimeLight JESD207 mode transmit burst start timing diagram]]<br />
<br />
====Data path transmit burst finish, JESD207 mode====<br />
[[File:Lms7002m-limelight-jesd207-transmit-burst-finish.png|center|550px|LMS7002M LimeLight JESD207 mode transmit burst finish timing diagram]]<br />
<br />
====Data path receive burst start, JESD207 mode====<br />
[[File:Lms7002m-limelight-jesd207-receive-burst-start.png|center|550px|LMS7002M LimeLight JESD207 mode receive burst start timing diagram]]<br />
<br />
====Data path receive burst finish, JESD207 mode====<br />
[[File:Lms7002m-limelight-jesd207-receive-burst-finish.png|center|550px|LMS7002M LimeLight JESD207 mode receive burst finish timing diagram]]<br />
<br />
====Receive data path, TRXIQ double data rate (DDR) mode====<br />
[[File:Lms7002m-limelight-trxiq-ddr-receive-data-path.png|center|550px|LMS7002M LimeLight TRXIQ DDR mode receive data path timing diagram]]<br />
<br />
====Transmit data path, TRXIQ double data rate (DDR) mode====<br />
[[File:Lms7002m-limelight-trxiq-ddr-transmit-data-path.png|center|550px|LMS7002M LimeLight TRXIQ DDR mode transmit data path timing diagram]]<br />
<br />
====Receive data path, TRXIQ single data rate (SDR) mode====<br />
[[File:Lms7002m-limelight-trxiq-sdr-receive-data-path.png|center|550px|LMS7002M LimeLight TRXIQ SDR mode receive data path timing diagram]]<br />
<br />
====Transmit data path, TRXIQ single data rate (SDR) mode====<br />
[[File:Lms7002m-limelight-trxiq-sdr-transmit-data-path.png|center|550px|LMS7002M LimeLight TRXIQ SDR mode transmit data path timing diagram]]<br />
<br />
==Implementing a low-voltage digital IQ interface==<br />
[[File:Lms7002m-digital-iq-interface-supplies.png|center|550px|LMS7002M digital IQ interface supplies diagram]]<br />
<br />
The digital IO buffers of the LMS7002M are supplied using four pins (pin name – DIGPRVDD2, pin ID – W33, T32, H32, AH30). All these pins must be supplied by the same supply DVDD. There is one additional supply pin (pin name – DIGPRPOC, pin ID – W31) which performs Power On Control (POC) function for digital pads. To implement a low voltage digital interface, DVDD can be lowered to 1.8 V. If DVDD = 1.8V then all data lines shown in the above diagram must also be set to 1.8 V CMOS Ios for correct interface operation.<br />
<br />
==IQ interface timing parameters==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit<br />
|-<br />
|Data setup time (t<sub>SETUP</sub>) || 1 || || || ns<br />
|-<br />
|Data hold time (t<sub>HOLD</sub>) || 0.2 || || || ns<br />
|-<br />
|Data output delay (t<sub>OD</sub>) at 15 pF load || || || 6 || ns<br />
|}<br />
<br />
==Digital IQ interface IO buffers specification==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Supply voltage (PVDD) || 1.7 || 2.5 || 3.6 || V || Can go below 2.5 V nominal to support LV CMOS signalling<br />
|-<br />
|Input high V<sub>IH</sub> || PVDD-0.8 || || || V || <br />
|-<br />
|Input low V<sub>IL</sub> || || || 0.8 || V || <br />
|-<br />
|Output high V<sub>OH</sub> || PVDD-0.4 || || || V || <br />
|-<br />
|Output low V<sub>OL</sub> || || || 0.4 || V || <br />
|-<br />
|Input pad capacitance C<sub>IN</sub> || || || 3.5 || pF || <br />
|-<br />
|Output drive current || || || 8 || mA || <br />
|}<br />
<br />
==DACs electical specifications==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Digital core supply || 1.1 || 1.2 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Analogue supply || 1.1 || 1.2 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Number of bits || || 12 || || bits || Two's complement format<br />
|-<br />
|DAC sampling rate || || || 640 || MHz || <br />
|-<br />
|Full scale current || || 625 || || uA || Programmable<br />
|-<br />
|SFDR || || 63<br />62 || || dBc || Fin=10MHz, -1dBFS<br />Fin=37MHz, -2dBFS<br />
|-<br />
|ENOB || || 9 || || bits || <br />
|}<br />
<br />
==ADCs electrical specification==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Digital core supply || 1.1 || 1.2 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Analogue supply || 1.1 || 1.2 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Number of bits || || 12 || || bits || Two's complement format<br />
|-<br />
|ADC sampling rate || || || 160 || MHz || <br />
|-<br />
|Input amplitude || || 0.8 || || Vpp || Differential<br />
|-<br />
|Input common mode voltage || || 0.55 || || V || <br />
|-<br />
|SFDR || || 63<br />62 || || dBc || Fin=10MHz, -1dBFS<br />Fin=37MHz, -2dBFS<br />
|-<br />
|ENOB || || 9 || || bits || <br />
|}<br />
<br />
==Serial Port Interface==<br />
The functionality of the LMS7002M transceiver is fully controlled by a set of internal registers which can be accessed through a serial port interface. Both write and read SPI operations are supported. The serial port can be configured to run in 3 or 4 wire mode with the following pins used:<br />
<br />
; SEN : serial port enable, active low<br />
; SCLK : serial clock, positive edge sensitive<br />
; SDIO : serial data in/out in 3 wire mode<br />serial data input in 4 wire mode<br />
; SDO : serial data out in 4 wire mode<br />don't care in 3 wire mode<br />
<br />
Serial port key features:<br />
<br />
*32 SPI clock cycles are required to complete a write operation.<br />
* 32 SPI clock cycles are required to complete a read operation.<br />
* Multiple write/read operations are possible without toggling serial port enable signal.<br />
<br />
All configuration registers are 16 bits wide. The write/read sequence consists of a 16-bit instruction followed by 16-bit data to write or read. MSB of the instruction bit stream is used as SPI command where CMD = 1 for write and CMD = 0 for read. Next 4 bits are reserved (Reserved[3:0]) and must be zeroes. Next 5 bits represent module address (Maddress[4:0]) since the LMS7002M configuration registers are divided into logical blocks as shown. The remaining 6 bits of the instruction are used to address particular registers (Reg[5:0]) within the block. Maddress and Reg compiles global 11-bit register address when concatenated ((Maddress << 6) | Reg).<br />
<br />
Note that the write operation is the same for both 3-wire and 4-wire modes. Although not shown, multiple write/read is possible by repeating the instruction/data sequence while keeping SEN low.<br />
<br />
===SPI timing parameters===<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit<br />
|-<br />
|rowspan="2"|Clock frequency, 4-wire mode<br />3-wire mode || || || 50 || MHz<br />
|-<br />
| || || 20 || MHz<br />
|-<br />
|Enable setup time (t<sub>ES</sub) || 2 || || || ns<br />
|-<br />
|Enable hold time (©) || 0.2 || || || ns<br />
|-<br />
|Data set up time (t<sub>DS</sub>) || 1 || || || ns<br />
|-<br />
|Data hold time (t<sub>DH</sub>) || 0.2 || || || ns<br />
|-<br />
|Data output delay (t<sub>OD</sub>) at 12 pF load || || || 6 || ns<br />
|}<br />
<br />
===SPI write cycle, 3-wire and 4-wire modes===<br />
[[File:Lms7002m-spi-write-cycle-timing.png|center|550px|LMS7002M SPI write cycle timing diagram]]<br />
<br />
===SPI read cycle, 4-wire mode (default)===<br />
[[File:Lms7002m-spi-read-cycle-4-wire-timing.png|center|550px|LMS7002M SPI read cycle, 4-wire (default) timing diagram]]<br />
<br />
===SPI read cycle, 3-wire mode===<br />
[[File:Lms7002m-spi-read-cycle-3-wire-timing.png|center|550px|LMS7002M SPI read cycle, 3-wire timing diagram]]<br />
<br />
===SPI memory map===<br />
The LMS7002M configuration registers are divided into a number of logical blocks.<br />
<br />
Integer and fractional parts of the PLL feedback divider are stored in a number of configuration memory registers. To change their values, multiple SPI write cycles are required. Hence, the controlled PLL will continue to output at the previously selected frequency until all NINT and NFRAC registers are updated. Otherwise it would generate an unpredictable and incorrect LO frequency while being configured. Such parameters are provided through shadow registers. Shadow registers are clocked by the PLL reference clock and output new values simultaneously at first positive clock edge after SEN goes high, i.e. after update of shadowed parameters via SPI is finished.<br />
<br />
{| class="wikitable"<br />
!Module description !! Module address [4:0] !! Register address space [5:0]<br />
|-<br />
|Microcontroller (MCU) || 00000 || 00xxxx<br />
|-<br />
|LimeLight port || 00000 || 1xxxxx<br />
|-<br />
|Top control (AFE, BIAS, XBUF, CGEN, LDO, BIST) || 0001x || xxxxxx<br />
|-<br />
|TRX (TRF(A/B), TBB(A/B), RFE(A/B), RBB(A/B), SX(R/T) || 0010x || xxxxxx<br />
|-<br />
|TxTSP(A/B) || 01000 || 0xxxxx<br />
|-<br />
|TxNCO(A/B) || 01001 || xxxxxx<br />
|-<br />
|TxGFIR1(A/B) || 01010 || xxxxxx<br />
|-<br />
|TxGFIR2(A/B) || 01011 || xxxxxx<br />
|-<br />
|TxGFIR3a(A/B) || 01100 || xxxxxx<br />
|-<br />
|TxGFIR3b(A/B) || 01101 || xxxxxx<br />
|-<br />
|TxGFIR3c(A/B) || 01110 || xxxxxx<br />
|-<br />
|RxTSP(A/B) || 10000 || 0xxxxx<br />
|-<br />
|RxNCO(A/B) || 10001 || xxxxxx<br />
|-<br />
|RxGFIR1(A/B) || 10010 || xxxxxx<br />
|-<br />
|RxGFIR2(A/B) || 10011 || xxxxxx<br />
|-<br />
|RxGFIR3a(A/B) || 10100 || xxxxxx<br />
|-<br />
|RxGFIR3b(A/B) || 10101 || xxxxxx<br />
|-<br />
|RxGFIR3c(A/B) || 10110 || xxxxxx<br />
|}<br />
<br />
===Implementing low-voltage SPI===<br />
[[File:Lms7002m-spi-supplies.png|center|550px|LMS7002M SPI supplies diagram]]<br />
<br />
Digital IO buffers in the SPI region are all supplied from the same pins as the digital IQ interface (pin name – DIGPRVDD2, pin ID – W33, T32, H32, AH30). All these pins must be supplied by the same supply DVDD. There is one additional supply pin (pin name – DIGPRPOC, pin ID – W31) which controls the power on circuitry of the digital pads. To implement a low voltage SPI interface, DVDD can be lowered to 1.8V. If DVDD=1.8V then all data lines in the above figure must also be set to 1.8V CMOS Ios for correct interface operation. The PLL reference clock input level is controlled independently of the DVDD voltage. By default it is 1.8V, but can be further lowered to 1.2V by chip controls if needed.<br />
<br />
==On-chip microcontroller==<br />
[[File:Lms7002m-mcu-connections.png|center|550px|LMS7002M on-chip microcontroller connection diagram]]<br />
<br />
The LMS7002M can be fully controlled by external BB/DSP/FPGA ICs using 4-wire or 3-wire serial port interface. The controlling processor needs to implement a set of calibration, tuning, and control functions to get the best performance out of the transceiver. The on-chip microcontroller unit (MCU) provides the option for independent control using code provided by Lime. This allows the LMS7002M to be independent of the BB/DSP/FPGA and off-loads these devices. Users can still implement full control in their preferred way by developing their own code and/or bypassing on chip microcontroller.<br />
<br />
MCU integration within the LMS7002M chip is shown above. Since the chip communication to the outside world is done through SPI the MCU uses the same protocol, hence the block master SPI (mSPI) is placed in front of it. The MCU communicates to the transceiver circuitry using the same SPI protocol as the BB processor itself. This is implemented via ucSPI lines. There is two way communication between the MCU and BB via mSPI. The baseband can trigger different calibration/tuning/control functions the MCU is programmed to perform. The MCU reports a success, failure or an error code back to the base band processor.<br />
<br />
In this architecture, the base band processor acts as master since it controls the whole chip (the transceiver as well as MCU). The baseband processor also controls the SPI switch (via the SPISW_CTRL control bit/line of mSPI) i.e. taking control over the transceiver part or handing it over to the MCU. The MCU acts as a slave processor. It can control the transceiver only if the baseband allows that via the SPI switch.<br />
<br />
The baseband has full control over the chip including calibration, tuning, and control. It also can trigger the MCU for assistance. In this case, it works in the following way:<br />
<br />
# The base band sets the transceiver for the targets (TX LO frequency, RX LO frequency, TX gain, RX gain, …).<br />
# The base band hands over SPI control to the MCU by setting SPISW_CTRL.<br />
# The base band triggers the function for the MCU to execute.<br />
# The base band periodically checks to see if the MCU has finished and for the status (success, failure, error code).<br />
<br />
===MCU boot-up and EEPROM programming===<br />
Two options are supported, one using external (off-chip) EEPROM and another without external EEPROM.<br />
<br />
====Using external EEPROM====<br />
# The baseband processor uploads 8 KB into the on chip program memory.<br />
# After receiving 8 KB, the MCU flushes program memory into EEPROM.<br />
# The base band resets the MCU. <br />
# The MCU reads EEPROM content back into the program memory and starts executing the code.<br />
After the initial EEPROM programming only steps 3 and 4 are required.<br />
<br />
====Without external EEPROM====<br />
# The baseband processor uploads 8 KB into the on chip program memory.<br />
# After receiving 8 KB, the MCU starts executing the code.<br />
<br />
===Specifications===<br />
* 8-bit microcontroller.<br />
* Industry standard 8051 instruction set compatible.<br />
* Running up to 60 MHz.<br />
* Memory<br />
** 8 KB SRAM program memory<br />
** 2 KB SRAM working memory<br />
** 256 B dual port RAM<br />
** All on-chip, integrated.<br />
<br />
==Data converters clock generation==<br />
[[File:Lms7002m-clock-generation.png|center|550px|LMS7002M clock generation diagram]]<br />
<br />
The clock generation circuit for the data converters is shown above. It shares the same reference clock input REFCLK with the RF synthesisers. The clock PLL then generates a continuous frequency range centered around 2.5 GHz. The feed forward divider (FFDIV) is programmable and capable of implementing division values as below:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{N} = 2 \left( \mathit{n} + 1 \right) , \mathit{n} = 0 , 1 , \ldots , 255<br />
\end{align}<br />
</math><br />
<br />
There is a fixed divide by 4 within the ADC block, hence clock division on the DAC side, to provide more flexibility. There is a MUX to connect either Fpll, or Fpll/M to either ADC or DAC clocks. M is programmable and can be set to M = 1, 2, 4 or 8. The other CLKMUX output will be connected to the other data converter clock input. <br />
<br />
TSP blocks receive the same clock as the corresponding data converter, hence there is no need for complex non-power of two or fractional interpolation/decimation. TSP blocks have programmable interpolation/decimation and generate MCLK clocks going back to the base band processor via the LimeLight™ port.<br />
<br />
The circuit implements a continuous clock frequency range from 5 MHz to 320 MHz for the data converters. It is still possible to generate the maximum DAC clock of 640 MHz, however it is not continuous in the range of 320 MHz – 640 MHz.<br />
<br />
==Calibration and initialisation==<br />
There are a number of calibrations which the LMS7002M can carry out internally when instructed via the SPI. These calibrations can be initiated on power up/reset to produce optimum settings. Initialisation and calibration steps are summarised below.<br />
<br />
===Initialisation===<br />
* Power up the chip. In case of using multiple off-chip LDOs, power up sequence is not important.<br />
* Apply RESET pulse (active low). This sets all the configuration registers to their default values.<br />
* Overwrite some registers' defaults if required.<br />
<br />
===Available calibration options===<br />
Listed in recommended order of execution.<br />
* On-chip resistor and capacitor calibration<br />
* TX, RX and clock synthesizer VCO tuning<br />
* TX and RX analog LPF pass band tuning<br />
* RX DC offset and RX LO leakage cancellation<br />
* TX DC offset and TX LO leakage cancellation<br />
* TX IQ imbalance calibration<br />
* RX IQ imbalance calibration<br />
<br />
===Calibration algorithms===<br />
This section shows three key calibration algorithms. Others are either similar or very simple. Please see the LMS7002M Programming and Calibration Guide and other relevant application notes for more details.<br />
<br />
====VCO tuning====<br />
In order to lock the RF or clock synthesiser while having phase noise close to optimum, VCO capacitance has to be selected carefully. A flexible algorithm, based on monitoring on chip Vtune comparators state, is described below.<br />
<br />
[[File:Lms7002m-calibration-vcocap.png|center|550px|LMS7002M calibration, VCOCAP]]<br />
<br />
Assuming the synthesiser is configured for target LO/clock frequency (correct VCO powered up, integer and fractional part of the divider set, …), the above figure shows typical measured Vtune variation with the VCOCAP codes for the two target LO frequencies 1.95 GHz and 2.14 GHz. Vtune is changing from 1.17V down to 0.05 V. However, PLL lock is guaranteed only when Vtune is in the range 0.18 V-0.92 V. Also, for the best phase noise performance, Vtune should be kept around the middle of the range i.e. 0.55 V.<br />
<br />
There are two on chip Vtune comparators per synthesiser: CMPH and CMPL. Their threshold voltages are set to Vth High=0.92 V and Vth Low=0.18 V. The state of the comparators can be obtained by powering them up and reading the corresponding SPI register. The truth table is given below.<br />
<br />
{| class="wikitable"<br />
!CMPH !! CMPL !! Status<br />
|-<br />
|1 || 0 || OK, Vtune in range<br />
|-<br />
|0 || 0 || Vtune is high (>0.92 V), PLL lock not guaranteed<br />
|-<br />
|1 || 1 || Vtune is low (<0.18 V), PLL lock not guaranteed<br />
|-<br />
|0 || 1 || Not possible<br />
|}<br />
<br />
These can be used to choose VCOCAP code. All we need to find is the code CMIN when comparators change the state from “00” to “10” and the code CMAX when the comparators change the state from “10” to “11”. Optimum VCOCAP code is then the middle one between CMIN and CMAX. For LO=2.4 GHz, this is illustrated in the earlier graph. In this case, optimum code is around 108.<br />
<br />
Once the synthesiser is set, Vtune comparators can also be used as lock (in range) indicators.<br />
<br />
====Analogue filters pass band tuning====<br />
The LMS7002M has six analogue low-pass filtering stages. The pass band of each stage can independently be programmed and/or tuned. Tuning is very useful as it takes into account process, temperature, sample-to-sample and voltage supply variations. The algorithm uses on chip options as follows:<br />
* TXNCO generates digital test tones (CW).<br />
* Digital test tones are converted into analog by the DACs.<br />
* INVERSE sinc filter must be enabled to flatten DACs amplitude response.<br />
* LMS7002M is set into either base-band or RF TX-to-RX loop back mode.<br />
* Only LPF being tuned should be enabled. Other TX and RX filters should be bypassed or widely open.<br />
* Loop back signal is converted back into digital domain by the ADCs.<br />
* Digital RX RSSI block measures the amplitude of the loop back signal.<br />
<br />
All filtering stages are implemented as active RC blocks hence their pass band is controllable by changing resistors and/or capacitors. Only two parameters per stage are available to change via SPI: one for filter resistors control and another one for capacitors control. If the resistors control parameter is changed then all resistors within the filter are scaled equally; if the capacitors control code is changed then all capacitors within the filter are scaled equally. Therefore, component ratio is kept constant which preserves designed filter amplitude response (Chebyshev for example) disregarding the control codes.<br />
<br />
There are two types of filter stages: trans-impedance (TXLPFLAD, TXLPFH, RXTIA) and voltage gain (TXLPFS5, RXLPFL, RXLPFH). Tuning is essentially the same for all stages with minor differences between trans-impedance and voltage gain types. The algorithm is two steps process described below and illustrated in the following figure.<br />
<br />
[[File:Lms7002m-calibration-pass-band.png|center|550px|LMS7002M calibration, pass-band tuning]]<br />
<br />
=====Step 1: Checkpoint=====<br />
TXNCO generates very low frequency (close to DC) test tone (200 kHz in the previous figure) which is by design guaranteed to be within filter pass band for all possible RC values.<br />
<br />
Tune the gain of the measurement loop (use DACs current amplifiers and RXPGA) to get RSSI reading few dB backed off from its maximum. This maximises the measurement dynamic range while still having some margin to measure filter gain which may be higher than the gain at low frequencies due to in band amplitude ripple.<br />
<br />
=====Step 2: RC search=====<br />
# TXNCO generates a test tone which is the target 3 dB cut-off frequency (4 MHz in the previous figure).<br />
# Alter C components of the filter to get RSSI reading 3 dB below the reading obtained at the end of step 1.<br />
## If step 2 fails to reach the target, change R components of the filter. If filter stage is trans-impedance go to step 1, otherwise go to step 2. Note that changing R in the trans-impedance stage changes its gain, hence the need to repeat step 1.<br />
<br />
====DC offset and IQ imbalance calibration====<br />
In order to show the basis of this kind of calibrations, let us first analyse a scenario with the LMS7002M configured as below.<br />
<br />
* Drive TXTSP with digital 12-bit two’s complement DC i.e. <br />
** TXI = 011111111111 = +max 12-bit word<br />
** TXQ = 10000000000 = -max 12-bit word<br />
*: This can be done through the on-chip test option, no need to engage LimeLight™ with assistance from BB.<br />
* Bypass IQ Gain Correction, IQ Phase Correction and TX DC Correction TXTSP blocks. Keep INVERSE sinc filter running.<br />
* Configure TXLPF pass band to be able to filter DAC images.<br />
* Tune TX Synthesiser to <math>\mathit{f_{TXLO}}</math>. Tune RX Synthesiser to <math>\mathit{f_{RXLO}}</math> offset from <math>\mathit{f_{TXLO}}</math> by a few MHz and keep <math>\mathit{f_{TXLO}} > \mathit{f_{RXLO}}</math>.<br />
* Close RF Loopback switch.<br />
* Set TXPAD, RXTIA and RXPGA gain not to overload ADCs.<br />
* Open RXLPF pass band as much as possible to clearly see all tones generated in this setup.<br />
* Bypass IQ Gain Correction, IQ Phase Correction and RX DC Correction RXTSP blocks. Bypass Decimation filter to see all tones generated by the whole setup.<br />
* Set RXNCO frequency to 0. Set TXNCO to <math>\mathit{f_{TXNCO}}</math> where <math>\mathit{f_{TXLO}} - \mathit{f_{RXLO}} > \mathit{f_{TXNCO}}</math><br />
<br />
The test setup described above uses minimum filtering to clearly show unwanted tones we need to cancel. The following spectrum diagram shows RX output while LMS7002M works in RF loopback mode. Tones and the reasons for their existence are as below.<br />
<br />
[[File:Lms7002m-calibration-iq-imbalance-spectral-tones.png|center|550px|LMS7002M calibration, IQ imbalance spectral tones example]]<br />
<br />
: (1) TX DC and TX LO leakage. It is down converted by fRXLO hence it appears in BB frequencies at fTXLO-fRXLO<br />
: (2) This is wanted TX sideband. Offset from TX LO leakage by TXNCO frequency .fTXNCO.<br />
: (3) Unwanted TX sideband caused by TX IQ imbalance.<br />
: (4) RX DC offset and RX LO leakage. Appears at DC.<br />
: (3a) RX unwanted side band caused by component (3)<br />
: (1a) RX unwanted side band caused by component (1)<br />
: (2a) RX unwanted side band caused by component (2)<br />
<br />
Note that all tones at negative frequencies are the consequence of RX IQ imbalance.<br />
<br />
The previous figure shows that with single measurement we can capture all tones we need to cancel. There are two problems with this approach. First, we need to perform complex FFT which is computationally intensive, i.e. it takes a long time. The on-chip MCU is not computationally powerful enough, so FFT has to be done by the BB processor which we want to avoid. The alternative would be to use digital RSSI for measurement instead of FFT. RSSI can accurately measure only single tone, not the multiple tones present in the previous figure. Fortunately, choosing the order of calibration steps carefully and with the help of on-chip available options (digital and/or analogue filters, TX and RX NCOs) this is possible.<br />
<br />
TX IQ imbalance calibration steps are shown here as an illustration. Other calibration steps are similar. Let us assume that RX DC/LO leakage as well as TX DC/LO leakage calibration steps have already been performed, i.e. tones (1), (1a), and (4) are minimised. In this case we will have four remaining tones as shown in the below figure.<br />
<br />
[[File:Lms7002m-calibration-digital-filtering-step-a.png|center|550px|LMS7002M calibration, digital filtering step (a)]]<br />
<br />
The goal of this calibration is to minimize tone (3) keeping wanted tone (2) untouched. Tone (2) will introduce a huge error if present in RSSI measurement, so some filtering will be required. Decimation filter is used for this purpose rather than general purpose FIR filters due to the fact that decimation filter is much simpler and faster to configure. The resulting spectrum after digital filtering is shown in the figure below.<br />
<br />
[[File:Lms7002m-calibration-digital-filtering-step-b.png|center|550px|LMS7002M calibration, digital filtering step (b)]]<br />
<br />
The same spectrum of the above figure drives the digital RSSI block. In fact, RSSI measures the level of the two-tone signal (3) and (3a), where (3a) is due to RX IQ imbalance. However, tones are correlated; in other words when minimising (3), tone (3a) will go down by the same amount. The RSSI output will be a composite power level of those two tones and is a valid measurement. If we minimise RSSI output we are minimising TX IQ imbalance disregarding the presence of two (correlated) tones.<br />
<br />
The algorithm, then, is simple. First alter the on-chip analogue IQ phase correction parameters, if available, to minimise RSSI output. After that alter the TX gain correction and TX phase correction parameters of the TXTSP digital block to further minimise RSSI output. The resulting spectrum is shown in the following figure.<br />
<br />
[[File:Lms7002m-calibration-digital-filtering-step-c.png|center|550px|LMS7002M calibration, digital filtering step (c)]]<br />
<br />
====TDD/FDD mode enhancement option====<br />
In both TDD and FDD mode the LMS7002M is capable of running from a single PLL, allowing one on-chip PLL to be powered down. In TDD mode, a single PLL output drives both TX and RX mixers; in FDD mode, a single PLL drives both mixers as well while UL/DL frequency separation is implemented in the digital domain using the NCO and complex mixer parts of the TSP block. The maximum frequency shift range which can be achieved in the digital domain is as below:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{f_{TXLO}} = \mathit{f_{PLL}} \pm 0.6 * \mathit{f_{DAC}} / 2 \\<br />
\mathit{f_{RXLO}} = \mathit{f_{PLL}} \pm 0.6 * \mathit{f_{ADC}} / 2<br />
\end{align}<br />
</math><br />
<br />
where <math>\mathit{f_{TXLO}}</math> and <math>\mathit{f_{RXLO}}</math> are effective TX and RX LO frequencies, <math>\mathit{f_{PLL}}</math> is the shared PLL output frequency while <math>\mathit{f_{DAC}}</math> and <math>\mathit{f_{ADC}}</math> are data converter sampling rates. Note that the Nyquist frequency of the NCOs is scaled by a factor of 0.6 to make space for TXLPF and RXLPF to operate.<br />
<br />
Running the LMS7002M in single PLL mode has the following advantages:<br />
<br />
* Current consumption is significantly reduced since one PLL is powered down.<br />
* Fast TX<->RX switching time in TDD mode is achievable since the PLL does not need to relock.<br />
* There is no TXVCO<->RXVCO polling issue since a single PLL is used.<br />
* Using the digital domain for LO frequency shifts enables implementation of very fast frequency hopping systems.<br />
<br />
====Improving fractional-N close-to-integer RF synthesiser spurs performance====<br />
Due to the PFD/CHP ‘dead zone,’ i.e. nonlinearity around zero, fractional-N synthesisers are prone to generate unwanted spurs when set close to integer frequency. These spurs are unfortunately in the loop-pass band and cannot be filtered. One of the solutions is to set constant charge pump current offset to shift PFD/CHP away from zero, i.e. operating them in a more linear region. However, this CHP offset value depends on how far PLL output frequency is away from the nearest integer frequency and has to be tuned accordingly.<br />
<br />
Digital blocks can help this case. Set the charge pump offset current to some middle value and keep it constant disregarding how far close-to-integer frequency is away from integer frequency. Offset the PLL wanted frequency away enough from integer frequency in order not to have close-to-integer spurs issue. This introduces a PLL output frequency error which can be corrected by a corresponding NCO available in the digital TSB block.<br />
<br />
==Package outline and pin description==<br />
[[File:Lms7002m-261l-aqfn-package-top.png|center|550px|LMS7002M in 261L aQFN package, top view]]<br />
<br />
{| class="wikitable"<br />
!Pin No. !! Pin ID !! Pin Name !! Type !! Description !! Notes<br />
|-<br />
| 1 || C1 || UNUSED || - || - || <br />
|-<br />
| 2 || D2 || UNUSED || - || - || <br />
|-<br />
| 3 || E3 || UNUSED || - || - || <br />
|-<br />
| 4 || F4 || UNUSED || - || - || <br />
|-<br />
| 5 || G5 || VDD12_TXBUF || analogue supply || 1.25V supply – TX XOSC buffer || <br />
|-<br />
| 6 || H6 || VDD18_TXBUF || analogue supply || 1.8V supply – TX XOSC buffer || <br />
|-<br />
| 7 || F2 || UNUSED || - || - || <br />
|-<br />
| 8 || G3 || VDD18_VCO_SXT || analogue supply || 1.8V supply – TX SX VCO || <br />
|-<br />
| 9 || J5 || VDD12O_VCO_SXT || analogue supply || 1.25V supply – TX SX VCO || <br />
|-<br />
| 10 || K6 || VDD12_VCO_SXT || analogue supply || 1.25V supply – TX SX VCO || <br />
|-<br />
| 11 || G1 || UNUSED || - || - || <br />
|-<br />
| 12 || H2 || GND_VCO_SXT || analogue gnd || GND – TX SX VCO || <br />
|-<br />
| 13 || J3 || VDD_CP_SXT || analogue supply || 1.25V supply – TX SX Charge pump || <br />
|-<br />
| 14 || K4 || GND_CP_SXT || analogue gnd || GND – TX SX Charge pump || <br />
|-<br />
| 15 || L5 || VDD_DIV_SXT || analogue supply || 1.25V supply – TX SX frequency divider || <br />
|-<br />
| 16 || J1 || UNUSED || - || - || <br />
|-<br />
| 17 || K2 || VDDO_DIV_SXT || analogue supply || 1.25V supply – TX SX frequency divider || <br />
|-<br />
| 18 || M6 || UNUSED || - || - || <br />
|-<br />
| 19 || L3 || GND_DIV_SXT || analogue gnd || GND – TX SX frequency divider || <br />
|-<br />
| 20 || M4 || DVDD_SXT || digital supply || 1.25V supply – digital supply for TX SX || <br />
|-<br />
| 21 || M2 || UNUSED || - || - || <br />
|-<br />
| 22 || N3 || DGND_SXT || digital gnd || GND – digital supply for TX SX || <br />
|-<br />
| 23 || N1 || VDD18_LDO_TX || analogue supply || 1.8V supply – TX LDO || <br />
|-<br />
| 24 || P4 || VDD_TBB || analogue supply || 1.25V supply – TX baseband || <br />
|-<br />
| 25 || P2 || tbbqn_pad_1 || in || TX change input pad to externally drive the TX BB Channel 1 || <br />
|-<br />
| 26 || R5 || tbbin_pad_1 || in || TX change input pad to externally drive the TX BB Channel 1 || <br />
|-<br />
| 27 || R3 || tbbqp_pad_1 || in || TX change input pad to externally drive the TX BB Channel 1 || <br />
|-<br />
| 28 || T6 || tbbin_pad_2 || in || TX change input pad to externally drive the TX BB Channel 2 || <br />
|-<br />
| 29 || T4 || tbbip_pad_1 || in || TX change input pad to externally drive the TX BB Channel 1 || <br />
|-<br />
| 30 || U5 || adcin_in_1 || in || ADC input pads – To use external filtering Channel 1 || <br />
|-<br />
| 31 || U3 || tbbqp_pad_2 || in || TX change input pad to externally drive the TX BB Channel 2 || <br />
|-<br />
| 32 || U1 || tbbqn_pad_2 || in || TX change input pad to externally drive the TX BB Channel 2 || <br />
|-<br />
| 33 || V2 || tbbip_pad_2 || in || TX change input pad to externally drive the TX BB Channel 2 || <br />
|-<br />
| 34 || V4 || adcin_ip_1 || in || ADC input pads – To use external filtering Channel 1 || <br />
|-<br />
| 35 || V6 || adcin_in_2 || in || ADC input pads – To use external filtering Channel 2 || <br />
|-<br />
| 36 || W3 || adcin_qn_1 || in || ADC nput pads – To use external filtering Channel 1 || <br />
|-<br />
| 37 || Y2 || adcin_qp_1 || in || ADC input pads – To use external filtering Channel 1 || <br />
|-<br />
| 38 || Y4 || adcin_qn_2 || in || ADC input pads – To use external filtering Channel 2 || <br />
|-<br />
| 39 || AA1 || adcin_ip_2 || in || ADC input pads – To use external filtering Channel 2 || <br />
|-<br />
| 40 || Y6 || rbbip_pad_1 || out || RX BB output – To use external filtering Channel 1 || <br />
|-<br />
| 41 || AA3 || adcin_qp_2 || in || ADC input pads – To use external filtering Channel 2 || <br />
|-<br />
| 42 || AA5 || rbbqn_pad_1 || out || RX BB output – To use external filtering Channel 1 || <br />
|-<br />
| 43 || AB2 || rbbin_pad_1 || out || RX BB output – To use external filtering Channel 1 || <br />
|-<br />
| 44 || AB4 || rbbqp_pad_1 || out || RX BB output – To use external filtering Channel 1 || <br />
|-<br />
| 45 || AC3 || rbbin_pad_2 || out || RX BB output – To use external filtering Channel 2 || <br />
|-<br />
| 46 || AB6 || rbbqn_pad_2 || out || RX BB output – To use external filtering Channel 2 || <br />
|-<br />
| 47 || AD2 || rbbip_pad_2 || out || RX BB output – To use external filtering Channel 2 || <br />
|-<br />
| 48 || AC5 || rbbqp_pad_2 || out || RX BB output – To use external filtering Channel 2 || <br />
|-<br />
| 49 || AE1 || UNUSED || - || - || <br />
|-<br />
| 50 || AD4 || VDD14_RBB || analogue supply || 1.4V supply- RX baseband || <br />
|-<br />
| 51 || AE3 || VDD18_TIA_RFE || analogue supply || 1.8V supply- RXFE TIA || <br />
|-<br />
| 52 || AF2 || VDD14_TIA_RFE || analogue supply || 1.4V supply- RXFE TIA || <br />
|-<br />
| 53 || AD6 || VDD12_TIA_RFE || analogue supply || 1.25V supply- RXFE TIA || <br />
|-<br />
| 54 || AE5 || UNUSED || - || - || <br />
|-<br />
| 55 || AF4 || VDD18_LDO_RX || analogue supply || 1.8V supply- RX LDO || <br />
|-<br />
| 56 || AG2 || UNUSED || - || - || <br />
|-<br />
| 57 || AH2 || UNUSED || - || - || <br />
|-<br />
| 58 || AJ1 || UNUSED || - || - || <br />
|-<br />
| 59 || AF6 || VDD14_LNA_RFE || analogue supply || 1.4V supply- RXFE LNA || <br />
|-<br />
| 60 || AG5 || VDD12_LNA_RFE || analogue supply || 1.25V supply- RXFE LNA || <br />
|-<br />
| 61 || AH4 || UNUSED || - || - || <br />
|-<br />
| 62 || AJ3 || UNUSED || - || - || <br />
|-<br />
| 63 || AK2 || UNUSED || - || - || <br />
|-<br />
| 64 || AJ5 || UNUSED || - || - || <br />
|-<br />
| 65 || AK4 || UNUSED || - || - || <br />
|-<br />
| 66 || AL3 || UNUSED || - || - || <br />
|-<br />
| 67 || AM2 || UNUSED || - || - || <br />
|-<br />
| 68 || AN3 || rfgp_w_RFE_2 || in || LNA input gate Wideband LNA – Gate : Channel 2 || <br />
|-<br />
| 69 || AM4 || rfgn_w_RFE_2 || in || LNA input gate Wideband LNA – Gate : Channel 2 || <br />
|-<br />
| 70 || AL5 || UNUSED || - || - || <br />
|-<br />
| 71 || AK6 || UNUSED || - || - || <br />
|-<br />
| 72 || AJ7 || rfsn_l_RFE_2 || in/out || LNA Lowband LNA – Source: Channel 2 || <br />
|-<br />
| 73 || AN5 || rfgp_l_RFE_2 || in || LNA input gate Lowband LNA – Gate : Channel 2 || <br />
|-<br />
| 74 || AM6 || UNUSED || - || - || <br />
|-<br />
| 75 || AL7 || UNUSED || - || - || <br />
|-<br />
| 76 || AK8 || UNUSED || - || - || <br />
|-<br />
| 77 || AJ9 || rfsp_l_RFE_2 || in/out || LNA Lowband LNA – Source : Channel 2 || <br />
|-<br />
| 78 || AP6 || rfgn_l_RFE_2 || in || LNA input gate Lowband LNA – Gate : Channel 2 || <br />
|-<br />
| 79 || AN7 || rfgp_h_RFE_2 || in || LNA input gate Highband LNA – Gate : Channel 2 || <br />
|-<br />
| 80 || AM8 || rfgn_h_RFE_2 || in || LNA input gate Highband LNA – Gate : Channel 2 || <br />
|-<br />
| 81 || AL9 || UNUSED || - || - || <br />
|-<br />
| 82 || AK10 || UNUSED || - || - || <br />
|-<br />
| 83 || AJ11 || UNUSED || - || - || <br />
|-<br />
| 84 || AN9 || rfgp_w_RFE_1 || in || LNA input gate Wideband LNA – Gate : Channel 1 || <br />
|-<br />
| 85 || AM10 || UNUSED || - || - || <br />
|-<br />
| 86 || AL11 || UNUSED || - || - || <br />
|-<br />
| 87 || AP10 || rfgn_w_RFE_1 || in || LNA input gate Wideband LNA – Gate : Channel 1 || <br />
|-<br />
| 88 || AK12 || rfsn_l_RFE_1 || in/out || LNA Lowband LNA – Source : Channel 1 || <br />
|-<br />
| 89 || AN11 || rfgp_l_RFE_1 || in || LNA input gate Lowband LNA – Gate : Channel 1 || <br />
|-<br />
| 90 || AJ13 || UNUSED || - || - || <br />
|-<br />
| 91 || AM12 || rfgn_l_RFE_1 || in || LNA input gate Lowband LNA – Gate : Channel 1 || <br />
|-<br />
| 92 || AL13 || rfsp_l_RFE_1 || in/out || LNA Lowband LNA – Source : Channel 1 || <br />
|-<br />
| 93 || AK14 || rfgp_h_RFE_1 || in || LNA input gate Highband LNA – Gate : Channel 1 || <br />
|-<br />
| 94 || AJ15 || rfgn_h_RFE_1 || in || LNA input gate Highband LNA – Gate : Channel 1 || <br />
|-<br />
| 95 || AN17 || VDD_MXLOBUF_RFE || analogue supply || 1.25V supply: RX LO buffers || <br />
|-<br />
| 96 || AM18 || VDD18_SXR || analogue supply || 1.8V supply: RX SX || <br />
|-<br />
| 97 || AL19 || VDD_CP_SXR || analogue supply || 1.25V supply: RX SX Charge pump || <br />
|-<br />
| 98 || AJ19 || GND_CP_SXR || analogue gnd || GND: RX SX Charge pump || <br />
|-<br />
| 99 || AM20 || VDD_DIV_SXR || analogue supply || 1.25V supply: RX SX frequency divider || <br />
|-<br />
| 100 || AK20 || GND_DIV_SXR || analogue gnd || GND: RX SX frequency divider || <br />
|-<br />
| 101 || AL21 || DVDD_SXR || digital supply || 1.25V digital supply: RX SX f || <br />
|-<br />
| 102 || AJ21 || UNUSED || - || - || <br />
|-<br />
| 103 || AM22 || DGND_SXR || digital gnd || GND: RX SX || <br />
|-<br />
| 104 || AN23 || VDD12_VCO_SXR || analogue supply || 1.25V supply: RX SX || <br />
|-<br />
| 105 || AK22 || VDD18_VCO_SXR || analogue supply || 1.8V supply: RX SX || <br />
|-<br />
| 106 || AL23 || GND_VCO_SXR || analogue gnd || GND: RX SX VCO || <br />
|-<br />
| 107 || AM24 || xoscin_rx || in || || <br />
|-<br />
| 108 || AN25 || GND_RXBUF || analogue gnd || GND – RX XOSC buffer || <br />
|-<br />
| 109 || AP26 || VDD12_RXBUF || analogue supply || 1.25V supply – RX XOSC buffer || <br />
|-<br />
| 110 || AM26 || VDD18_RXBUF || analogue supply || 1.8V supply – RX XOSC buffer || <br />
|-<br />
| 111 || AN27 || UNUSED || - || - || <br />
|-<br />
| 112 || AJ25 || VDD_AFE || analogue supply || 1.25V supply – ADC/DAC || <br />
|-<br />
| 113 || AK26 || UNUSED || - || - || <br />
|-<br />
| 114 || AL27 || UNUSED || - || - || <br />
|-<br />
| 115 || AM28 || UNUSED || - || - || <br />
|-<br />
| 116 || AN29 || UNUSED || - || - || <br />
|-<br />
| 117 || AP30 || UNUSED || - || - || <br />
|-<br />
| 118 || AJ27 || UNUSED || - || - || <br />
|-<br />
| 119 || AK28 || UNUSED || - || - || <br />
|-<br />
| 120 || AL29 || UNUSED || - || - || <br />
|-<br />
| 121 || AM30 || UNUSED || - || - || <br />
|-<br />
| 122 || AN31 || UNUSED || - || - || <br />
|-<br />
| 123 || AP32 || UNUSED || - || - || <br />
|-<br />
| 124 || AJ29 || UNUSED || - || - || <br />
|-<br />
| 125 || AL31 || UNUSED || - || - || <br />
|-<br />
| 126 || AK30 || UNUSED || - || - || <br />
|-<br />
| 127 || AM34 || UNUSED || - || - || <br />
|-<br />
| 128 || AL33 || UNUSED || - || - || <br />
|-<br />
| 129 || AK32 || UNUSED || - || - || <br />
|-<br />
| 130 || AJ31 || UNUSED || - || - || <br />
|-<br />
| 131 || AH30 || DIGPRVDD2 || DVDD || Digital Pad Ring power supply for post-driver || <br />
|-<br />
| 132 || AG29 || DIGPRGND1 || pad gnd || Digital Pad Ring ground for pre-driver || <br />
|-<br />
| 133 || AK34 || UNUSED || - || - || <br />
|-<br />
| 134 || AJ33 || UNUSED || - || - || <br />
|-<br />
| 135 || AH32 || UNUSED || - || - || <br />
|-<br />
| 136 || AG31 || DIQ1_D0 || IO_cmos1225 || DIQ bus, bit 0. LML Port 1 || <br />
|-<br />
| 137 || AF30 || DIQ1_D1 || IO_cmos1225 || DIQ bus, bit 1. LML Port 1 || <br />
|-<br />
| 138 || AE29 || DIGPRVDD1 || DVDD || Digital Pad Ring power supply for pre-driver || <br />
|-<br />
| 139 || AG33 || UNUSED || - || - || <br />
|-<br />
| 140 || AF32 || DIGPRGND2 || pad gnd || Digital Pad Ring ground for post-driver || <br />
|-<br />
| 141 || AE31 || DIQ1_D3 || IO_cmos1225 || DIQ bus, bit 3. LML Port 1 || <br />
|-<br />
| 142 || AD30 || DIQ1_D4 || IO_cmos1225 || DIQ bus, bit 4. LML Port 1 || <br />
|-<br />
| 143 || AF34 || DIQ1_D2 || IO_cmos1225 || DIQ bus, bit 2. LML Port 1 || <br />
|-<br />
| 144 || AE33 || DIQ1_D6 || IO_cmos1225 || DIQ bus, bit 6. LML Port 1 || <br />
|-<br />
| 145 || AC29 || DIQ1_D5 || IO_cmos1225 || DIQ bus, bit 5. LML Port 1 || <br />
|-<br />
| 146 || AD32 || DIQ1_D7 || IO_cmos1225 || DIQ bus, bit 7. LML Port 1 || <br />
|-<br />
| 147 || AC31 || DIQ1_D8 || IO_cmos1225 || DIQ bus, bit 8. LML Port 1 || <br />
|-<br />
| 148 || AB30 || DIQ1_D10 || IO_cmos1225 || DIQ bus, bit 10. LML Port 1 || <br />
|-<br />
| 149 || AC33 || DIQ1_D9 || IO_cmos1225 || DIQ bus, bit 9. LML Port 1 || <br />
|-<br />
| 150 || AB32 || DIQ1_D11 || IO_cmos1225 || DIQ bus, bit 11. LML Port 1 || <br />
|-<br />
| 151 || AA29 || DIGPRVDD1 || DVDD || Digital Pad Ring power supply for pre-driver || <br />
|-<br />
| 152 || AB34 || MCLK1 || out_cmos1225 || Clock from RFIC to BBIC in JESD207 mode. LML Port 1 || <br />
|-<br />
| 153 || AA31 || DIGPRGND1 || DGND || Digital Pad Ring ground for pre-driver || <br />
|-<br />
| 154 || AA33 || FCLK1 || in_cmos1225 || Clock from BBIC to RFIC in JESD207 mode. LML Port 1 || <br />
|-<br />
| 155 || Y30 || DIGPRGND2 || pad gnd || Digital Pad Ring ground for post-driver || <br />
|-<br />
| 156 || Y32 || ENABLE_IQSEL1 || IO_cmos1225 || IQ flag in RXTXIQ mode; enable flag in JESD207 mode. LML Port 1 || <br />
|-<br />
| 157 || W29 || DIGPRGND1 || pad gnd || Digital Pad Ring ground for pre-driver || <br />
|-<br />
| 158 || W31 || DIGPRPOC || POC || POC circuit || <br />
|-<br />
| 159 || W33 || DIGPRVDD2 || DVDD || Digital Pad Ring power supply for post-driver || <br />
|-<br />
| 160 || V30 || LOGIC_RESET || analogue supply/gnd || Not used || <br />
|-<br />
| 161 || V32 || TXNRX1 || in_cmos1225 || IQ data protocol control in JESD207 mode. LML Port 1 || <br />
|-<br />
| 162 || V34 || RXEN || in_cmos1225 || RX hard power off || <br />
|-<br />
| 163 || U33 || CORE_LDO_EN || analogue supply/gnd || External enable control signal for the internal LDOs. || Should be fixed to analogue supply if internal LDOs are used.<br />Should be fixed to analogue gnd if internal LDOs are NOT used.<br />
|-<br />
| 164 || U31 || TXNRX2 || in_cmos1225 || IQ data protocol control in JESD207 mode. LML Port 2 || <br />
|-<br />
| 165 || U29 || TXEN || in_cmos1225 || TX hard power off || <br />
|-<br />
| 166 || T32 || DIGPRVDD2, DIGPRPOC || DVDD || Digital Pad Ring power supply for post-driver and POC || <br />
|-<br />
| 167 || T30 || DIGPRGND1, DIGPRGND2 || pad gnd || Digital Pad Ring ground for pre-driver and post-driver || <br />
|-<br />
| 168 || R33 || ENABLE_ IQSEL2 || IO_cmos1225 || IQ flag in RXTXIQ mode; enable flag in JESD207 mode. LML Port 2 || <br />
|-<br />
| 169 || R31 || DIGPRVDD1 || DVDD || Digital Pad Ring power supply for pre-driver || <br />
|-<br />
| 170 || P34 || MCLK2 || out_cmos1225 || Clock from RFIC to BBIC in JESD207 mode. LML Port 2 || <br />
|-<br />
| 171 || R29 || FCLK2 || in_cmos1225 || Clock from BBIC to RFIC in JESD207 mode. LML Port 2 || <br />
|-<br />
| 172 || P32 || DIQ2_D11 || IO_cmos1225 || DIQ bus, bit 11. LML Port 2 || <br />
|-<br />
| 173 || P30 || DIQ2_D10 || IO_cmos1225 || DIQ bus, bit 10. LML Port 2 || <br />
|-<br />
| 174 || N33 || DIQ2_D9 || IO_cmos1225 || DIQ bus, bit 9. LML Port 2 || <br />
|-<br />
| 175 || N31 || DIQ2_D8 || IO_cmos1225 || DIQ bus, bit 8. LML Port 2 || <br />
|-<br />
| 176 || M32 || DIQ2_D7 || IO_cmos1225 || DIQ bus, bit 7. LML Port 2 || <br />
|-<br />
| 177 || L33 || DIGPRVDD1 || DVDD || Digital Pad Ring power supply for pre-driver || <br />
|-<br />
| 178 || M30 || DIQ2_D6 || IO_cmos1225 || DIQ bus, bit 6. LML Port 2 || <br />
|-<br />
| 179 || K34 || DIQ2_D5 || IO_cmos1225 || DIQ bus, bit 5. LML Port 2 || <br />
|-<br />
| 180 || L31 || DIQ2_D4 || IO_cmos1225 || DIQ bus, bit 4. LML Port 2 || <br />
|-<br />
| 181 || K32 || DIQ2_D3 || IO_cmos1225 || DIQ bus, bit 3. LML Port 2 || <br />
|-<br />
| 182 || J33 || DIGPRGND1 || DGND || Digital Pad Ring ground for pre-driver || <br />
|-<br />
| 183 || K30 || DIQ2_D2 || IO_cmos1225 || DIQ bus, bit 2. LML Port 2 || <br />
|-<br />
| 184 || J31 || DIQ2_D1 || IO_cmos1225 || DIQ bus, bit 1. LML Port 2 || <br />
|-<br />
| 185 || H32 || DIGPRVDD2 || DVDD || Digital Pad Ring supply for post-driver || <br />
|-<br />
| 186 || H30 || DIQ2_D0 || IO_cmos1225 || DIQ bus, bit 0. LML Port 2 || <br />
|-<br />
| 187 || G31 || DIGPRGND2 || pad gnd || Digital Pad Ring ground for post-driver || <br />
|-<br />
| 188 || F32 || UNUSED || - || - || <br />
|-<br />
| 189 || G29 || UNUSED || - || - || <br />
|-<br />
| 190 || F30 || SDIO || IO_cmos1225 || Serial port data input-output in 3 wire mode, Serial port data input in 4 wire mode, CMOS || <br />
|-<br />
| 191 || E31 || UNUSED || - || - || <br />
|-<br />
| 192 || D32 || UNUSED || - || - || <br />
|-<br />
| 193 || C31 || UNUSED || - || - || <br />
|-<br />
| 194 || D30 || UNUSED || - || - || <br />
|-<br />
| 195 || E29 || UNUSED || - || - || <br />
|-<br />
| 196 || F28 || SDO || out_cmos1225 || Serial port data output, CMOS || <br />
|-<br />
| 197 || C29 || SCLK || in_cmos1225 || Serial port clock, positive edge sensitive, CMOS || <br />
|-<br />
| 198 || D28 || SEN || in_cmos1225 || Serial port enable, active low, CMOS || <br />
|-<br />
| 199 || E27 || RESET || in_cmos1225 || Hardware reset, active low, CMOS level || <br />
|-<br />
| 200 || F26 || UNUSED || - || - || <br />
|-<br />
| 201 || C27 || SCL || IO_cmos1225 || uControler || <br />
|-<br />
| 202 || D26 || SDA || IO_cmos1225 || uControler || <br />
|-<br />
| 203 || E25 || GND_SPI_BUF || digital gnd || GND – SPI buffer || <br />
|-<br />
| 204 || F24 || VDD_SPI_BUF || digital supply || 1.25V supply – SPI buffer || <br />
|-<br />
| 205 || C25 || VDD12_DIG || digital supply || output 1.2V supply for digital LDO || <br />
|-<br />
| 206 || D24 || VDD18_DIG || digital supply || 1.8V supply for digital LDO || <br />
|-<br />
| 207 || E23 || UNUSED || - || - || <br />
|-<br />
| 208 || F22 || tstdo<1> || out_cmos1225 || digital output test pin || <br />
|-<br />
| 209 || C23 || GND_DIG || digital gnd || GND for the digital LDO || <br />
|-<br />
| 210 || D22 || tstdo<0> || out_cmos1225 || digital output test pin || <br />
|-<br />
| 211 || B22 || tstao || out_cmos1225 || analogue test pin || <br />
|-<br />
| 212 || E21 || VDD18_VCO_CGEN || analogue supply || &nbsp;1.8V supply – VCO CLKGEN || <br />
|-<br />
| 213 || C21 || VDD14_VCO_CGEN || analogue supply || 1.4V supply – VCO CLKGEN || <br />
|-<br />
| 214 || F20 || VDD_CP_CGEN || analogue supply || 1.25V supply – Charge Pump – CLKGEN || <br />
|-<br />
| 215 || A21 || UNUSED || - || - || <br />
|-<br />
| 216 || D20 || GND_DIV_CGEN || analogue gnd || GND –frequency divider – CLKGEN || <br />
|-<br />
| 217 || B20 || GND_CP_CGEN || analogue gnd || GND –Charge Pump – CLKGEN || <br />
|-<br />
| 218 || E19 || VDD_DIV_CGEN || analogue supply || 1.25V supply – frequency divider – CLKGEN || <br />
|-<br />
| 219 || C19 || UNUSED || - || - || <br />
|-<br />
| 220 || F18 || vr_rext || in || external 10 kOhm accurate reference resistor || <br />
|-<br />
| 221 || D18 || UNUSED || - || - || <br />
|-<br />
| 222 || B18 || DGND_CGEN || digital gnd || GND – CLKGEN || <br />
|-<br />
| 223 || A17 || DVDD_CGEN || digital supply || 1.25V supply- Digital supply for CLK GEN || <br />
|-<br />
| 224 || C17 || UNUSED || - || - || <br />
|-<br />
| 225 || E17 || VDD18_BIAS || analogue supply || 1.8V supply – Bias || <br />
|-<br />
| 226 || B16 || VDD_TPAD_TRF || analogue supply || 1.25V supply – TX PAD || <br />
|-<br />
| 227 || D16 || VDD18_TRF || analogue supply || 1.8V supply – TX RF || <br />
|-<br />
| 228 || F16 || UNUSED || - || - || <br />
|-<br />
| 229 || C15 || UNUSED || - || - || <br />
|-<br />
| 230 || E15 || UNUSED || - || - || <br />
|-<br />
| 231 || B14 || pa2on_2 || out || PA driver output RF pad PAD2, Channel 2 || <br />
|-<br />
| 232 || D14 || UNUSED || - || - || <br />
|-<br />
| 233 || A13 || pa2op_2 || out || PA driver output RF pad PAD2, Channel 2 || <br />
|-<br />
| 234 || F14 || UNUSED || - || - || <br />
|-<br />
| 235 || C13 || UNUSED || - || - || <br />
|-<br />
| 236 || B12 || pa1op_2 || out || PA driver output RF pad PAD1, Channel 2 || <br />
|-<br />
| 237 || E13 || UNUSED || - || - || <br />
|-<br />
| 238 || D12 || UNUSED || - || - || <br />
|-<br />
| 239 || C11 || pa1on_2 || out || PA driver output RF pad PAD1, Channel 2 || <br />
|-<br />
| 240 || F12 || UNUSED || - || - || <br />
|-<br />
| 241 || B10 || pa2on_1 || out || PA driver output RF pad PAD2, Channel 1 || <br />
|-<br />
| 242 || A9 || pa2op_1 || out || PA driver output RF pad PAD2, Channel 1 || <br />
|-<br />
| 243 || E11 || UNUSED || - || - || <br />
|-<br />
| 244 || D10 || UNUSED || - || - || <br />
|-<br />
| 245 || C99 || UNUSED || - || - || <br />
|-<br />
| 246 || B8 || pa1op_1 || out || PA driver output RF pad PAD1, Channel 1 || <br />
|-<br />
| 247 || A7 || pa1on_1 || out || PA driver output RF pad PAD1, Channel 1 || <br />
|-<br />
| 248 || F10 || UNUSED || - || - || <br />
|-<br />
| 249 || E9 || UNUSED || - || - || <br />
|-<br />
| 250 || D8 || UNUSED || - || - || <br />
|-<br />
| 251 || C7 || GND_TLOBUF_TRF || analogue gnd || Ground for TX LO buffers || <br />
|-<br />
| 252 || A5 || UNUSED || - || - || <br />
|-<br />
| 253 || F8 || VDD_TLOBUF_TRF || analogue supply || 1.25V supply – TX LO BUFFER || <br />
|-<br />
| 254 || D6 || VDDO_TLOBUF_TRF || analogue supply || || <br />
|-<br />
| 255 || C5 || UNUSED || - || - || <br />
|-<br />
| 256 || B4 || UNUSED || - || - || <br />
|-<br />
| 257 || E5 || xoscin_tx || in || TX XOSC buffer input || <br />
|-<br />
| 258 || C3 || UNUSED || - || - || <br />
|-<br />
| 259 || F6 || GND_TXBUF || analogue gnd || GND supply – TX XOSC buffer || <br />
|-<br />
| 260 || B2 || UNUSED || - || - || <br />
|-<br />
| 261 || D4 || UNUSED || - || - || <br />
|-<br />
|}<br />
<br />
==Typical application==<br />
===RF section example===<br />
[[File:Lms7002m-typical-rf-application-circuit.png|center|550px|LMS7002M in a typical RF application circuit]]<br />
<br />
A typical application circuit of the LMS7002M is given above. Note that only the RF part of a single MIMO TRX chain is shown. More details can be found in the LMS7002M evaluation board schematics.<br />
<br />
===Digital interface configuration example===<br />
[[File:Lms7002m-typical-digital-interface-configuration.png|center|550px|LMS7002M in a typical digital interface configuration]]<br />
<br />
The above figure shows one useful example of clock generation and distribution as well as interfacing the LMS7002M to a digital BB modem. Note that interface control signals such as ENABLE, TXNRX, IQSEL are not shown for clarity. As can be seen, CLKPLL block generates a 491.52 MHz (integer multiple of 61.44 MHz) clock. CLKPLL output is divided by a programmable divider (division set to 4 in this example) to construct a 122.88 MHz clock driving DACs, TXTSP, and the TX part of LimeLight™. Similarly, CLKPLL output is divided by fixed division of 4 to construct 122.88 MHz clock driving ADCs, RXTSP, and the RX part of LimeLight™. Interpolation and decimation are both set to 2. This configuration provides a 245.76 MS/s double data rate (DDR) interface to the BB modem. This translates into the overall system performance as below:<br />
* TX/RX IF bandwidth: 20MHz<br />
* TX/RX RF bandwidth: 40MHz<br />
* Digital interpolation image suppression: 60dB<br />
* DACs analog image suppression: 72dB<br />
* ADCs analog alias suppression: 43dB assuming no off chip filtering<br />
* Digital decimation alias suppression: 60dB<br />
<br />
==Ordering information==<br />
{| class="wikitable"<br />
!Model !! Temperature range range !! Package description<br />
|-<br />
|LMS7002M || -40&deg;C to +85&deg;C || 261-pin aQFN<br />
|-<br />
|LMS7002M-REEL || -40&deg;C to +85&deg;C || 261-pin aQFN<br />
|-<br />
|LMS7002M-EVB || || Evaluation board<br />
|}<br />
<br />
==Disclaimer==<br />
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Lime Microsystems products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Lime Microsystems hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRRANTIES OF MERCHANTABILITY, NON-INFRIGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Lime Microsystems shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Lime Microsystems had been advised of the possibility of the same. Lime Microsystems assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties. Lime Microsystems products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Lime Microsystems products in Critical Applications.<br />
<br />
==Document Version==<br />
Based on LMS7002M Datasheet v2.8.0.<br />
<br />
Changes since document generation:<br />
* Minor typographical and grammatical changes.<br />
<br />
{{LimeMicro}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=LimeMicro:LMS7002M_Datasheet&diff=828
LimeMicro:LMS7002M Datasheet
2016-06-03T14:18:12Z
<p>Ghalfacree: Initial page creation and content transfer.</p>
<hr />
<div>==Features summary==<br />
* Field Programmable Radio Frequency (FPRF) chip<br />
* Dual transceiver, ideal for MIMO<br />
* User programmable on-the-fly<br />
* Continuous coverage of the 100 kHz - 3.8 GHz RF frequency range<br />
* Digital interface to baseband with on-chip integrated 12 bit D/A and A/D converters<br />
* Programmable RF modulation bandwidth up to 160 MHz using analog interface<br />
* Programmable RF modulation bandwidth up to 60 MHz using digital interface<br />
* Supports both TDD and full duplex FDD<br />
* LimeLight™ digital IQ interface – JEDEC JESD207 TDD and FDD compliant<br />
* Transceiver Signal Processor block employs advanced techniques for enhanced performance<br />
* Single chip supports 2x2 MIMO. Multiple chips can be used to implement higher order MIMO<br />
* On-chip RF calibration circuitry<br />
* Fully differential baseband signals, analog IQ<br />
* Few external components<br />
* Low voltage operation, 1.25 V, 1.4 V, and 1.8 V. Integrated LDOs to run on a single 1.8 V supply voltage<br />
* On-chip integrated microcontroller for simplified calibration, tuning and control<br />
* Integrated clock PLL for flexible clock generation and distribution<br />
* User definable analogue and digital filters for customised filtering<br />
* RF and baseband Received Signal Strength Indicator (RSSI)<br />
* 261-pin aQFN 11.5x11.5 mm package<br />
* Power-down option<br />
* Serial port interface<br />
* Low power consumption, typically 880 mW in full 2x2 MIMO mode (550 mW in SISO mode) using external LDOs<br />
* Multiple bypass modes for greater flexibility<br />
<br />
==Applications==<br />
* Broadband wireless communications <br />
* GSM, CDMA2000, TD-SCDMA, WCDMA/HSPA, LTE<br />
* IEEE® xxx.xxx radios<br />
* Wi-Fi operating in the Whitespace frequencies<br />
* Software Defined Radio (SDR)<br />
* Cognitive Radio<br />
* Unmanned Aerial Vehicle (UAV)<br />
* Other Whitespace applications<br />
<br />
==Functional block diagram==<br />
[[File:Lms7002m-functional-block-diagram.png|center|550px|LMS7002M functional block diagram]]<br />
<br />
==General description==<br />
The LMS7002M is a fully-integrated, multi-band, multi-standard RF transceiver that is highly programmable. It combines Low Noise Amplifiers (RXLNA), TX Power Amplifier Drivers (TXPAD) receiver/transmitter (RX/TX) mixers, RX/TX filters, synthesisers, RX gain control, TX power control, analogue-to-digital and digital-to-analogue converters (ADC/DACs) and has been designed to require very few external components.<br />
<br />
The top level architecture of LMS7002M transceiver is shown in the [[#Functional_block_diagram|functional block diagram]]. The chip contains two transmit and two receive chains for achieving a Multiple In Multiple Out (MIMO) platform. Both transmitters share one PLL and both receivers share another. Transmit and receive chains are all implemented as Zero Intermediate Frequency (Zero IF or ZIF) architectures providing up to 160MHz RF modulation bandwidth (equivalent to 80MHz baseband IQ bandwidth). For the purpose of simplifying this document, the explanation for the functionality and performance of the chip is based on one transmit and one receive circuitry, given that the other two work in exact the same manner.<br />
<br />
On the transmit side, In-phase and Quadrature IQ DAC data samples from the base band processor are provided to the LMS7002M via the LimeLight™ digital IQ interface. LimeLight™ implements the JESD207 standard IQ interface protocol as well as de facto IQ multiplexed standard. JESD207 is Double Data Rate (DDR) by definition. In IQ multiplexed mode LimeLight™ also supports Single Data Rate (SDR). The IQ samples are then preprocessed by the digital Transceiver Signal Processor (TSP) for minimum analogue and RF distortion and applied to the on-chip transmit DACs. The DACs generate analogue IQ signals which are provided for further processing to the analogue/RF section. Transmit low-pass filters (TXLPF) remove the images generated by zero-hold effect of the DACs as well as the DAC out-of-band noise. The analogue IQ signals are then mixed with the transmit PLL (TXPLL) output to produce a modulated RF signal. This RF signal is then amplified by one of two separate, selectable power amplifier drivers and two open-drain differential outputs are provided as RF output for each MIMO path.<br />
<br />
The LMS7002M provides an RF loopback option which enables the TX RF signal to be fed back into the baseband for calibration and test purposes. The RF loopback signal is amplified by the loopback amplifier in order to increase the dynamic range of the loop.<br />
<br />
There are two additional loopback options implemented: one is an analogue baseband (BB) loopback; the other is a digital loopback (DLB). The analogue loop back is intended for testing while the DLB can be used to verify the LMS7002M connectivity to baseband, FPGA, DSP, or any other digital circuitry.<br />
<br />
On the receive side three separate inputs are provided, each with a dedicated LNA optimised for narrow or wideband operation. Each port RF signal is first amplified by a programmable low-noise amplifier (RXLNA). The RF signal is then mixed with the receive PLL (RXPLL) output to directly down-convert to baseband. AGC steps can be implemented by a BB trans-impedance amplifier (RXTIA) prior to the programmable bandwidth low pass channel select/antialias filters (RXLPF). The received IQ signal is further amplified by a programmable gain amplifier (RXPGA). DC offset is applied at the input of RXTIA to prevent saturation and to preserve the receive ADC’s dynamic range. The resulting analogue receive IQ signals are converted into the digital domain with on-chip receive ADCs. Following the ADCs, the signal conditioning is performed by the digital Transceiver Signal Processor (TSP) and the resulting signals are then provided to the BB via the LimeLight™ digital IQ interface.<br />
<br />
The analog receive signals can also be provided off-chip at the RXOUTI and RXOUTQ pins by closing the RXOUT switch. In this case it is possible to power down the on chip ADCs/TSP and use external parts, which can be very useful for more resource-demanding applications or where higher signal resolution is required. A similar option is also available on the TX side where the analogue signal can be processed by external components: the on-chip DACs/TSP can be powered down and analogue inputs can be provided at TXINI and TXINQ pins.<br />
<br />
==General specifications==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Operating temperature range || -40 || 25 || 85 || °C || <br />
|-<br />
|Storage temperature range || -65 || 25 || 125 || °C || <br />
|-<br />
|Operating frequency range || 30<br />0.1 || || 3800<br />3800 || MHz || <br />Extended by TSP NCOs<br />
|-<br />
|RF modulation bandwidth || || || 60<br />160 || MHZ || Through digital interface<br />Through analogue interface<br />
|-<br />
|Frequency resolution || || || 24.8 || Hz || Using 52MHZ PLL reference clock<br />
|-<br />
|Analogue supply voltage, high (VDDAH) || 1.71 || 1.8 || 1.89 || V || Used for TXPAD<br />
|-<br />
|Analogue supply voltage, medium (VDDAM) || 1.33 || 1.4 || 1.47 || V || Generated using integrated low-dropout regulators (LDOs)<br />
|-<br />
|Analogue supply voltage, low (VDDAL) || 1.2 || 1.25 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Digital core supply voltage || 1.1 || 1.2 || 1.3 || V || <br />
|-<br />
|TX supply current || || 350 || || mA || At -7 dBm output power, 2x2 MIMO, including the DACs and TSP<br />
|-<br />
|RX supply current || || 420 || || mA || For 2x2 MIMO, including the ADCs and TSP<br />
|-<br />
|Maximum RF output power || || 0 || || dBm || Continuous wave<br />
|-<br />
|PLL reference clock || 10 || || 52 || MHz ||<br />
|-<br />
|Interpolation/decimation digital filters stop band suppression || || || 108 || dB || <br />
|}<br />
<br />
==General RF specifications==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|RF channel frequency range || 30<br />0.1 || || 3800<br />3800 || MHz || <br />Extended by TSP NCOs<br />
|-<br />
|Transmit analogue input impedance || || 400 || || Ohms || Differential, programmable<br />
|-<br />
|Transmit load impedance at the output pins || || 40 || || Ohms || Differential, for maximum OIP3<br />
|-<br />
|Transmit differential I and Q input current || || 625 || || μA || Differential, common mode<br />
|-<br />
|Transmit gain control range || || 70 || || dB || TXTSP and TXPAD combined<br />
|-<br />
|Transmit gain control step || || 1 || || dB || <br />
|-<br />
|TX local oscillator (LO) leakage || || -60 || || dBc || Calibrated<br />
|-<br />
|RXLNAL frequency range || 0.1 || || 2000 || MHz || Narrowband tunable, set by external matching circuit<br />
|-<br />
|RXLNAH frequency range || 0.1 || || 3800 || MHz || Narrowband tunable, set by external matching circuit<br />
|-<br />
|RXLNAW frequency range || 0.1 || || 3800 || MHz || Broadband tunable, set by external matching circuit<br />
|-<br />
|Noise figure || || 2.0<br />2.5<br />3.5 || || dB || at 0.95GHz<br />at 2GHz<br />at 3.8GHz<br />
|-<br />
|2nd order input intercept point || || 50 || || dBm || Total receiver gain ~50 dB or more. Noise figure <3.5 dB in all bands. Two tone signals out of band.<br />
|-<br />
|3rd order input intercept point || || 4 || || dBM || Total receiver gain ~50 dB or more. Noise figure <3.5 dB in all bands. Two tone signals out of band.<br />
|-<br />
|Receive gain control range || || 70 || || dB || RXLNA, RXTIA, RXPGA, and RXTSP combined<br />
|-<br />
|Receive gain control step || 0.5 || 1 || 1.5 || dB || <br />
|}<br />
<br />
Two transmitter outputs (TXOUT1, TXOUT2) and three receiver inputs (RXINL, RXINH, RXINW) are provided to facilitate multi-band multi-standard operation. <br />
The functionality of the LMS7002M is fully controlled by a set of internal registers which can be accessed through a serial port and rapidly reprogrammed on the fly for advanced system architectures. In order to enable full duplex operation, LMS7002M contains two separate synthesisers (TXPLL, RXPLL), both usually driven from the same reference clock source PLLCLK.<br />
<br />
==Gain control==<br />
===TX gain control===<br />
[[File:Lms7002m-analogue-gain-control-architecture.png|center|550px|LMS7002M analogue/RF gain control architecture diagram.]]<br />
<br />
The LMS7002M transmitter has two programmable gain stages, where the TSP provides digital gain control and the TXPAD gives programmable gain of the RF signal.<br />
<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Digital TSP gain control range || || 15 || || dB || In steps of 1 LSB digital gain control<br />
|-<br />
|TXPAD gain control range || || 55 || || dB ||<br />
|-<br />
|TXPAD gain step size || || 1 || || dB || For the higher 10 steps<br />
|-<br />
|TXPAD gain step size || || 2 || || dB || For the lower 20 steps<br />
|}<br />
<br />
===RX gain control===<br />
[[File:Lms7002m-rx-gain-control-architecture.png|center|550px|LMS7002M RX gain control architecture diagram.]]<br />
<br />
The LMS7002M receiver has three gain control elements, RXLNA, RXTIA, and RXPGA. If required, additional gain control can be implemented by RXTSP in digital domain. RXLNA gain control consists of 30 dB with 1 dB steps at high gain settings and 3 dB steps at low gain settings for AGC when large adjacent channel blockers are present and a reduction in system noise figure (NF) is acceptable. RXTIA offers 3 dB of control range. RXTIA is intended for AGC steps needed to reduce system gain prior to the channel filters when large in band blockers are present. This gain can be under the control of the baseband or fixed on calibration. RXPGA provides gain control for the AGC if a constant RX signal level at the ADC input is required. It has a 32 dB gain range control in 1 dB steps.<br />
<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Digital TSP gain control range || || 15 || || dB || In steps of 1 LSB digital gain control<br />
|-<br />
|RXLNA gain control range || || 30 || || dB || 1 and 3 dB steps<br />
|-<br />
|RXTIA gain control range || || 3 || || dB || <br />
|-<br />
|RXPGA gain control range || || 32 || || dB || <br />
|-<br />
|RXPGA gain step size || || 1 || || dB || <br />
|}<br />
<br />
==Synthesisers==<br />
The LMS7002M has two low phase noise synthesisers to enable full-duplex operation, and both are capable of output frequencies up to 3.8 GHz. Each synthesiser uses a fractional-N PLL architecture. The same reference frequency can be used for both synthesisers and is flexible between 10 to 52 MHz clock frequency. The synthesisers produce complex outputs with levels suitable to drive IQ mixers in both the TX and the RX paths. The transmit PLL could also be routed via switches to the receive PLL so as to offer phase-coherent operation in TDD mode.<br />
<br />
===PLL reference clock===<br />
[[File:Lms7002m-pll-architecture.png|center|550px|LMS7002M PLL architecture diagram.]]<br />
The LMS7002M can accept clipped sine as well as CMOS level signals for the PLL reference clock. Both DC and AC coupling are supported as shown in Figure 5. Internal buffer self-biasing must be enabled for AC coupling mode. The PLL reference clock input can also be low voltage CMOS (<1.2V) which is implemented by lowering the clock buffer supply. <br />
<br />
====DC coupled====<br />
[[File:Lms7002m-pll-reference-clock-input-buffer-dc-coupled.png|center|550px|LMS7002M PLL reference clock input buffer, DC coupled.]]<br />
<br />
====AC coupled====<br />
[[File:Lms7002m-pll-reference-clock-input-buffer-ac-coupled.png|center|550px|LMS7002M PLL reference clock input buffer, AC coupled.]]<br />
<br />
===Synthesiser specifications===<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Output frequency range || 30 || || 3800 || MHz || <br />
|-<br />
|Reference amplitude || 0.2 || 0.8 || 2.5 || Vpp || At PVDD >2.5 V<br />
|-<br />
|Reference frequency || 10 || || 52 || MHz || For continuous LO frequency range<br />
|-<br />
|Frequency resolution || || || 2.4 || Hz || Using 52 MHz PLL reference clock<br />
|-<br />
|850 MHz Phase Noise<br />1 kHz offset<br />5 kHz offset<br />10 kHz offset<br />100 kHz offset<br />1 MHz offset<br />30 MHz offset || || <br />-96<br />-97<br />-99<br />-107<br />-131<br />-158 || || dBc/Hz || <br />
|-<br />
|2.0 GHz Phase Noise<br />1 kHz offset<br />5 kHz offset<br />10 kHz offset<br />100 kHz offset<br />1 MHz offset<br />30 MHz offset || || <br />-91<br />-92<br />-92<br />-102<br />-127<br />-158 || || dBc/Hz || <br />
|-<br />
|2.7 GHz Phase Noise<br />1 kHz offset<br />5 kHz offset<br />10 kHz offset<br />100 kHz offset<br />1 MHz offset<br />30 MHz offset || || <br />-87<br />-88<br />-92<br />-98<br />-123<br />-158 || || dBc/Hz || <br />
|-<br />
|3.5 GHz Phase Noise<br />1 kHz offset<br />5 kHz offset<br />10 kHz offset<br />100 kHz offset<br />1 MHz offset<br />30 MHz offset || || <br />-84<br />-85<br />-86<br />-89<br />-113<br />-152 || || dBc/Hz || <br />
|- <br />
|Reference spurious outputs || || -70 || -68 || dBc || <br />
|-<br />
|Other spurious outputs || || -60 || -55 || dBc || <br />
|-<br />
|850 MHz IQ phase error || || 0.8 || 1 || degrees || rowspan="4"|After calibration<br />
|-<br />
|2000 MHz IQ phase error || || 2 || || degrees<br />
|-<br />
|3500 MHz IQ phase error || || 3 || || degrees<br />
|-<br />
|IQ amplitude error || || ±0.1 || ±0.2 || dB<br />
|-<br />
|PLL setting time || || 50 || 150 || μS || Loop BW=70 kHz<br />
|}<br />
<br />
==RF ports==<br />
The LMS7002M has two transmitter outputs and three receiver inputs for each of the dual transceivers. The optimum transmitter output load is 40 Ω differential at the output pads. The final stage amplifiers are open drain and require +1.8V voltage supply. The receiver inputs are common-source with different inductive degeneration, optimised for different frequency bands. They need to be externally matched for optimised narrowband performance or broadband utilising a wideband transformer.<br />
<br />
==TX and RX low-pass filters==<br />
The LMS7002M integrates selective low-pass filters in both the TX and RX paths. These filters have a programmable pass band in order to provide more flexibility on the DAC/ADC clock frequency and also to provide adjacent channel rejection in the receive chain. The complete filtering function is a combination of analogue filtering and digital TSP filtering. RX analogue filters are tunable from 0.7 MHz to 80 MHz. The digital filters provide a lower pass band of 0.7 MHz. Using such mixed mode filtering (digital and analogue) provides 60 dB antialias performance and 40 dB adjacent channel rejection as the worst case scenario. The TX filtering chain pass band is tunable from 2 MHz to 80 MHz. When combined with TX digital filters the chain offers enhanced performance in a similar way to the RX analogue/digital filtering chain.<br />
<br />
===TX analogue filter chain===<br />
[[File:Lms7002m-tx-analogue-filter-chain.png|center|550px|LMS7002M TX analogue filter chain]]<br />
<br />
The transmitter baseband has three independently controlled low pass filter stages:<br />
# 4th order ladder filter (TXLPFLAD)<br />
# 1st order real pole filter (TXLPFS5)<br />
# 2nd order high-band filter (TXLPFH)<br />
<br />
The low-band filter (TXLPFL) path pass band is tunable from 2 MHz to 20 MHz and is comprised of two filter stages: 4th order low pass ladder filter (TXLPFLAD) and 1st order low pass real pole filter (TXLPFS5). The real pole stage filters the BB noise at the duplex frequency to meet the far-end noise specifications in some FDD systems. The high-band filter (TXLPFH) pass band is tunable from 20 MHz up to 80 MHz and is comprised of a single 2nd order low pass stage. Only one path (TXLPFL or TXLPH) can be active at the same time.<br />
<br />
===RX analogue filter chain===<br />
[[File:Lms7002m-rx-analogue-filter-chain.png|center|550px|LMS7002M RX analogue filter chain]]<br />
<br />
The receiver baseband has three independently controlled low pass filter stages:<br />
# 1st order single pole filter (RXTIA)<br />
# 2nd order low band filter (RXLPFL)<br />
# 2nd order high band filter (RXLPFH)<br />
<br />
The initial filtering is done by the transimpedance amplifier (RXTIA), which acts as a single-pole low-pass filter. The RXTIA output is routed to one of two filter stages. Low band filter pass band is tunable from 0.75 MHz up to 20 MHz. High band filter pass band is tunable from 20 MHz up to 80 MHz. Both low band and high band stages are 2nd order low pass filters. Paired with the RXTIA, these stages produce a 3rd order low pass filter response. Only one path (RXLPFL or RXLPH) can be active at the same time.<br />
<br />
===Analogue TX LPFH amplitude response===<br />
[[File:Lms7002m-analogue-tx-lpfh-amplitude.png|center|550px|LMS7002M analogue TX LPFH amplitude graph]]<br />
<br />
===Analogue TX LPFL amplitude response===<br />
[[File:Lms7002m-analogue-tx-lpfl-amplitude.png|center|550px|LMS7002M analogue TX LPFL amplitude graph]]<br />
<br />
===Analogue RX LPFH amplitude response===<br />
[[File:Lms7002m-analogue-rx-lpfh-amplitude.png|center|550px|LMS7002M analogue RX LPFH amplitude graph]]<br />
<br />
===Analogue RX LPFL amplitude response===<br />
[[File:Lms7002m-analogue-rx-lpfl-amplitude.png|center|550px|LMS7002M analogue RX LPFH amplitude graph]]<br />
<br />
==Transceiver signal processor==<br />
[[File:Lms7002m-tsp.png|center|550px|LMS7002M Transceiver Signal Processor (TSP) block diagram]]<br />
<br />
The LMS7002M includes a high digital gate count within the Transceiver Signal Processor (TSP) block. The function of the TSP is to employ advanced digital signal processing techniques to enhance the performance of the analogue/RF parts. This results in improved performance of the overall system and a saving on total current consumption. The TSP is placed between the data converters and the LimeLight™ digital IQ interface. Functionally, the [[#RXTSP structure|RX]] and [[#TXTSP structure|TX]] parts of the TSP are similar<br />
<br />
In both the TX and RX TSP blocks there are three general-purpose finite impulse response (FIR) filters, G.P. FIR 1, G.P. FIR 2, and G.P. FIR 3. The filter coefficients are fully programmable and the implementation does not force their impulse response to be symmetrical.<br />
<br />
On the TX side one of these filters could be used as a phase equaliser, which is a requirement in some communication standards such as CDMA2000. Another can be used to flatten the amplitude response of the TXLPF, while the third FIR could be used to further enhance the channel filtering function of the BB modem. If phase equalisation is not required then one filter can be used to minimise group delay variation of the analog TXLPF. Possible applications of the G.P. FIR filters on the RX side are similar. One could be used to minimise group delay variation of the analogue RXLPF while another could help to improve RXLPF adjacent channel rejection performance.<br />
<br />
The interpolation block within the TXTSP takes IQ data from the BB modem and increases the data sample rate. The advantages of having interpolation are as follows: for narrow band systems (GSM/EDGE) or even moderately broad band (WCDMA, CDMA2000) modulation standards the BB modem does not need to interpolate IQ data to the target system clock. The base band can provide output data at a much lower sample rate saving on power at the digital interface. Having a low data rate interface also simplifies the PCB design. However, the interpolator block generates data samples at the system clock rate, so the DACs run at a high sampling rate. As the DACs are running at a high frequency, it means that the quantisation noise is spread over a wider frequency range which results in a better overall SNR. Also, the image generated by the DAC zero hold effect is further away from the wanted signal hence the specification for the TXLPF can be relaxed.<br />
<br />
The reason for having decimation in the RXTSP is similar to that of interpolation in TXTSP. The ADCs can run at high frequency, and the specification of the RXLPF used as an anti-alias filter in this case is relaxed, the G.P. FIR improves adjacent channel rejection and the decimation circuit reduces the received data sample rate before sending the data to the BB modem.<br />
<br />
The two Numerically Controlled Oscillators (NCO) and digital complex mixer (CMIX) in the TXTSP and RXTSP paths enable the LMS7002M to run in low digital IF.<br />
<br />
Inverse sinc filters (INVSINC) within the TXTSP chain compensate for sinx/x amplitude roll off imposed by the DACs themselves.<br />
<br />
The Tx DC Corr block is used to cancel residual DC offset of TXLPF. It is also used to cancel TX LO leakage feed-through as mentioned earlier.<br />
<br />
There are three sources of the DC component at the RX output. These are the residual DC offset of the RXPGA and RXLPF, RX LO leakage feed-through and second order distortion (IP2). The Rx DC Corr blocks compensate for all of these sources of offset. The block is implemented as a real time tracking loop so any change of the RX DC due to either the signal level change, or due to RX gain change as well as any temperature effect will be tracked and cancelled automatically.<br />
<br />
The IQ Gain Corr and IQ Phase Corr blocks correct IQ imbalance in both TXTSP and RXTSP in order to minimise the level of unwanted sideband (image) component.<br />
<br />
The last stage in the RXTSP path is a digital implementation of an Adaptive Gain Control (AGC) loop. Assuming that the BB modem does not require 12-bit full scale ADC outputs, the digital AGC block can provide a certain level of automatic gain control before the BB involves RF and IF gain stages.<br />
<br />
===RXTSP structure===<br />
[[File:Lms7002m-tsp-rx.png|center|550px|LMS7002M RXTSP structure diagram]]<br />
<br />
===TXTSP structure===<br />
[[File:Lms7002m-tsp-tx.png|center|550px|LMS7002M TXTSP structure diagram]]<br />
<br />
===IQ gain correction===<br />
[[File:Lms7002m-tsp-iq-gain-correction.png|center|550px|LMS7002M IQ gain correction diagram]]<br />
This block implements the following equation:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{Iout} = \mathit{Iin} * \mathit{G\_I} \\<br />
\mathit{Qout} = \mathit{Qin} * \mathit{G\_Q}<br />
\end{align}<br />
</math><br />
<br />
<math>\mathit{G\_I}</math> and <math>\mathit{G\_Q}</math> are programmable correction factors which are altered by the BB modem to minimise any unwanted sideband component. The BB modem can combine IQ gain correction and digital gain control using the same module by calculating <math>\mathit{G\_I}</math> and <math>\mathit{G\_Q}</math> in the following way:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{G\_I} = \mathit{G\_I\_corr} * \mathit{G\_digi}\\<br />
\mathit{G\_Q} = \mathit{G\_Q\_corr} * \mathit{G\_digi}<br />
\end{align}<br />
</math><br />
<br />
where <math>\mathit{G\_I\_corr}</math> and <math>\mathit{G\_Q\_corr}</math> are IQ gain correction factors and <math>\mathit{G\_digi}</math> is the desired digital gain.<br />
<br />
===IQ phase correction===<br />
[[File:Lms7002m-tsp-iq-phase-correction.png|center|550px|LMS7002M IQ phase correction diagram]]<br />
<br />
IQ phase correction is in fact equivalent to vector rotation. If the quadrature phase error is <math>\alpha</math> then the I and Q vectors are both rotated by <math>\alpha/2</math> but in opposite directions, hence IQ outputs of the corrector circuit are 90&deg; phase shifted. IQ phase correction equations are given below:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{Iout} = \mathit{Iin} + \mathit{Qin} * \tan \biggl( {\alpha \over 2} \biggr) \\<br />
\mathit{Qout} = \mathit{Qin} + \mathit{Iin} * \tan \biggl( {\alpha \over 2} \biggr)<br />
\end{align}<br />
</math><br />
<br />
The value of <math>\tan(\alpha/2)</math> should be stored in the configuration register as a programmable correction parameter. The BB modem should adjust this value to minimise the unwanted side band component. The BB modem can also use the following approximation formula:<br />
<br />
<math><br />
\begin{align}<br />
\tan \biggl( {\alpha \over 2} \biggr) \approx {\alpha \over 2}<br />
\end{align}<br />
</math><br />
<br />
when <math>\alpha</math> is small, which is usually the case. The IQ phase corrector of the LMS7002M is designed to correct an IQ phase error up to ±20&deg;.<br />
<br />
===TX DC correction===<br />
[[File:Lms7002m-tsp-dc-offset.png|center|550px|LMS7002M DC offset diagram]]<br />
<br />
DC offset correction in the TXTSP path is achieved by using the following equation:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{Iout} = \mathit{Iin} + \mathit{DC_I} \\<br />
\mathit{Qout} = \mathit{Qin} + \mathit{DC_Q}<br />
\end{align}<br />
</math><br />
<br />
Here <math>\mathit{DC_I}</math> and <math>\mathit{DC_Q}</math> are programmable DC offset correction parameters which the BB modem should adjust to minimise the TX DC and TX LO leakage feed-through.<br />
<br />
===RX DC correction===<br />
[[File:Lms7002m-tsp-rx-dc-correction.png|center|550px|LMS7002M RX DC correction diagram]]<br />
<br />
As mentioned previously, there are multiple reasons for DC to appear at the RX output. The most difficult to correct, in a static manner, is the second order distortion (IP2) component which changes with the RX input level as well as the RX gain set up. A compensation loop running in real time is required to track and correct the DC at the RX output. A simple digital implementation of such a loop is given above.<br />
<br />
The averaging (COMB) filter calculates the DC of the corrector input and subtracts it to cancel out the offset. The loop is running all the time so any change of the RX DC due to the signal level change, RX gain change, or temperature will be tracked and cancelled automatically. The only programmable parameter in the loop is DCAVG which defines the averaging window size.<br />
<br />
===Inverse SINC filter===<br />
The inverse sinc filter compensates for sinx/x amplitude roll off imposed by the DAC. The filter is designed to compensate from DC to 0.35fs where fs is the DAC sampling frequency. Impulse and amplitude responses are shown in Figure 19 and Figure 20.a respectively. Figure 20.b plots the equivalent DAC amplitude response with the inverse sinc function compensation applied. The in band (0 – 0.35fs ) amplitude ripple is less than +/- 0.04 dB.<br />
<br />
====INVSINC impulse response====<br />
<nowiki>h( 0) = 0.0101318 = h( 4)<br />
h( 1) = -0.0616455 = h( 3)<br />
h( 2) = 0.855469</nowiki><br />
<br />
====INVSINC (a) and equivalent DAC (b) amplitude response====<br />
[[File:Lms7002m-tsp-invsinc-dac-amplitude.png|center|550px|LMS7002M INVSINC (a) and corresponding DAC (b) amplitude response graph]]<br />
<br />
===Complex mixer===<br />
The complex mixer used in the RXTSP and TXTSP is designed to implement the following set of equations:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{Iout} = \mathit{Iin} \cos \omega _{\mathit{c}} \mathit{t} \mp \mathit{Qin} \sin \omega_{\mathit{c}} \mathit{t} \\<br />
\mathit{Qout} = \mathit{Iin} \sin \omega _{\mathit{c}} \mathit{t} + \mathit{Qin} \cos \omega_{\mathit{c}} \mathit{t}<br />
\end{align}<br />
</math><br />
<br />
where <math>\mathit{Iin}</math> and <math>\mathit{Qin}</math> are provided from the IQ pre-processing stages while cosine and sine signals are generated by the NCO. An option to choose the sign in the mixing equations is implemented which gives the ability to do up-mixing or down-mixing in both TX and RX chains.<br />
<br />
===Numerically-controlled oscillator===<br />
[[File:Lms7002m-tsp-nco-architecture.png|center|550px|LMS7002M NCO architecture diagram]]<br />
<br />
The quadrature carrier signal, required to implement low digital IF, is generated by the local NCO. The internal NCO design is based on a Direct Digital Frequency Synthesis (DDFS) algorithm with a 32-bit phase accumulator with 19-bit phase precision and provides 14-bit digital sine and cosine waveforms with spurious performance better than –114 dBc.<br />
<br />
The carrier frequency<math>\mathit{f_c}</math> generated by the NCO is defined using the following formula:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{f_c} = {\mathit{fcw} \over 2^{32}} \mathit{f_{clk}}<br />
\end{align}<br />
</math><br />
<br />
where <math>\mathit{fcw}</math> represents the decimal value of the 32-bit frequency control word and <math>\mathit{f_{clk}}</math> is the NCO clock frequency.<br />
<br />
Carrier phase offset can also be adjusted using the 16-bit configuration parameter <math>\mathit{pho}</math>. The carrier phase shift is calculated as follows:<br />
<br />
<math><br />
\begin{align}<br />
\phi = 2 \pi {\mathit{pho} \over 2^{16}}<br />
\end{align}<br />
</math><br />
<br />
with <math>\mathit{pho}</math> being the decimal value stored in the carrier phase offset register.<br />
<br />
Both frequency control and phase control words are easily accessible via SPI, therefore NCOs can be modulated by direct symbol insertion. Up to 16FSK or 16PSK modulations are supported.<br />
<br />
===Interpolation===<br />
[[File:Lms7002m-tsp-interpolation-filters.png|center|550px|LMS7002M interpolation filters diagram]]<br />
<br />
Interpolation within the TXTSP channel is implemented using the chain of five fixed coefficients half band FIR filters. Each sub-filter in the chain interpolates by two. The interpolation ratio of the overall filter is set by selecting one of the sub-filter outputs and adjusting the clock rates accordingly. Hence, the interpolation ratio <math>\mathit{K}</math> can be programmed to be:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{K} = 1, 2, 4, 8, 16, \mathrm{or}\ 32<br />
\end{align}<br />
</math><br />
<br />
Interpolation by 1 is achieved by bypassing all the interpolation filters. The filters are designed to provide a wide signal pass band from DC to <math>\mathit{f_p}</math> where:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{f_p} = x \cdot {\mathit{f_{clk}} \over \mathit{K}}<br />
\end{align}<br />
</math><br />
<br />
Scaling factor <math>x</math> in the equation above, for <math>\mathit{K}</math> = 2, 4, 8, 16, or 32, should be set to one of the following values:<br />
<br />
: <math>x</math> <= 0.27 for >= 108dB interpolation image suppression<br />
: <math>x</math> <= 0.30 for >= 75dB interpolation image suppression<br />
: <math>x</math> <= 0.32 for >= 60dB interpolation image suppression<br />
<br />
<math>x</math> can be used to trade off interpolation image suppression for the interpolation filter pass band.<br />
<br />
For <math>\mathit{K}=1</math>, <math>x</math> should be set to <math>x < 0.5</math> to limit the signal BW below the Nyquist limit, making room for analogue TX filters to operate. There is no interpolation image in this case hence more flexibility to set <math>x</math> for higher IF/RF bandwidth.<br />
<br />
Only two different configurations are used within the filtering chain of the NCO implementation: HB1 and HB2. The [[#HB1_impulse_response|impulse]] and [[#HB1_amplitude_response|amplitude response]] of HB1 are provided below. The remaining three filters (HB2A, HB2B and HB2C) are all the same with their [[#HB2_impulse_response|coefficients]] and [[#HB2_amplitude_response|amplitude response]] also given below. The overall interpolator can provide image suppression of better than –108 dB with negligible amplitude distortion (pass band ripple less than 10<sup>-5</sup> dB).<br />
<br />
====HB1 impulse response====<br />
<nowiki>h( 0) = -4.673e-05 = h(30)<br />
h( 1) = 0 = h(29)<br />
h( 2) = 0.000392914 = h(28)<br />
h( 3) = 0 = h(27)<br />
h( 4) = -0.00181007 = h(26)<br />
h( 5) = 0 = h(25)<br />
h( 6) = 0.00600147 = h(24)<br />
h( 7) = 0 = h(23)<br />
h( 8) = -0.0160789 = h(22)<br />
h( 9) = 0 = h(21)<br />
h(10) = 0.0378866 = h(20)<br />
h(11) = 0 = h(19)<br />
h(12) = -0.0882454 = h(18)<br />
h(13) = 0 = h(17)<br />
h(14) = 0.3119 = h(16)<br />
h(15) = 0.5</nowiki><br />
<br />
====HB1 amplitude response====<br />
[[File:Lms7002m-tsp-hb1-amplitude-response.png|center|550px|LMS7002M HB1 amplitude response graph]]<br />
<br />
====HB2 impulse response====<br />
<nowiki>h( 0) = -0.00164032 = h(14)<br />
h( 1) = 0 = h(13)<br />
h( 2) = 0.0138855 = h(12)<br />
h( 3) = 0 = h(11)<br />
h( 4) = -0.0630875 = h(10)<br />
h( 5) = 0 = h( 9)<br />
h( 6) = 0.300842 = h( 8)<br />
h( 7) = 0.5</nowiki><br />
<br />
<br />
====HB2 amplitude response====<br />
[[File:Lms7002m-tsp-hb2-amplitude-response.png|center|550px|LMS7002M HB2 amplitude response graph]]<br />
<br />
===Decimation===<br />
[[File:Lms7002m-tsp-decimation-filters.png|center|550px|LMS7002M decimation filter chain diagram]]<br />
<br />
The decimation function is implemented using the same filters as in the case for interpolation although the hardware is simplified slightly by taking advantage of only having to provide every second sample at the sub-filters output. Decimation ratio <math>\mathit{K}</math> can be programmed to be:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{K} = 1, 2, 4, 8, 16, \mathrm{or}\ 32<br />
\end{align}<br />
</math><br />
<br />
Decimation by 1 is achieved by bypassing all the decimation filters. Decimator performance is the same as the performance of the interpolator i.e. pass band is:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{f_p} = x \cdot {\mathit{f_{clk}} \over \mathit{K}}<br />
\end{align}<br />
</math><br />
<br />
As before, scaling factor <math>x</math> in the equation above, for <math>\mathit{K}</math> = 2, 4, 8, 16, or 32, should be set to one of the following values:<br />
<br />
: <math>x</math> <= 0.27 for >= 108dB decimation alias suppression<br />
: <math>x</math> <= 0.30 for >= 75dB decimation alias suppression<br />
: <math>x</math> <= 0.32 for >= 60dB decimation alias suppression<br />
<br />
Again, <math>x</math> can be used to trade off decimation alias suppression for the decimation filter pass band.<br />
<br />
For <math>\mathit{K}=1</math>, <math>x</math> should be set to <math>x < 0.5</math> to limit the signal BW below the Nyquist limit, making room for additional filtering in BB, if required. There is no decimation alias in this case hence more flexibility to set <math>x</math> for higher IF/RF bandwidth.<br />
<br />
===General-purpose FIR filters===<br />
[[File:Lms7002m-tsp-fir-memory-banks.png|center|550px|LMS7002M FIR memory bank diagram]]<br />
<br />
The LMS7002M features general-purpose filters 1 and 2, which are based on a Multiply and Accumulate (MAC) FIR architecture. They can implement up to a 40-tap filtering function and the coefficients are fully programmable via SPI. The hardware implementation does not impose the constraint for the filter impulse response to be symmetrical hence the filter phase response can but does not need to be ideally linear. Therefore it can be used in general filtering as well as nonlinear applications which can be used to implement phase equalisation.<br />
<br />
The filter coefficients are stored in five 8x16-bit internal memory banks as two’s complement signed integers, where <math>\mathit{L}</math> is related to the filter length <math>\mathit{N}</math> as follows:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{L} = \left[ {\mathit{N} \over 5} \right]<br />
\end{align}<br />
</math><br />
<br />
Grey locations in the above memory bank diagram highlight the memory registers which are set to zero for <math>5 \mathit{L} > \mathit{N}</math>. Evidently, the number of the filter taps <math>\mathit{N}</math> is limited by the size of the coefficients memory to:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{N} \le 5 * 8 = 40<br />
\end{align}<br />
</math><br />
<br />
The following relationship should be satisfied:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{L} \le \mathit{K}<br />
\end{align}<br />
</math><br />
<br />
<math>\mathit{K}</math> being the interpolation or decimation ratio, for the MAC hardware to be able to produce output samples on time.<br />
<br />
General purpose FIR filter 3 hardware is composed of three filters (each equivalent to G.P. FIR 1 or 2) running in parallel in order to increase its processing power, hence it can implement the filters with:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{N} \le 3 * 40 = 120<br />
\end{align}<br />
</math><br />
<br />
It can be used as a channel select filter or for any other purpose which requires a larger number of filtering taps.<br />
<br />
===Received signal strength indicators===<br />
A digital received signal strength indicator (RSSI) circuit calculates the level of the received complex signal (<math>\mathit{I} + \mathrm{j}\mathit{Q}</math>) as follows:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{RSSI} = \sqrt{\mathit{I}^2 + \mathit{Q}^2}<br />
\end{align}<br />
</math><br />
<br />
The following approximation of the square root is implemented in the chip:<br />
<br />
<math><br />
\begin{align}<br />
\sqrt{a^2 + b^2} \approx \mathrm{max} \left( \left( \left( \mathit{M} - 0.125 \mathit{M} \right) + 0.5 \mathit{N} \right) , \mathit{M} \right)<br />
\end{align}<br />
</math><br />
<br />
where:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{M} = \mathrm{max} \left( \vert a \vert , \vert b \vert \right) \\<br />
\mathit{N} = \mathrm{min} \left( \vert a \vert , \vert b \vert \right)<br />
\end{align}<br />
</math><br />
<br />
The same RSSI block is used within the digital AGC loop. If digital AGC is not required then the RSSI output, after being averaged by the COMB filter, can be provided back to the BB modem via SPI as shown under [[#Automatic_gain_control|automatic gain control]]. In this way the BB can control RF and IF gain stages to implement analogue AGC in which case the AGC loop is closed via the BB modem.<br />
<br />
There is also an RF RSSI block implemented in the RF front end connected to the input of the wideband LNA. This block can be used to detect the presence of large interferers so the BB modem can adjust RX gain stages very quickly to counteract such scenarios. The RF RSSI output is routed to I ADCs of RX channel 1 or RX channel 2. When the RSSI output is to be read, the main RX path of that channel should be disabled. Also, RF RSSI analog output can be provided off-chip at the test pin and further processed by external circuits. In this case none of the RX paths needs to be disabled. The RSSI detects the input from -70 dBm to -20 dBm, corresponding to the full dynamic range of the ADC.<br />
<br />
===Automatic gain control===<br />
[[File:Lms7002m-tsp-agc.png|center|550px|LMS7002M automatic gain control architecture diagram]]<br />
<br />
The AGC loop functions as follows:<br />
<br />
* “Square root of two” (RSSI) block calculates the RMS of the AGC output.<br />
* This signal is averaged by the COMB filter. The averaging window size AVG is programmable via SPI.<br />
* An error signal is then calculated as the difference between the desired output signal level and the measured one. The desired amplitude level ADESIRED is programmable via SPI.<br />
* After the loop gain stage, the error is integrated to construct the digital VGAs gain control signal. Loop gain K is programmable via SPI.<br />
* VGAs gain cannot be negative and should not be zero either, hence max(1,x) module is provided in the feedback path.<br />
<br />
====Possible applications====<br />
[[File:Lms7002m-tsp-agc-truncation.png|center|550px|LMS7002M AGC truncation application example diagram]]<br />
<br />
The first example (a) shows the case where the BB modem expects 4 bits instead of full 12-bit ADC output. In this case, the ADESIRED loop parameter is set as shown in the figure, the gain of RF and IF stages are set for ADC not to produce full scale but ADESIRED level instead. The middle 4 bits are provided to BB. If the RF input signal level goes higher or lower, AGC will adapt the gain to keep its output at ADESIRED value so bits 7 to 4 will always contain 4 MSBs of the received signal. Since we have 4 bits on top and 4 bits below the middle 4 bits, the loop itself provides ±24 dB automatic gain control range without using RF and IF gain stages. The second example shown (b) is a more general case. The BB modem will receive 10 bits while the loop provides ±6 dB gain control range without engaging RF and IF gain blocks.<br />
<br />
==LimeLight™ digital IQ data interface==<br />
The LMS7002M implements a LimeLight™ digital IQ interface to the BB modem. LimeLight™ can be configured to run in one of the following three modes:<br />
<br />
# JESD207 mode<br />
# TRXIQ double data rate (DDR) mode<br />
# TRXIQ single data rate (SDR) mode<br />
<br />
All three modes are capable of supporting both TDD and FDD operation. The data throughput of JESD207 and TRX DDR is high enough to connect to up to 2x2 MIMO BB modems. TRXIQ SDR mode is backward compatible to the LMS6002D digital IQ interface.<br />
<br />
===JESD mode===<br />
[[File:Lms7002m-limelight-jesd-mode.png|center|550px|LMS7002M LimeLight port, JESD mode]]<br />
<br />
This figure shows typical connectivity between the LMS7002M and the BB modem with LimeLight™ running in JESD207 mode. LimeLight™ uses two such ports to support FDD. Signalling is defined by the JESD207 standard itself as specified by JEDEC.<br />
<br />
===TRIXIQ mode===<br />
Connectivity in TRXIQ DDR and SDR modes is the same. The only difference is that in DDR mode the BB and RF chips sample at both edges of FCLK/MCLK.<br />
<br />
====TRXIQ-TX mode====<br />
[[File:Lms7002m-limelight-trxiq-tx-mode.png|center|550px|LMS7002M LimeLight port, TRXIQ-TX mode]]<br />
<br />
In TRXIQ-TX mode the BB modem provides IQSEL, DIO[11:0] and FCLK. The LMS7002M captures data using one or both edges of FCLK.<br />
<br />
====TRXIQ-RX mode====<br />
[[File:Lms7002m-limelight-trxiq-rx-mode.png|center|550px|LMS7002M LimeLight port, TRXIQ-RX mode]]<br />
<br />
In TRXIQ-RX mode, the LMS7002M provides IQSEL, DIO[11:0] and MCLK. The BB modem captures data using one or both edges of MCLK.<br />
<br />
===Timing diagrams===<br />
<br />
====Data path transmit burst start, JESD207 mode====<br />
[[File:Lms7002m-limelight-jesd207-transmit-burst-start.png|center|550px|LMS7002M LimeLight JESD207 mode transmit burst start timing diagram]]<br />
<br />
====Data path transmit burst finish, JESD207 mode====<br />
[[File:Lms7002m-limelight-jesd207-transmit-burst-finish.png|center|550px|LMS7002M LimeLight JESD207 mode transmit burst finish timing diagram]]<br />
<br />
====Data path receive burst start, JESD207 mode====<br />
[[File:Lms7002m-limelight-jesd207-receive-burst-start.png|center|550px|LMS7002M LimeLight JESD207 mode receive burst start timing diagram]]<br />
<br />
====Data path receive burst finish, JESD207 mode====<br />
[[File:Lms7002m-limelight-jesd207-receive-burst-finish.png|center|550px|LMS7002M LimeLight JESD207 mode receive burst finish timing diagram]]<br />
<br />
====Receive data path, TRXIQ double data rate (DDR) mode====<br />
[[File:Lms7002m-limelight-trxiq-ddr-receive-data-path.png|center|550px|LMS7002M LimeLight TRXIQ DDR mode receive data path timing diagram]]<br />
<br />
====Transmit data path, TRXIQ double data rate (DDR) mode====<br />
[[File:Lms7002m-limelight-trxiq-ddr-transmit-data-path.png|center|550px|LMS7002M LimeLight TRXIQ DDR mode transmit data path timing diagram]]<br />
<br />
====Receive data path, TRXIQ single data rate (SDR) mode====<br />
[[File:Lms7002m-limelight-trxiq-sdr-receive-data-path.png|center|550px|LMS7002M LimeLight TRXIQ SDR mode receive data path timing diagram]]<br />
<br />
====Transmit data path, TRXIQ single data rate (SDR) mode====<br />
[[File:Lms7002m-limelight-trxiq-sdr-transmit-data-path.png|center|550px|LMS7002M LimeLight TRXIQ SDR mode transmit data path timing diagram]]<br />
<br />
==Implementing a low-voltage digital IQ interface==<br />
[[File:Lms7002m-digital-iq-interface-supplies.png|center|550px|LMS7002M digital IQ interface supplies diagram]]<br />
<br />
The digital IO buffers of the LMS7002M are supplied using four pins (pin name – DIGPRVDD2, pin ID – W33, T32, H32, AH30). All these pins must be supplied by the same supply DVDD. There is one additional supply pin (pin name – DIGPRPOC, pin ID – W31) which performs Power On Control (POC) function for digital pads. To implement a low voltage digital interface, DVDD can be lowered to 1.8 V. If DVDD = 1.8V then all data lines shown in the above diagram must also be set to 1.8 V CMOS Ios for correct interface operation.<br />
<br />
==IQ interface timing parameters==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit<br />
|-<br />
|Data setup time (t<sub>SETUP</sub>) || 1 || || || ns<br />
|-<br />
|Data hold time (t<sub>HOLD</sub>) || 0.2 || || || ns<br />
|-<br />
|Data output delay (t<sub>OD</sub>) at 15 pF load || || || 6 || ns<br />
|}<br />
<br />
==Digital IQ interface IO buffers specification==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Supply voltage (PVDD) || 1.7 || 2.5 || 3.6 || V || Can go below 2.5 V nominal to support LV CMOS signalling<br />
|-<br />
|Input high V<sub>IH</sub> || PVDD-0.8 || || || V || <br />
|-<br />
|Input low V<sub>IL</sub> || || || 0.8 || V || <br />
|-<br />
|Output high V<sub>OH</sub> || PVDD-0.4 || || || V || <br />
|-<br />
|Output low V<sub>OL</sub> || || || 0.4 || V || <br />
|-<br />
|Input pad capacitance C<sub>IN</sub> || || || 3.5 || pF || <br />
|-<br />
|Output drive current || || || 8 || mA || <br />
|}<br />
<br />
==DACs electical specifications==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Digital core supply || 1.1 || 1.2 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Analogue supply || 1.1 || 1.2 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Number of bits || || 12 || || bits || Two's complement format<br />
|-<br />
|DAC sampling rate || || || 640 || MHz || <br />
|-<br />
|Full scale current || || 625 || || uA || Programmable<br />
|-<br />
|SFDR || || 63<br />62 || || dBc || Fin=10MHz, -1dBFS<br />Fin=37MHz, -2dBFS<br />
|-<br />
|ENOB || || 9 || || bits || <br />
|}<br />
<br />
==ADCs electrical specification==<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit !! Condition/Comment<br />
|-<br />
|Digital core supply || 1.1 || 1.2 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Analogue supply || 1.1 || 1.2 || 1.3 || V || Generated using integrated LDOs<br />
|-<br />
|Number of bits || || 12 || || bits || Two's complement format<br />
|-<br />
|ADC sampling rate || || || 160 || MHz || <br />
|-<br />
|Input amplitude || || 0.8 || || Vpp || Differential<br />
|-<br />
|Input common mode voltage || || 0.55 || || V || <br />
|-<br />
|SFDR || || 63<br />62 || || dBc || Fin=10MHz, -1dBFS<br />Fin=37MHz, -2dBFS<br />
|-<br />
|ENOB || || 9 || || bits || <br />
|}<br />
<br />
==Serial Port Interface==<br />
The functionality of the LMS7002M transceiver is fully controlled by a set of internal registers which can be accessed through a serial port interface. Both write and read SPI operations are supported. The serial port can be configured to run in 3 or 4 wire mode with the following pins used:<br />
<br />
; SEN : serial port enable, active low<br />
; SCLK : serial clock, positive edge sensitive<br />
; SDIO : serial data in/out in 3 wire mode<br />serial data input in 4 wire mode<br />
; SDO : serial data out in 4 wire mode<br />don't care in 3 wire mode<br />
<br />
Serial port key features:<br />
<br />
*32 SPI clock cycles are required to complete a write operation.<br />
* 32 SPI clock cycles are required to complete a read operation.<br />
* Multiple write/read operations are possible without toggling serial port enable signal.<br />
<br />
All configuration registers are 16 bits wide. The write/read sequence consists of a 16-bit instruction followed by 16-bit data to write or read. MSB of the instruction bit stream is used as SPI command where CMD = 1 for write and CMD = 0 for read. Next 4 bits are reserved (Reserved[3:0]) and must be zeroes. Next 5 bits represent module address (Maddress[4:0]) since the LMS7002M configuration registers are divided into logical blocks as shown. The remaining 6 bits of the instruction are used to address particular registers (Reg[5:0]) within the block. Maddress and Reg compiles global 11-bit register address when concatenated ((Maddress << 6) | Reg).<br />
<br />
Note that the write operation is the same for both 3-wire and 4-wire modes. Although not shown, multiple write/read is possible by repeating the instruction/data sequence while keeping SEN low.<br />
<br />
===SPI timing parameters===<br />
{| class="wikitable"<br />
!Parameter !! Min. !! Typ. !! Max. !! Unit<br />
|-<br />
|rowspan="2"|Clock frequency, 4-wire mode<br />3-wire mode || || || 50 || MHz<br />
|-<br />
| || || 20 || MHz<br />
|-<br />
|Enable setup time (t<sub>ES</sub) || 2 || || || ns<br />
|-<br />
|Enable hold time (©) || 0.2 || || || ns<br />
|-<br />
|Data set up time (t<sub>DS</sub>) || 1 || || || ns<br />
|-<br />
|Data hold time (t<sub>DH</sub>) || 0.2 || || || ns<br />
|-<br />
|Data output delay (t<sub>OD</sub>) at 12 pF load || || || 6 || ns<br />
|}<br />
<br />
===SPI write cycle, 3-wire and 4-wire modes===<br />
[[File:Lms7002m-spi-write-cycle-timing.png|center|550px|LMS7002M SPI write cycle timing diagram]]<br />
<br />
===SPI read cycle, 4-wire mode (default)===<br />
[[File:Lms7002m-spi-read-cycle-4-wire-timing.png|center|550px|LMS7002M SPI read cycle, 4-wire (default) timing diagram]]<br />
<br />
===SPI read cycle, 3-wire mode===<br />
[[File:Lms7002m-spi-read-cycle-3-wire-timing.png|center|550px|LMS7002M SPI read cycle, 3-wire timing diagram]]<br />
<br />
===SPI memory map===<br />
The LMS7002M configuration registers are divided into a number of logical blocks.<br />
<br />
Integer and fractional parts of the PLL feedback divider are stored in a number of configuration memory registers. To change their values, multiple SPI write cycles are required. Hence, the controlled PLL will continue to output at the previously selected frequency until all NINT and NFRAC registers are updated. Otherwise it would generate an unpredictable and incorrect LO frequency while being configured. Such parameters are provided through shadow registers. Shadow registers are clocked by the PLL reference clock and output new values simultaneously at first positive clock edge after SEN goes high, i.e. after update of shadowed parameters via SPI is finished.<br />
<br />
{| class="wikitable"<br />
!Module description !! Module address [4:0] !! Register address space [5:0]<br />
|-<br />
|Microcontroller (MCU) || 00000 || 00xxxx<br />
|-<br />
|LimeLight port || 00000 || 1xxxxx<br />
|-<br />
|Top control (AFE, BIAS, XBUF, CGEN, LDO, BIST) || 0001x || xxxxxx<br />
|-<br />
|TRX (TRF(A/B), TBB(A/B), RFE(A/B), RBB(A/B), SX(R/T) || 0010x || xxxxxx<br />
|-<br />
|TxTSP(A/B) || 01000 || 0xxxxx<br />
|-<br />
|TxNCO(A/B) || 01001 || xxxxxx<br />
|-<br />
|TxGFIR1(A/B) || 01010 || xxxxxx<br />
|-<br />
|TxGFIR2(A/B) || 01011 || xxxxxx<br />
|-<br />
|TxGFIR3a(A/B) || 01100 || xxxxxx<br />
|-<br />
|TxGFIR3b(A/B) || 01101 || xxxxxx<br />
|-<br />
|TxGFIR3c(A/B) || 01110 || xxxxxx<br />
|-<br />
|RxTSP(A/B) || 10000 || 0xxxxx<br />
|-<br />
|RxNCO(A/B) || 10001 || xxxxxx<br />
|-<br />
|RxGFIR1(A/B) || 10010 || xxxxxx<br />
|-<br />
|RxGFIR2(A/B) || 10011 || xxxxxx<br />
|-<br />
|RxGFIR3a(A/B) || 10100 || xxxxxx<br />
|-<br />
|RxGFIR3b(A/B) || 10101 || xxxxxx<br />
|-<br />
|RxGFIR3c(A/B) || 10110 || xxxxxx<br />
|}<br />
<br />
===Implementing low-voltage SPI===<br />
[[File:Lms7002m-spi-supplies.png|center|550px|LMS7002M SPI supplies diagram]]<br />
<br />
Digital IO buffers in the SPI region are all supplied from the same pins as the digital IQ interface (pin name – DIGPRVDD2, pin ID – W33, T32, H32, AH30). All these pins must be supplied by the same supply DVDD. There is one additional supply pin (pin name – DIGPRPOC, pin ID – W31) which controls the power on circuitry of the digital pads. To implement a low voltage SPI interface, DVDD can be lowered to 1.8V. If DVDD=1.8V then all data lines in the above figure must also be set to 1.8V CMOS Ios for correct interface operation. The PLL reference clock input level is controlled independently of the DVDD voltage. By default it is 1.8V, but can be further lowered to 1.2V by chip controls if needed.<br />
<br />
==On-chip microcontroller==<br />
[[File:Lms7002m-mcu-connections.png|center|550px|LMS7002M on-chip microcontroller connection diagram]]<br />
<br />
The LMS7002M can be fully controlled by external BB/DSP/FPGA ICs using 4-wire or 3-wire serial port interface. The controlling processor needs to implement a set of calibration, tuning, and control functions to get the best performance out of the transceiver. The on-chip microcontroller unit (MCU) provides the option for independent control using code provided by Lime. This allows the LMS7002M to be independent of the BB/DSP/FPGA and off-loads these devices. Users can still implement full control in their preferred way by developing their own code and/or bypassing on chip microcontroller.<br />
<br />
MCU integration within the LMS7002M chip is shown above. Since the chip communication to the outside world is done through SPI the MCU uses the same protocol, hence the block master SPI (mSPI) is placed in front of it. The MCU communicates to the transceiver circuitry using the same SPI protocol as the BB processor itself. This is implemented via ucSPI lines. There is two way communication between the MCU and BB via mSPI. The baseband can trigger different calibration/tuning/control functions the MCU is programmed to perform. The MCU reports a success, failure or an error code back to the base band processor.<br />
<br />
In this architecture, the base band processor acts as master since it controls the whole chip (the transceiver as well as MCU). The baseband processor also controls the SPI switch (via the SPISW_CTRL control bit/line of mSPI) i.e. taking control over the transceiver part or handing it over to the MCU. The MCU acts as a slave processor. It can control the transceiver only if the baseband allows that via the SPI switch.<br />
<br />
The baseband has full control over the chip including calibration, tuning, and control. It also can trigger the MCU for assistance. In this case, it works in the following way:<br />
<br />
# The base band sets the transceiver for the targets (TX LO frequency, RX LO frequency, TX gain, RX gain, …).<br />
# The base band hands over SPI control to the MCU by setting SPISW_CTRL.<br />
# The base band triggers the function for the MCU to execute.<br />
# The base band periodically checks to see if the MCU has finished and for the status (success, failure, error code).<br />
<br />
===MCU boot-up and EEPROM programming===<br />
Two options are supported, one using external (off chip) EEPROM and another without external EEPROM.<br />
<br />
====Using external EEPROM====<br />
# The baseband processor uploads 8 KB into the on chip program memory.<br />
# After receiving 8 KB, the MCU flushes program memory into EEPROM.<br />
# The base band resets the MCU. <br />
# The MCU reads EEPROM content back into the program memory and starts executing the code.<br />
After the initial EEPROM programming only steps 3 and 4 are required.<br />
<br />
====Without external EEPROM====<br />
# The baseband processor uploads 8 KB into the on chip program memory.<br />
# After receiving 8 KB, the MCU starts executing the code.<br />
<br />
===Specifications===<br />
* 8-bit microcontroller.<br />
* Industry standard 8051 instruction set compatible.<br />
* Running up to 60 MHz.<br />
* Memory<br />
** 8 KB SRAM program memory<br />
** 2 KB SRAM working memory<br />
** 256 B dual port RAM<br />
** All on-chip, integrated.<br />
<br />
==Data converters clock generation==<br />
[[File:Lms7002m-clock-generation.png|center|550px|LMS7002M clock generation diagram]]<br />
<br />
The clock generation circuit for the data converters is shown above. It shares the same reference clock input REFCLK with the RF synthesisers. The clock PLL then generates a continuous frequency range centered around 2.5 GHz. The feed forward divider (FFDIV) is programmable and capable of implementing division values as below:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{N} = 2 \left( \mathit{n} + 1 \right) , \mathit{n} = 0 , 1 , \ldots , 255<br />
\end{align}<br />
</math><br />
<br />
There is a fixed divide by 4 within the ADC block, hence clock division on the DAC side, to provide more flexibility. There is a MUX to connect either Fpll, or Fpll/M to either ADC or DAC clocks. M is programmable and can be set to M = 1, 2, 4 or 8. The other CLKMUX output will be connected to the other data converter clock input. <br />
<br />
TSP blocks receive the same clock as the corresponding data converter, hence there is no need for complex non-power of two or fractional interpolation/decimation. TSP blocks have programmable interpolation/decimation and generate MCLK clocks going back to the base band processor via the LimeLight™ port.<br />
<br />
The circuit implements a continuous clock frequency range from 5 MHz to 320 MHz for the data converters. It is still possible to generate the maximum DAC clock of 640 MHz, however it is not continuous in the range of 320 MHz – 640 MHz.<br />
<br />
==Calibration and initialisation==<br />
There are a number of calibrations which the LMS7002M can carry out internally when instructed via the SPI. These calibrations can be initiated on power up/reset to produce optimum settings. Initialisation and calibration steps are summarised below.<br />
<br />
===Initialisation===<br />
* Power up the chip. In case of using multiple off-chip LDOs, power up sequence is not important.<br />
* Apply RESET pulse (active low). This sets all the configuration registers to their default values.<br />
* Overwrite some registers' defaults if required.<br />
<br />
===Available calibration options===<br />
Listed in recommended order of execution.<br />
* On-chip resistor and capacitor calibration<br />
* TX, RX and clock synthesizer VCO tuning<br />
* TX and RX analog LPF pass band tuning<br />
* RX DC offset and RX LO leakage cancellation<br />
* TX DC offset and TX LO leakage cancellation<br />
* TX IQ imbalance calibration<br />
* RX IQ imbalance calibration<br />
<br />
===Calibration algorithms===<br />
This section shows three key calibration algorithms. Others are either similar or very simple. Please see the LMS7002M Programming and Calibration Guide and other relevant application notes for more details.<br />
<br />
====VCO tuning====<br />
In order to lock the RF or clock synthesiser while having phase noise close to optimum, VCO capacitance has to be selected carefully. A flexible algorithm, based on monitoring on chip Vtune comparators state, is described below.<br />
<br />
[[File:Lms7002m-calibration-vcocap.png|center|550px|LMS7002M calibration, VCOCAP]]<br />
<br />
Assuming the synthesiser is configured for target LO/clock frequency (correct VCO powered up, integer and fractional part of the divider set, …), the above figure shows typical measured Vtune variation with the VCOCAP codes for the two target LO frequencies 1.95 GHz and 2.14 GHz. Vtune is changing from 1.17V down to 0.05 V. However, PLL lock is guaranteed only when Vtune is in the range 0.18 V-0.92 V. Also, for the best phase noise performance, Vtune should be kept around the middle of the range i.e. 0.55 V.<br />
<br />
There are two on chip Vtune comparators per synthesiser: CMPH and CMPL. Their threshold voltages are set to Vth High=0.92 V and Vth Low=0.18 V. The state of the comparators can be obtained by powering them up and reading the corresponding SPI register. The truth table is given below.<br />
<br />
{| class="wikitable"<br />
!CMPH !! CMPL !! Status<br />
|-<br />
|1 || 0 || OK, Vtune in range<br />
|-<br />
|0 || 0 || Vtune is high (>0.92 V), PLL lock not guaranteed<br />
|-<br />
|1 || 1 || Vtune is low (<0.18 V), PLL lock not guaranteed<br />
|-<br />
|0 || 1 || Not possible<br />
|}<br />
<br />
These can be used to choose VCOCAP code. All we need to find is the code CMIN when comparators change the state from “00” to “10” and the code CMAX when the comparators change the state from “10” to “11”. Optimum VCOCAP code is then the middle one between CMIN and CMAX. For LO=2.4 GHz, this is illustrated in the earlier graph. In this case, optimum code is around 108.<br />
<br />
Once the synthesiser is set, Vtune comparators can also be used as lock (in range) indicators.<br />
<br />
====Analogue filters pass band tuning====<br />
The LMS7002M has six analogue low-pass filtering stages. The pass band of each stage can independently be programmed and/or tuned. Tuning is very useful as it takes into account process, temperature, sample-to-sample and voltage supply variations. The algorithm uses on chip options as follows:<br />
* TXNCO generates digital test tones (CW).<br />
* Digital test tones are converted into analog by the DACs.<br />
* INVERSE sinc filter must be enabled to flatten DACs amplitude response.<br />
* LMS7002M is set into either base-band or RF TX-to-RX loop back mode.<br />
* Only LPF being tuned should be enabled. Other TX and RX filters should be bypassed or widely open.<br />
* Loop back signal is converted back into digital domain by the ADCs.<br />
* Digital RX RSSI block measures the amplitude of the loop back signal.<br />
<br />
All filtering stages are implemented as active RC blocks hence their pass band is controllable by changing resistors and/or capacitors. Only two parameters per stage are available to change via SPI: one for filter resistors control and another one for capacitors control. If the resistors control parameter is changed then all resistors within the filter are scaled equally; if the capacitors control code is changed then all capacitors within the filter are scaled equally. Therefore, component ratio is kept constant which preserves designed filter amplitude response (Chebyshev for example) disregarding the control codes.<br />
<br />
There are two types of filter stages: trans-impedance (TXLPFLAD, TXLPFH, RXTIA) and voltage gain (TXLPFS5, RXLPFL, RXLPFH). Tuning is essentially the same for all stages with minor differences between trans-impedance and voltage gain types. The algorithm is two steps process described below and illustrated in the following figure.<br />
<br />
[[File:Lms7002m-calibration-pass-band.png|center|550px|LMS7002M calibration, pass-band tuning]]<br />
<br />
=====Step 1: Checkpoint=====<br />
TXNCO generates very low frequency (close to DC) test tone (200 kHz in the previous figure) which is by design guaranteed to be within filter pass band for all possible RC values.<br />
<br />
Tune the gain of the measurement loop (use DACs current amplifiers and RXPGA) to get RSSI reading few dB backed off from its maximum. This maximises the measurement dynamic range while still having some margin to measure filter gain which may be higher than the gain at low frequencies due to in band amplitude ripple.<br />
<br />
=====Step 2: RC search=====<br />
# TXNCO generates a test tone which is the target 3 dB cut-off frequency (4 MHz in the previous figure).<br />
# Alter C components of the filter to get RSSI reading 3 dB below the reading obtained at the end of step 1.<br />
## If step 2 fails to reach the target, change R components of the filter. If filter stage is trans-impedance go to step 1, otherwise go to step 2. Note that changing R in the trans-impedance stage changes its gain, hence the need to repeat step 1.<br />
<br />
====DC offset and IQ imbalance calibration====<br />
In order to show the basis of this kind of calibrations, let us first analyse a scenario with the LMS7002M configured as below.<br />
<br />
* Drive TXTSP with digital 12-bit two’s complement DC i.e. <br />
** TXI = 011111111111 = +max 12-bit word<br />
** TXQ = 10000000000 = -max 12-bit word<br />
*: This can be done through the on-chip test option, no need to engage LimeLight™ with assistance from BB.<br />
* Bypass IQ Gain Correction, IQ Phase Correction and TX DC Correction TXTSP blocks. Keep INVERSE sinc filter running.<br />
* Configure TXLPF pass band to be able to filter DAC images.<br />
* Tune TX Synthesiser to <math>\mathit{f_{TXLO}}</math>. Tune RX Synthesiser to <math>\mathit{f_{RXLO}}</math> offset from <math>\mathit{f_{TXLO}}</math> by a few MHz and keep <math>\mathit{f_{TXLO}} > \mathit{f_{RXLO}}</math>.<br />
* Close RF Loopback switch.<br />
* Set TXPAD, RXTIA and RXPGA gain not to overload ADCs.<br />
* Open RXLPF pass band as much as possible to clearly see all tones generated in this setup.<br />
* Bypass IQ Gain Correction, IQ Phase Correction and RX DC Correction RXTSP blocks. Bypass Decimation filter to see all tones generated by the whole setup.<br />
* Set RXNCO frequency to 0. Set TXNCO to <math>\mathit{f_{TXNCO}}</math> where <math>\mathit{f_{TXLO}} - \mathit{f_{RXLO}} > \mathit{f_{TXNCO}}</math><br />
<br />
The test setup described above uses minimum filtering to clearly show unwanted tones we need to cancel. The following spectrum diagram shows RX output while LMS7002M works in RF loopback mode. Tones and the reasons for their existence are as below.<br />
<br />
[[File:Lms7002m-calibration-iq-imbalance-spectral-tones.png|center|550px|LMS7002M calibration, IQ imbalance spectral tones example]]<br />
<br />
: (1) TX DC and TX LO leakage. It is down converted by fRXLO hence it appears in BB frequencies at fTXLO-fRXLO<br />
: (2) This is wanted TX sideband. Offset from TX LO leakage by TXNCO frequency .fTXNCO.<br />
: (3) Unwanted TX sideband caused by TX IQ imbalance.<br />
: (4) RX DC offset and RX LO leakage. Appears at DC.<br />
: (3a) RX unwanted side band caused by component (3)<br />
: (1a) RX unwanted side band caused by component (1)<br />
: (2a) RX unwanted side band caused by component (2)<br />
<br />
Note that all tones at negative frequencies are the consequence of RX IQ imbalance.<br />
<br />
The previous figure shows that with single measurement we can capture all tones we need to cancel. There are two problems with this approach. First, we need to perform complex FFT which is computationally intensive, i.e. it takes a long time. The on-chip MCU is not computationally powerful enough, so FFT has to be done by the BB processor which we want to avoid. The alternative would be to use digital RSSI for measurement instead of FFT. RSSI can accurately measure only single tone, not the multiple tones present in the previous figure. Fortunately, choosing the order of calibration steps carefully and with the help of on-chip available options (digital and/or analogue filters, TX and RX NCOs) this is possible.<br />
<br />
TX IQ imbalance calibration steps are shown here as an illustration. Other calibration steps are similar. Let us assume that RX DC/LO leakage as well as TX DC/LO leakage calibration steps have already been performed, i.e. tones (1), (1a), and (4) are minimised. In this case we will have four remaining tones as shown in the below figure.<br />
<br />
[[File:Lms7002m-calibration-digital-filtering-step-a.png|center|550px|LMS7002M calibration, digital filtering step (a)]]<br />
<br />
The goal of this calibration is to minimize tone (3) keeping wanted tone (2) untouched. Tone (2) will introduce a huge error if present in RSSI measurement, so some filtering will be required. Decimation filter is used for this purpose rather than general purpose FIR filters due to the fact that decimation filter is much simpler and faster to configure. The resulting spectrum after digital filtering is shown in the figure below.<br />
<br />
[[File:Lms7002m-calibration-digital-filtering-step-b.png|center|550px|LMS7002M calibration, digital filtering step (b)]]<br />
<br />
The same spectrum of the above figure drives the digital RSSI block. In fact, RSSI measures the level of the two-tone signal (3) and (3a), where (3a) is due to RX IQ imbalance. However, tones are correlated; in other words when minimising (3), tone (3a) will go down by the same amount. The RSSI output will be a composite power level of those two tones and is a valid measurement. If we minimise RSSI output we are minimising TX IQ imbalance disregarding the presence of two (correlated) tones.<br />
<br />
The algorithm, then, is simple. First alter the on-chip analogue IQ phase correction parameters, if available, to minimise RSSI output. After that alter the TX gain correction and TX phase correction parameters of the TXTSP digital block to further minimise RSSI output. The resulting spectrum is shown in the following figure.<br />
<br />
[[File:Lms7002m-calibration-digital-filtering-step-c.png|center|550px|LMS7002M calibration, digital filtering step (c)]]<br />
<br />
====TDD/FDD mode enhancement option====<br />
In both TDD and FDD mode the LMS7002M is capable of running from a single PLL, allowing one on-chip PLL to be powered down. In TDD mode, a single PLL output drives both TX and RX mixers; in FDD mode, a single PLL drives both mixers as well while UL/DL frequency separation is implemented in the digital domain using the NCO and complex mixer parts of the TSP block. The maximum frequency shift range which can be achieved in the digital domain is as below:<br />
<br />
<math><br />
\begin{align}<br />
\mathit{f_{TXLO}} = \mathit{f_{PLL}} \pm 0.6 * \mathit{f_{DAC}} / 2 \\<br />
\mathit{f_{RXLO}} = \mathit{f_{PLL}} \pm 0.6 * \mathit{f_{ADC}} / 2<br />
\end{align}<br />
</math><br />
<br />
where <math>\mathit{f_{TXLO}}</math> and <math>\mathit{f_{RXLO}}</math> are effective TX and RX LO frequencies, <math>\mathit{f_{PLL}}</math> is the shared PLL output frequency while <math>\mathit{f_{DAC}}</math> and <math>\mathit{f_{ADC}}</math> are data converter sampling rates. Note that the Nyquist frequency of the NCOs is scaled by a factor of 0.6 to make space for TXLPF and RXLPF to operate.<br />
<br />
Running the LMS7002M in single PLL mode has the following advantages:<br />
<br />
* Current consumption is significantly reduced since one PLL is powered down.<br />
* Fast TX<->RX switching time in TDD mode is achievable since the PLL does not need to relock.<br />
* There is no TXVCO<->RXVCO polling issue since a single PLL is used.<br />
* Using the digital domain for LO frequency shifts enables implementation of very fast frequency hopping systems.<br />
<br />
====Improving fractional-N close-to-integer RF synthesiser spurs performance====<br />
Due to the PFD/CHP ‘dead zone,’ i.e. nonlinearity around zero, fractional-N synthesisers are prone to generate unwanted spurs when set close to integer frequency. These spurs are unfortunately in the loop-pass band and cannot be filtered. One of the solutions is to set constant charge pump current offset to shift PFD/CHP away from zero, i.e. operating them in a more linear region. However, this CHP offset value depends on how far PLL output frequency is away from the nearest integer frequency and has to be tuned accordingly.<br />
<br />
Digital blocks can help this case. Set the charge pump offset current to some middle value and keep it constant disregarding how far close-to-integer frequency is away from integer frequency. Offset the PLL wanted frequency away enough from integer frequency in order not to have close-to-integer spurs issue. This introduces a PLL output frequency error which can be corrected by a corresponding NCO available in the digital TSB block.<br />
<br />
==Package outline and pin description==<br />
[[File:Lms7002m-261l-aqfn-package-top.png|center|550px|LMS7002M in 261L aQFN package, top view]]<br />
<br />
{| class="wikitable"<br />
!Pin No. !! Pin ID !! Pin Name !! Type !! Description !! Notes<br />
|-<br />
| 1 || C1 || UNUSED || - || - || <br />
|-<br />
| 2 || D2 || UNUSED || - || - || <br />
|-<br />
| 3 || E3 || UNUSED || - || - || <br />
|-<br />
| 4 || F4 || UNUSED || - || - || <br />
|-<br />
| 5 || G5 || VDD12_TXBUF || analogue supply || 1.25V supply – TX XOSC buffer || <br />
|-<br />
| 6 || H6 || VDD18_TXBUF || analogue supply || 1.8V supply – TX XOSC buffer || <br />
|-<br />
| 7 || F2 || UNUSED || - || - || <br />
|-<br />
| 8 || G3 || VDD18_VCO_SXT || analogue supply || 1.8V supply – TX SX VCO || <br />
|-<br />
| 9 || J5 || VDD12O_VCO_SXT || analogue supply || 1.25V supply – TX SX VCO || <br />
|-<br />
| 10 || K6 || VDD12_VCO_SXT || analogue supply || 1.25V supply – TX SX VCO || <br />
|-<br />
| 11 || G1 || UNUSED || - || - || <br />
|-<br />
| 12 || H2 || GND_VCO_SXT || analogue gnd || GND – TX SX VCO || <br />
|-<br />
| 13 || J3 || VDD_CP_SXT || analogue supply || 1.25V supply – TX SX Charge pump || <br />
|-<br />
| 14 || K4 || GND_CP_SXT || analogue gnd || GND – TX SX Charge pump || <br />
|-<br />
| 15 || L5 || VDD_DIV_SXT || analogue supply || 1.25V supply – TX SX frequency divider || <br />
|-<br />
| 16 || J1 || UNUSED || - || - || <br />
|-<br />
| 17 || K2 || VDDO_DIV_SXT || analogue supply || 1.25V supply – TX SX frequency divider || <br />
|-<br />
| 18 || M6 || UNUSED || - || - || <br />
|-<br />
| 19 || L3 || GND_DIV_SXT || analogue gnd || GND – TX SX frequency divider || <br />
|-<br />
| 20 || M4 || DVDD_SXT || digital supply || 1.25V supply – digital supply for TX SX || <br />
|-<br />
| 21 || M2 || UNUSED || - || - || <br />
|-<br />
| 22 || N3 || DGND_SXT || digital gnd || GND – digital supply for TX SX || <br />
|-<br />
| 23 || N1 || VDD18_LDO_TX || analogue supply || 1.8V supply – TX LDO || <br />
|-<br />
| 24 || P4 || VDD_TBB || analogue supply || 1.25V supply – TX baseband || <br />
|-<br />
| 25 || P2 || tbbqn_pad_1 || in || TX change input pad to externally drive the TX BB Channel 1 || <br />
|-<br />
| 26 || R5 || tbbin_pad_1 || in || TX change input pad to externally drive the TX BB Channel 1 || <br />
|-<br />
| 27 || R3 || tbbqp_pad_1 || in || TX change input pad to externally drive the TX BB Channel 1 || <br />
|-<br />
| 28 || T6 || tbbin_pad_2 || in || TX change input pad to externally drive the TX BB Channel 2 || <br />
|-<br />
| 29 || T4 || tbbip_pad_1 || in || TX change input pad to externally drive the TX BB Channel 1 || <br />
|-<br />
| 30 || U5 || adcin_in_1 || in || ADC input pads – To use external filtering Channel 1 || <br />
|-<br />
| 31 || U3 || tbbqp_pad_2 || in || TX change input pad to externally drive the TX BB Channel 2 || <br />
|-<br />
| 32 || U1 || tbbqn_pad_2 || in || TX change input pad to externally drive the TX BB Channel 2 || <br />
|-<br />
| 33 || V2 || tbbip_pad_2 || in || TX change input pad to externally drive the TX BB Channel 2 || <br />
|-<br />
| 34 || V4 || adcin_ip_1 || in || ADC input pads – To use external filtering Channel 1 || <br />
|-<br />
| 35 || V6 || adcin_in_2 || in || ADC input pads – To use external filtering Channel 2 || <br />
|-<br />
| 36 || W3 || adcin_qn_1 || in || ADC nput pads – To use external filtering Channel 1 || <br />
|-<br />
| 37 || Y2 || adcin_qp_1 || in || ADC input pads – To use external filtering Channel 1 || <br />
|-<br />
| 38 || Y4 || adcin_qn_2 || in || ADC input pads – To use external filtering Channel 2 || <br />
|-<br />
| 39 || AA1 || adcin_ip_2 || in || ADC input pads – To use external filtering Channel 2 || <br />
|-<br />
| 40 || Y6 || rbbip_pad_1 || out || RX BB output – To use external filtering Channel 1 || <br />
|-<br />
| 41 || AA3 || adcin_qp_2 || in || ADC input pads – To use external filtering Channel 2 || <br />
|-<br />
| 42 || AA5 || rbbqn_pad_1 || out || RX BB output – To use external filtering Channel 1 || <br />
|-<br />
| 43 || AB2 || rbbin_pad_1 || out || RX BB output – To use external filtering Channel 1 || <br />
|-<br />
| 44 || AB4 || rbbqp_pad_1 || out || RX BB output – To use external filtering Channel 1 || <br />
|-<br />
| 45 || AC3 || rbbin_pad_2 || out || RX BB output – To use external filtering Channel 2 || <br />
|-<br />
| 46 || AB6 || rbbqn_pad_2 || out || RX BB output – To use external filtering Channel 2 || <br />
|-<br />
| 47 || AD2 || rbbip_pad_2 || out || RX BB output – To use external filtering Channel 2 || <br />
|-<br />
| 48 || AC5 || rbbqp_pad_2 || out || RX BB output – To use external filtering Channel 2 || <br />
|-<br />
| 49 || AE1 || UNUSED || - || - || <br />
|-<br />
| 50 || AD4 || VDD14_RBB || analogue supply || 1.4V supply- RX baseband || <br />
|-<br />
| 51 || AE3 || VDD18_TIA_RFE || analogue supply || 1.8V supply- RXFE TIA || <br />
|-<br />
| 52 || AF2 || VDD14_TIA_RFE || analogue supply || 1.4V supply- RXFE TIA || <br />
|-<br />
| 53 || AD6 || VDD12_TIA_RFE || analogue supply || 1.25V supply- RXFE TIA || <br />
|-<br />
| 54 || AE5 || UNUSED || - || - || <br />
|-<br />
| 55 || AF4 || VDD18_LDO_RX || analogue supply || 1.8V supply- RX LDO || <br />
|-<br />
| 56 || AG2 || UNUSED || - || - || <br />
|-<br />
| 57 || AH2 || UNUSED || - || - || <br />
|-<br />
| 58 || AJ1 || UNUSED || - || - || <br />
|-<br />
| 59 || AF6 || VDD14_LNA_RFE || analogue supply || 1.4V supply- RXFE LNA || <br />
|-<br />
| 60 || AG5 || VDD12_LNA_RFE || analogue supply || 1.25V supply- RXFE LNA || <br />
|-<br />
| 61 || AH4 || UNUSED || - || - || <br />
|-<br />
| 62 || AJ3 || UNUSED || - || - || <br />
|-<br />
| 63 || AK2 || UNUSED || - || - || <br />
|-<br />
| 64 || AJ5 || UNUSED || - || - || <br />
|-<br />
| 65 || AK4 || UNUSED || - || - || <br />
|-<br />
| 66 || AL3 || UNUSED || - || - || <br />
|-<br />
| 67 || AM2 || UNUSED || - || - || <br />
|-<br />
| 68 || AN3 || rfgp_w_RFE_2 || in || LNA input gate Wideband LNA – Gate : Channel 2 || <br />
|-<br />
| 69 || AM4 || rfgn_w_RFE_2 || in || LNA input gate Wideband LNA – Gate : Channel 2 || <br />
|-<br />
| 70 || AL5 || UNUSED || - || - || <br />
|-<br />
| 71 || AK6 || UNUSED || - || - || <br />
|-<br />
| 72 || AJ7 || rfsn_l_RFE_2 || in/out || LNA Lowband LNA – Source: Channel 2 || <br />
|-<br />
| 73 || AN5 || rfgp_l_RFE_2 || in || LNA input gate Lowband LNA – Gate : Channel 2 || <br />
|-<br />
| 74 || AM6 || UNUSED || - || - || <br />
|-<br />
| 75 || AL7 || UNUSED || - || - || <br />
|-<br />
| 76 || AK8 || UNUSED || - || - || <br />
|-<br />
| 77 || AJ9 || rfsp_l_RFE_2 || in/out || LNA Lowband LNA – Source : Channel 2 || <br />
|-<br />
| 78 || AP6 || rfgn_l_RFE_2 || in || LNA input gate Lowband LNA – Gate : Channel 2 || <br />
|-<br />
| 79 || AN7 || rfgp_h_RFE_2 || in || LNA input gate Highband LNA – Gate : Channel 2 || <br />
|-<br />
| 80 || AM8 || rfgn_h_RFE_2 || in || LNA input gate Highband LNA – Gate : Channel 2 || <br />
|-<br />
| 81 || AL9 || UNUSED || - || - || <br />
|-<br />
| 82 || AK10 || UNUSED || - || - || <br />
|-<br />
| 83 || AJ11 || UNUSED || - || - || <br />
|-<br />
| 84 || AN9 || rfgp_w_RFE_1 || in || LNA input gate Wideband LNA – Gate : Channel 1 || <br />
|-<br />
| 85 || AM10 || UNUSED || - || - || <br />
|-<br />
| 86 || AL11 || UNUSED || - || - || <br />
|-<br />
| 87 || AP10 || rfgn_w_RFE_1 || in || LNA input gate Wideband LNA – Gate : Channel 1 || <br />
|-<br />
| 88 || AK12 || rfsn_l_RFE_1 || in/out || LNA Lowband LNA – Source : Channel 1 || <br />
|-<br />
| 89 || AN11 || rfgp_l_RFE_1 || in || LNA input gate Lowband LNA – Gate : Channel 1 || <br />
|-<br />
| 90 || AJ13 || UNUSED || - || - || <br />
|-<br />
| 91 || AM12 || rfgn_l_RFE_1 || in || LNA input gate Lowband LNA – Gate : Channel 1 || <br />
|-<br />
| 92 || AL13 || rfsp_l_RFE_1 || in/out || LNA Lowband LNA – Source : Channel 1 || <br />
|-<br />
| 93 || AK14 || rfgp_h_RFE_1 || in || LNA input gate Highband LNA – Gate : Channel 1 || <br />
|-<br />
| 94 || AJ15 || rfgn_h_RFE_1 || in || LNA input gate Highband LNA – Gate : Channel 1 || <br />
|-<br />
| 95 || AN17 || VDD_MXLOBUF_RFE || analogue supply || 1.25V supply: RX LO buffers || <br />
|-<br />
| 96 || AM18 || VDD18_SXR || analogue supply || 1.8V supply: RX SX || <br />
|-<br />
| 97 || AL19 || VDD_CP_SXR || analogue supply || 1.25V supply: RX SX Charge pump || <br />
|-<br />
| 98 || AJ19 || GND_CP_SXR || analogue gnd || GND: RX SX Charge pump || <br />
|-<br />
| 99 || AM20 || VDD_DIV_SXR || analogue supply || 1.25V supply: RX SX frequency divider || <br />
|-<br />
| 100 || AK20 || GND_DIV_SXR || analogue gnd || GND: RX SX frequency divider || <br />
|-<br />
| 101 || AL21 || DVDD_SXR || digital supply || 1.25V digital supply: RX SX f || <br />
|-<br />
| 102 || AJ21 || UNUSED || - || - || <br />
|-<br />
| 103 || AM22 || DGND_SXR || digital gnd || GND: RX SX || <br />
|-<br />
| 104 || AN23 || VDD12_VCO_SXR || analogue supply || 1.25V supply: RX SX || <br />
|-<br />
| 105 || AK22 || VDD18_VCO_SXR || analogue supply || 1.8V supply: RX SX || <br />
|-<br />
| 106 || AL23 || GND_VCO_SXR || analogue gnd || GND: RX SX VCO || <br />
|-<br />
| 107 || AM24 || xoscin_rx || in || || <br />
|-<br />
| 108 || AN25 || GND_RXBUF || analogue gnd || GND – RX XOSC buffer || <br />
|-<br />
| 109 || AP26 || VDD12_RXBUF || analogue supply || 1.25V supply – RX XOSC buffer || <br />
|-<br />
| 110 || AM26 || VDD18_RXBUF || analogue supply || 1.8V supply – RX XOSC buffer || <br />
|-<br />
| 111 || AN27 || UNUSED || - || - || <br />
|-<br />
| 112 || AJ25 || VDD_AFE || analogue supply || 1.25V supply – ADC/DAC || <br />
|-<br />
| 113 || AK26 || UNUSED || - || - || <br />
|-<br />
| 114 || AL27 || UNUSED || - || - || <br />
|-<br />
| 115 || AM28 || UNUSED || - || - || <br />
|-<br />
| 116 || AN29 || UNUSED || - || - || <br />
|-<br />
| 117 || AP30 || UNUSED || - || - || <br />
|-<br />
| 118 || AJ27 || UNUSED || - || - || <br />
|-<br />
| 119 || AK28 || UNUSED || - || - || <br />
|-<br />
| 120 || AL29 || UNUSED || - || - || <br />
|-<br />
| 121 || AM30 || UNUSED || - || - || <br />
|-<br />
| 122 || AN31 || UNUSED || - || - || <br />
|-<br />
| 123 || AP32 || UNUSED || - || - || <br />
|-<br />
| 124 || AJ29 || UNUSED || - || - || <br />
|-<br />
| 125 || AL31 || UNUSED || - || - || <br />
|-<br />
| 126 || AK30 || UNUSED || - || - || <br />
|-<br />
| 127 || AM34 || UNUSED || - || - || <br />
|-<br />
| 128 || AL33 || UNUSED || - || - || <br />
|-<br />
| 129 || AK32 || UNUSED || - || - || <br />
|-<br />
| 130 || AJ31 || UNUSED || - || - || <br />
|-<br />
| 131 || AH30 || DIGPRVDD2 || DVDD || Digital Pad Ring power supply for post-driver || <br />
|-<br />
| 132 || AG29 || DIGPRGND1 || pad gnd || Digital Pad Ring ground for pre-driver || <br />
|-<br />
| 133 || AK34 || UNUSED || - || - || <br />
|-<br />
| 134 || AJ33 || UNUSED || - || - || <br />
|-<br />
| 135 || AH32 || UNUSED || - || - || <br />
|-<br />
| 136 || AG31 || DIQ1_D0 || IO_cmos1225 || DIQ bus, bit 0. LML Port 1 || <br />
|-<br />
| 137 || AF30 || DIQ1_D1 || IO_cmos1225 || DIQ bus, bit 1. LML Port 1 || <br />
|-<br />
| 138 || AE29 || DIGPRVDD1 || DVDD || Digital Pad Ring power supply for pre-driver || <br />
|-<br />
| 139 || AG33 || UNUSED || - || - || <br />
|-<br />
| 140 || AF32 || DIGPRGND2 || pad gnd || Digital Pad Ring ground for post-driver || <br />
|-<br />
| 141 || AE31 || DIQ1_D3 || IO_cmos1225 || DIQ bus, bit 3. LML Port 1 || <br />
|-<br />
| 142 || AD30 || DIQ1_D4 || IO_cmos1225 || DIQ bus, bit 4. LML Port 1 || <br />
|-<br />
| 143 || AF34 || DIQ1_D2 || IO_cmos1225 || DIQ bus, bit 2. LML Port 1 || <br />
|-<br />
| 144 || AE33 || DIQ1_D6 || IO_cmos1225 || DIQ bus, bit 6. LML Port 1 || <br />
|-<br />
| 145 || AC29 || DIQ1_D5 || IO_cmos1225 || DIQ bus, bit 5. LML Port 1 || <br />
|-<br />
| 146 || AD32 || DIQ1_D7 || IO_cmos1225 || DIQ bus, bit 7. LML Port 1 || <br />
|-<br />
| 147 || AC31 || DIQ1_D8 || IO_cmos1225 || DIQ bus, bit 8. LML Port 1 || <br />
|-<br />
| 148 || AB30 || DIQ1_D10 || IO_cmos1225 || DIQ bus, bit 10. LML Port 1 || <br />
|-<br />
| 149 || AC33 || DIQ1_D9 || IO_cmos1225 || DIQ bus, bit 9. LML Port 1 || <br />
|-<br />
| 150 || AB32 || DIQ1_D11 || IO_cmos1225 || DIQ bus, bit 11. LML Port 1 || <br />
|-<br />
| 151 || AA29 || DIGPRVDD1 || DVDD || Digital Pad Ring power supply for pre-driver || <br />
|-<br />
| 152 || AB34 || MCLK1 || out_cmos1225 || Clock from RFIC to BBIC in JESD207 mode. LML Port 1 || <br />
|-<br />
| 153 || AA31 || DIGPRGND1 || DGND || Digital Pad Ring ground for pre-driver || <br />
|-<br />
| 154 || AA33 || FCLK1 || in_cmos1225 || Clock from BBIC to RFIC in JESD207 mode. LML Port 1 || <br />
|-<br />
| 155 || Y30 || DIGPRGND2 || pad gnd || Digital Pad Ring ground for post-driver || <br />
|-<br />
| 156 || Y32 || ENABLE_IQSEL1 || IO_cmos1225 || IQ flag in RXTXIQ mode; enable flag in JESD207 mode. LML Port 1 || <br />
|-<br />
| 157 || W29 || DIGPRGND1 || pad gnd || Digital Pad Ring ground for pre-driver || <br />
|-<br />
| 158 || W31 || DIGPRPOC || POC || POC circuit || <br />
|-<br />
| 159 || W33 || DIGPRVDD2 || DVDD || Digital Pad Ring power supply for post-driver || <br />
|-<br />
| 160 || V30 || LOGIC_RESET || analogue supply/gnd || Not used || <br />
|-<br />
| 161 || V32 || TXNRX1 || in_cmos1225 || IQ data protocol control in JESD207 mode. LML Port 1 || <br />
|-<br />
| 162 || V34 || RXEN || in_cmos1225 || RX hard power off || <br />
|-<br />
| 163 || U33 || CORE_LDO_EN || analogue supply/gnd || External enable control signal for the internal LDOs. || Should be fixed to analogue supply if internal LDOs are used.<br />Should be fixed to analogue gnd if internal LDOs are NOT used.<br />
|-<br />
| 164 || U31 || TXNRX2 || in_cmos1225 || IQ data protocol control in JESD207 mode. LML Port 2 || <br />
|-<br />
| 165 || U29 || TXEN || in_cmos1225 || TX hard power off || <br />
|-<br />
| 166 || T32 || DIGPRVDD2, DIGPRPOC || DVDD || Digital Pad Ring power supply for post-driver and POC || <br />
|-<br />
| 167 || T30 || DIGPRGND1, DIGPRGND2 || pad gnd || Digital Pad Ring ground for pre-driver and post-driver || <br />
|-<br />
| 168 || R33 || ENABLE_ IQSEL2 || IO_cmos1225 || IQ flag in RXTXIQ mode; enable flag in JESD207 mode. LML Port 2 || <br />
|-<br />
| 169 || R31 || DIGPRVDD1 || DVDD || Digital Pad Ring power supply for pre-driver || <br />
|-<br />
| 170 || P34 || MCLK2 || out_cmos1225 || Clock from RFIC to BBIC in JESD207 mode. LML Port 2 || <br />
|-<br />
| 171 || R29 || FCLK2 || in_cmos1225 || Clock from BBIC to RFIC in JESD207 mode. LML Port 2 || <br />
|-<br />
| 172 || P32 || DIQ2_D11 || IO_cmos1225 || DIQ bus, bit 11. LML Port 2 || <br />
|-<br />
| 173 || P30 || DIQ2_D10 || IO_cmos1225 || DIQ bus, bit 10. LML Port 2 || <br />
|-<br />
| 174 || N33 || DIQ2_D9 || IO_cmos1225 || DIQ bus, bit 9. LML Port 2 || <br />
|-<br />
| 175 || N31 || DIQ2_D8 || IO_cmos1225 || DIQ bus, bit 8. LML Port 2 || <br />
|-<br />
| 176 || M32 || DIQ2_D7 || IO_cmos1225 || DIQ bus, bit 7. LML Port 2 || <br />
|-<br />
| 177 || L33 || DIGPRVDD1 || DVDD || Digital Pad Ring power supply for pre-driver || <br />
|-<br />
| 178 || M30 || DIQ2_D6 || IO_cmos1225 || DIQ bus, bit 6. LML Port 2 || <br />
|-<br />
| 179 || K34 || DIQ2_D5 || IO_cmos1225 || DIQ bus, bit 5. LML Port 2 || <br />
|-<br />
| 180 || L31 || DIQ2_D4 || IO_cmos1225 || DIQ bus, bit 4. LML Port 2 || <br />
|-<br />
| 181 || K32 || DIQ2_D3 || IO_cmos1225 || DIQ bus, bit 3. LML Port 2 || <br />
|-<br />
| 182 || J33 || DIGPRGND1 || DGND || Digital Pad Ring ground for pre-driver || <br />
|-<br />
| 183 || K30 || DIQ2_D2 || IO_cmos1225 || DIQ bus, bit 2. LML Port 2 || <br />
|-<br />
| 184 || J31 || DIQ2_D1 || IO_cmos1225 || DIQ bus, bit 1. LML Port 2 || <br />
|-<br />
| 185 || H32 || DIGPRVDD2 || DVDD || Digital Pad Ring supply for post-driver || <br />
|-<br />
| 186 || H30 || DIQ2_D0 || IO_cmos1225 || DIQ bus, bit 0. LML Port 2 || <br />
|-<br />
| 187 || G31 || DIGPRGND2 || pad gnd || Digital Pad Ring ground for post-driver || <br />
|-<br />
| 188 || F32 || UNUSED || - || - || <br />
|-<br />
| 189 || G29 || UNUSED || - || - || <br />
|-<br />
| 190 || F30 || SDIO || IO_cmos1225 || Serial port data input-output in 3 wire mode, Serial port data input in 4 wire mode, CMOS || <br />
|-<br />
| 191 || E31 || UNUSED || - || - || <br />
|-<br />
| 192 || D32 || UNUSED || - || - || <br />
|-<br />
| 193 || C31 || UNUSED || - || - || <br />
|-<br />
| 194 || D30 || UNUSED || - || - || <br />
|-<br />
| 195 || E29 || UNUSED || - || - || <br />
|-<br />
| 196 || F28 || SDO || out_cmos1225 || Serial port data output, CMOS || <br />
|-<br />
| 197 || C29 || SCLK || in_cmos1225 || Serial port clock, positive edge sensitive, CMOS || <br />
|-<br />
| 198 || D28 || SEN || in_cmos1225 || Serial port enable, active low, CMOS || <br />
|-<br />
| 199 || E27 || RESET || in_cmos1225 || Hardware reset, active low, CMOS level || <br />
|-<br />
| 200 || F26 || UNUSED || - || - || <br />
|-<br />
| 201 || C27 || SCL || IO_cmos1225 || uControler || <br />
|-<br />
| 202 || D26 || SDA || IO_cmos1225 || uControler || <br />
|-<br />
| 203 || E25 || GND_SPI_BUF || digital gnd || GND – SPI buffer || <br />
|-<br />
| 204 || F24 || VDD_SPI_BUF || digital supply || 1.25V supply – SPI buffer || <br />
|-<br />
| 205 || C25 || VDD12_DIG || digital supply || output 1.2V supply for digital LDO || <br />
|-<br />
| 206 || D24 || VDD18_DIG || digital supply || 1.8V supply for digital LDO || <br />
|-<br />
| 207 || E23 || UNUSED || - || - || <br />
|-<br />
| 208 || F22 || tstdo<1> || out_cmos1225 || digital output test pin || <br />
|-<br />
| 209 || C23 || GND_DIG || digital gnd || GND for the digital LDO || <br />
|-<br />
| 210 || D22 || tstdo<0> || out_cmos1225 || digital output test pin || <br />
|-<br />
| 211 || B22 || tstao || out_cmos1225 || analogue test pin || <br />
|-<br />
| 212 || E21 || VDD18_VCO_CGEN || analogue supply || &nbsp;1.8V supply – VCO CLKGEN || <br />
|-<br />
| 213 || C21 || VDD14_VCO_CGEN || analogue supply || 1.4V supply – VCO CLKGEN || <br />
|-<br />
| 214 || F20 || VDD_CP_CGEN || analogue supply || 1.25V supply – Charge Pump – CLKGEN || <br />
|-<br />
| 215 || A21 || UNUSED || - || - || <br />
|-<br />
| 216 || D20 || GND_DIV_CGEN || analogue gnd || GND –frequency divider – CLKGEN || <br />
|-<br />
| 217 || B20 || GND_CP_CGEN || analogue gnd || GND –Charge Pump – CLKGEN || <br />
|-<br />
| 218 || E19 || VDD_DIV_CGEN || analogue supply || 1.25V supply – frequency divider – CLKGEN || <br />
|-<br />
| 219 || C19 || UNUSED || - || - || <br />
|-<br />
| 220 || F18 || vr_rext || in || external 10 kOhm accurate reference resistor || <br />
|-<br />
| 221 || D18 || UNUSED || - || - || <br />
|-<br />
| 222 || B18 || DGND_CGEN || digital gnd || GND – CLKGEN || <br />
|-<br />
| 223 || A17 || DVDD_CGEN || digital supply || 1.25V supply- Digital supply for CLK GEN || <br />
|-<br />
| 224 || C17 || UNUSED || - || - || <br />
|-<br />
| 225 || E17 || VDD18_BIAS || analogue supply || 1.8V supply – Bias || <br />
|-<br />
| 226 || B16 || VDD_TPAD_TRF || analogue supply || 1.25V supply – TX PAD || <br />
|-<br />
| 227 || D16 || VDD18_TRF || analogue supply || 1.8V supply – TX RF || <br />
|-<br />
| 228 || F16 || UNUSED || - || - || <br />
|-<br />
| 229 || C15 || UNUSED || - || - || <br />
|-<br />
| 230 || E15 || UNUSED || - || - || <br />
|-<br />
| 231 || B14 || pa2on_2 || out || PA driver output RF pad PAD2, Channel 2 || <br />
|-<br />
| 232 || D14 || UNUSED || - || - || <br />
|-<br />
| 233 || A13 || pa2op_2 || out || PA driver output RF pad PAD2, Channel 2 || <br />
|-<br />
| 234 || F14 || UNUSED || - || - || <br />
|-<br />
| 235 || C13 || UNUSED || - || - || <br />
|-<br />
| 236 || B12 || pa1op_2 || out || PA driver output RF pad PAD1, Channel 2 || <br />
|-<br />
| 237 || E13 || UNUSED || - || - || <br />
|-<br />
| 238 || D12 || UNUSED || - || - || <br />
|-<br />
| 239 || C11 || pa1on_2 || out || PA driver output RF pad PAD1, Channel 2 || <br />
|-<br />
| 240 || F12 || UNUSED || - || - || <br />
|-<br />
| 241 || B10 || pa2on_1 || out || PA driver output RF pad PAD2, Channel 1 || <br />
|-<br />
| 242 || A9 || pa2op_1 || out || PA driver output RF pad PAD2, Channel 1 || <br />
|-<br />
| 243 || E11 || UNUSED || - || - || <br />
|-<br />
| 244 || D10 || UNUSED || - || - || <br />
|-<br />
| 245 || C99 || UNUSED || - || - || <br />
|-<br />
| 246 || B8 || pa1op_1 || out || PA driver output RF pad PAD1, Channel 1 || <br />
|-<br />
| 247 || A7 || pa1on_1 || out || PA driver output RF pad PAD1, Channel 1 || <br />
|-<br />
| 248 || F10 || UNUSED || - || - || <br />
|-<br />
| 249 || E9 || UNUSED || - || - || <br />
|-<br />
| 250 || D8 || UNUSED || - || - || <br />
|-<br />
| 251 || C7 || GND_TLOBUF_TRF || analogue gnd || Ground for TX LO buffers || <br />
|-<br />
| 252 || A5 || UNUSED || - || - || <br />
|-<br />
| 253 || F8 || VDD_TLOBUF_TRF || analogue supply || 1.25V supply – TX LO BUFFER || <br />
|-<br />
| 254 || D6 || VDDO_TLOBUF_TRF || analogue supply || || <br />
|-<br />
| 255 || C5 || UNUSED || - || - || <br />
|-<br />
| 256 || B4 || UNUSED || - || - || <br />
|-<br />
| 257 || E5 || xoscin_tx || in || TX XOSC buffer input || <br />
|-<br />
| 258 || C3 || UNUSED || - || - || <br />
|-<br />
| 259 || F6 || GND_TXBUF || analogue gnd || GND supply – TX XOSC buffer || <br />
|-<br />
| 260 || B2 || UNUSED || - || - || <br />
|-<br />
| 261 || D4 || UNUSED || - || - || <br />
|-<br />
|}<br />
<br />
==Typical application==<br />
===RF section example===<br />
[[File:Lms7002m-typical-rf-application-circuit.png|center|550px|LMS7002M in a typical RF application circuit]]<br />
<br />
A typical application circuit of the LMS7002M is given above. Note that only the RF part of a single MIMO TRX chain is shown. More details can be found in the LMS7002M evaluation board schematics.<br />
<br />
===Digital interface configuration example===<br />
[[File:Lms7002m-typical-digital-interface-configuration.png|center|550px|LMS7002M in a typical digital interface configuration]]<br />
<br />
The above figure shows one useful example of clock generation and distribution as well as interfacing the LMS7002M to a digital BB modem. Note that interface control signals such as ENABLE, TXNRX, IQSEL are not shown for clarity. As can be seen, CLKPLL block generates a 491.52 MHz (integer multiple of 61.44 MHz) clock. CLKPLL output is divided by a programmable divider (division set to 4 in this example) to construct a 122.88 MHz clock driving DACs, TXTSP, and the TX part of LimeLight™. Similarly, CLKPLL output is divided by fixed division of 4 to construct 122.88 MHz clock driving ADCs, RXTSP, and the RX part of LimeLight™. Interpolation and decimation are both set to 2. This configuration provides a 245.76 MS/s double data rate (DDR) interface to the BB modem. This translates into the overall system performance as below:<br />
* TX/RX IF bandwidth: 20MHz<br />
* TX/RX RF bandwidth: 40MHz<br />
* Digital interpolation image suppression: 60dB<br />
* DACs analog image suppression: 72dB<br />
* ADCs analog alias suppression: 43dB assuming no off chip filtering<br />
* Digital decimation alias suppression: 60dB<br />
<br />
==Ordering information==<br />
{| class="wikitable"<br />
!Model !! Temperature range range !! Package description<br />
|-<br />
|LMS7002M || -40&deg;C to +85&deg;C || 261-pin aQFN<br />
|-<br />
|LMS7002M-REEL || -40&deg;C to +85&deg;C || 261-pin aQFN<br />
|-<br />
|LMS7002M-EVB || || Evaluation board<br />
|}<br />
<br />
==Disclaimer==<br />
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Lime Microsystems products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Lime Microsystems hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRRANTIES OF MERCHANTABILITY, NON-INFRIGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Lime Microsystems shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Lime Microsystems had been advised of the possibility of the same. Lime Microsystems assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties. Lime Microsystems products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Lime Microsystems products in Critical Applications.<br />
<br />
==Document Version==<br />
Based on LMS7002M Datasheet v2.8.0.<br />
<br />
Changes since document generation:<br />
* Minor typographical and grammatical changes.<br />
<br />
{{LimeMicro}}</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Lms7002m-typical-digital-interface-configuration.png&diff=826
File:Lms7002m-typical-digital-interface-configuration.png
2016-06-02T20:52:12Z
<p>Ghalfacree: LMS7002M in a typical digital interface configuration</p>
<hr />
<div>LMS7002M in a typical digital interface configuration</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Lms7002m-typical-rf-application-circuit.png&diff=825
File:Lms7002m-typical-rf-application-circuit.png
2016-06-02T20:47:28Z
<p>Ghalfacree: LMS7002M in a typical RF application circuit</p>
<hr />
<div>LMS7002M in a typical RF application circuit</div>
Ghalfacree
https://wiki.myriadrf.org/index.php?title=File:Lms7002m-261l-aqfn-package-top.png&diff=824
File:Lms7002m-261l-aqfn-package-top.png
2016-06-02T20:24:35Z
<p>Ghalfacree: LMS7002M in 261L aQFN package, top view</p>
<hr />
<div>LMS7002M in 261L aQFN package, top view</div>
Ghalfacree