LimeMicro:LMS6002D Programming and Calibration

Description
The functionality of the LMS6002 transceiver is fully controlled by a set of internal registers which can be accessed through a serial port interface. Both write and read operations are supported. The serial port can be configured to run in 3 or 4 wire mode with the following pins used:


 * SEN - serial port enable, active low
 * SCLK - serial clock
 * SDIO - serial data in/out in 3 wire mode, serial data input in 4 wire mode
 * SDO-serial data out in 4 wire mode, don’t care in 3 wire mode

Serial port key features:
 * 16 serial clock cycles are required to complete write operation
 * 16 serial clock cycles are required to complete read operation
 * Multiple write/read operations are possible without toggling serial enable signal

All configuration registers are 8-bit wide. Write/read sequence consists of 8-bit instruction followed by 8-bit data to write or read. The MSB of the instruction bit stream is used as SPI command, where CMD = 1 for write and CMD = 0 for read. Next 3 bits represent the block address, since LMS6002 configuration registers are divided into eight logical blocks as shown in the LMS6002Dr2 Memory Map. The remaining 4 bits of the instruction are used to address particular registers within the block as detailed in the Memory Map Description. Use address values from the tables.

Write/read cycle waveforms are shown below. Note that write operation is the same for both 3-wire and 4-wire modes. Although not shown in the figures, multiple byte write/read is possible by repeating instruction/data sequence while keeping SEN low.

TX/RX PLL Configuration (User Mode)

 * Shadow registered

TX RF Modules Configuration (User Mode)
{| class="wikitable" ! Address (7 bits) !! Bits !! Description
 * rowspan="3"|0x40 || 7-2 || Not used.
 * 1 || EN : TXRF modules enable
 * 0 – TXRF modules powered down.
 * 1 – TXRF modules enabled. (Default)
 * 0 || DECODE:
 * 0 – Decode control signals. (Default)
 * 1 – Use control signals from test mode registers.
 * rowspan="3"|0x41 || 7-5 || Not used.
 * 4-0 || VGA1GAIN[4:0]: TXVGA1 gain, log-linear control. LSB=1dB, encoded as shown below.
 * || Default: 00010101
 * rowspan="2"|0x42 || 7-0 || VGA1DC_I[7:0]: TXVGA1 DC shift control, LO leakage cancellation. LSB=0.0625mV, encoded as shown below.
 * || Default: 10000000
 * rowspan="2"|0x43 || 7-0 || VGA1DC_Q[7:0]: TXVGA1 DC shift control, LO leakage cancellation LSB=0.0625mV, encoded as shown below.
 * 4-0 || VGA1GAIN[4:0]: TXVGA1 gain, log-linear control. LSB=1dB, encoded as shown below.
 * || Default: 00010101
 * rowspan="2"|0x42 || 7-0 || VGA1DC_I[7:0]: TXVGA1 DC shift control, LO leakage cancellation. LSB=0.0625mV, encoded as shown below.
 * || Default: 10000000
 * rowspan="2"|0x43 || 7-0 || VGA1DC_Q[7:0]: TXVGA1 DC shift control, LO leakage cancellation LSB=0.0625mV, encoded as shown below.
 * || Default: 10000000
 * rowspan="2"|0x43 || 7-0 || VGA1DC_Q[7:0]: TXVGA1 DC shift control, LO leakage cancellation LSB=0.0625mV, encoded as shown below.
 * rowspan="2"|0x43 || 7-0 || VGA1DC_Q[7:0]: TXVGA1 DC shift control, LO leakage cancellation LSB=0.0625mV, encoded as shown below.
 * rowspan="2"|0x43 || 7-0 || VGA1DC_Q[7:0]: TXVGA1 DC shift control, LO leakage cancellation LSB=0.0625mV, encoded as shown below.


 * || Default: 10000000
 * rowspan="5"|0x44 || 7-5 || Not used.
 * 4-3 || PA_EN[2:0]: VGA2 power amplifier (TX output) selection.
 * 2 || PA_EN[2]: AUXPA, auxiliary (RF loopack) PA power down.
 * 0 – Powered up. (Default)
 * 1 – Powered down.
 * 1-0 || Not used.
 * || Default: 00001011
 * rowspan="3"|0x45 || 7-3 || VGA2GAIN[4:0]: TXVGA2 gain control, log-linear control. LSB=1dB, encoded as shown below.
 * 2-0 || ENVD[2:0]: Controls envelop/peak detector analogue MUX.
 * ENVD[2]: Selects the signal for AC coupling, MUX provides:
 * 0 – Reference DC generated inside the selected detector. (Default)
 * 1 – Average of the selected detector output.
 * ENVD[1:0]: Detector select, MUX provides
 * 00 – AUXPA envelop detector output (Default)
 * 01 – AUXPA peak detector output.
 * 10 – PA1 envelop detector output.
 * 11 – PA2 envelop detector output.
 * || Default: 00000000
 * rowspan="5"|0x46 || 7-4 || PKDBW[3:0]: Controls the bandwidth of the envelop and peak detectors.
 * 0000 – Minimum bandwidth, envelop ~1MHz, peak 30kHz. (Default)
 * 1111 – Maximum bandwidth, envelop ~15MHz, peak ~300KHz.
 * 3-2 || LOOPBBEN[1:0]: Base band loopback switches control.
 * 00 – Switch open. (Default)
 * 11 – Switch closed.
 * 1 || FST_PKDET: Shorts the resistor in the envelop/peak detector to speed up charging for faster response. After the initial charge up, it should be disabled to achieve a LPF function.
 * 0 – Switch open, LPF function in effect. (Default)
 * 1 – Resistor shorted (no LPF function).
 * 0 || FST_TXHFBIAS: Bias stage of high frequency TX part has large resistors to filter the noise. However, they create large settling time. This switch can be used to short those resistors during the initialization and then it may be needed to open it to filter the noise, in case the noise is too high.
 * 0 – Switch open (noise filtering functional). (Default)
 * 1 – Resistors shorted (short settling - no noise filtering).
 * || Default: 00000000
 * rowspan="3"|0x47 || 7-4 || ICT_TXLOBUF[3:0]: Controls the bias current of the LO buffer. Higher current will increase the linearity. LSB=5/6mA.
 * 0000 – Minimum current.
 * 0110 – TXMIX takes 5mA for buffer. (Default)
 * 1111 – Maximum current.
 * 3-0 || VBCAS_TXDRV[3:0]: The linearity of PAs depends on the bias at the base of the cascode NPNs in the PA cells. Increasing the VBCAS will lower the base of the cascode NPN.
 * 0000 – Maximum base voltage. (Default)
 * 1111 – Minimum base voltage.
 * || Default: 01100000
 * rowspan="3"|0x48 || 7-5 || Not used.
 * 4-0 || ICT_TXMIX[4:0]: Controls the bias current of the mixer. Higher current will increase the linearity. LSB=1mA.
 * 00000 – 0mA.
 * 01100 – TXMIX takes 12mA for each cell. (Default)
 * 11111 – 31mA.
 * || Default: 00001100
 * rowspan="3"|0x49 || 7-5 || Not used.
 * 4-0 || ICT_TXDRV[4:0]: Controls the bias current of the PAs. Higher current will increase the linearity. LSB=1mA.
 * 00000 – 0mA.
 * 01100 – PAs take 12mA for each cell. (Default)
 * 11111 – 31mA.
 * || Default: 00001100
 * }
 * 0000 – Maximum base voltage. (Default)
 * 1111 – Minimum base voltage.
 * || Default: 01100000
 * rowspan="3"|0x48 || 7-5 || Not used.
 * 4-0 || ICT_TXMIX[4:0]: Controls the bias current of the mixer. Higher current will increase the linearity. LSB=1mA.
 * 00000 – 0mA.
 * 01100 – TXMIX takes 12mA for each cell. (Default)
 * 11111 – 31mA.
 * || Default: 00001100
 * rowspan="3"|0x49 || 7-5 || Not used.
 * 4-0 || ICT_TXDRV[4:0]: Controls the bias current of the PAs. Higher current will increase the linearity. LSB=1mA.
 * 00000 – 0mA.
 * 01100 – PAs take 12mA for each cell. (Default)
 * 11111 – 31mA.
 * || Default: 00001100
 * }
 * 4-0 || ICT_TXDRV[4:0]: Controls the bias current of the PAs. Higher current will increase the linearity. LSB=1mA.
 * 00000 – 0mA.
 * 01100 – PAs take 12mA for each cell. (Default)
 * 11111 – 31mA.
 * || Default: 00001100
 * }
 * }

TX/RX PLL
The frequency setting for both TX and RX PLLs is the same as described here. TX PLL SPI registers are at x001xxxx and TX PLL registers are at x010xxxx.

To configure the PLL there are a number of variables which need to be set.
 * Integer and fractional part of the divider.
 * FRANGE value.
 * VCO CAP, charge pump current (Icp) and charge pump offset current (Ioff).

This assumes the given loop filter value with a loop BW of 100kHz is used.

FREQSEL
To simplify the TX/RX PLL register setup the FRANGE and SELVCO register are combined to FREQSEL register. The frequency range and FREQSEL[5:0] value table is reproduced below.

For example, UMTS Band I centre frequency 2140MHz is in the range 1.86 to 2.285GHz, hence FREQSEL = 100100 (0x24).

Integer and Fractional Part of the Divider
For wanted LO frequency $$\mathit{f_{LO}}$$ and given PLL reference clock frequency $$\mathit{f_{REF}}$$, calculate calculate integer and fractional part of the divider as below.

First, find temporary variable $$x$$ from the 3 least significant bits of the $$\mathit{FREQSEL}$$ value:

$$x = 2 ^ {\mathit{FREQSEL}[2:0] - 3}$$

Use $$x$$ to calculate $$\mathit{NINT}$$ and $$\mathit{NFRAC}$$:

$$\mathit{NINT} = \biggl\lfloor {x * \mathit{f_{LO}} \over \mathit{f_{REF}}} \biggr\rfloor$$

$$\mathit{NFRAC} = \biggl\lfloor 2 ^ {23} \biggl[ {x * \mathit{f_{LO}} \over \mathit{f_{REF}}} - \mathit{NINT} \biggr] \biggr\rfloor$$

and store the values in $$\mathit{NINT}$$/$$\mathit{NFRAC}$$ registers at address 0x10-0x13 for TXPLL and 0x20-0x23 for RX PLL.

For example $$\mathit{f_{LO}}$$ is band 1 centre frequency of 2140MHz, and $$\mathit{f_{REF}}$$ = 30.72MHz:

$$\mathit{FREQSEL}[5:0] = 0\mathrm{b}100100, \mathit{FREQSEL}[2:0] = 0\mathrm{b}100 = 0 \mathrm{x} 4 = 4$$

$$x = 2 ^ {\mathit{FREQSEL}[2:0] - 3} = 2 ^ {4 - 3} = 2 ^ 1 = 2$$

$$\mathit{NINT} = \biggl\lfloor {x * \mathit{f_{LO}} \over \mathit{f_{REF}}} \biggr\rfloor = \biggl\lfloor {2 * 2140 \over 30.72} \biggr\rfloor = 139$$

$$\mathit{NFRAC} = \biggl\lfloor 2 ^ {23} \biggl[ {x * \mathit{f_{LO}} \over \mathit{f_{REF}}} - \mathit{NINT} \biggr] \biggr\rfloor = \biggl\lfloor 2 ^ {23} \biggl[ {2 * 2140 \over 30.72} - 139 \biggr] \biggr\rfloor = 2708821$$

VCO Capacitor, Icp and Ioff Selection
For the PLL loop filter implemented on the evaluation board, loop bandwidth of 100kHz and optimum PLL phase noise performance, the following charge pump current setup is recommended.
 * Charge pump current Icp=1200uA (default).
 * Charge pump current offset up Ioff up = 30uA.
 * Charge pump current offset down Ioff down = 0uA (default).

Regarding VCOCAP selection, a flexible algorithm based on monitoring on chip Vtune comparators state is developed as described below.



Typical measured Vtune variation with the VCOCAP codes for the two target LO frequencies, 1.95GHz and 2.14GHz. Obviously, Vtune is changing from 2.9V down to 0V. However, PLL lock is guaranteed only when Vtune is in the range 0.5V-2.5V. Also, for the best phase noise performance, Vtune should be kept around the middle of the range i.e. 1.5V.

There are two on chip Vtune comparators per PLL as shown in PLL Control. Their threshold voltages are set to Vth Low=0.5V and Vth High=2.5V. The state of the comparators can be obtained by powering them up (register 0x1B for TXPLL or 0x2B for RXPLL, bit 3) and reading the register 0x1A for TXPPLL or 0x2A for RXPLL, bits 7-6. True table is given below.

These can be used to choose VCOCAP code. All we need to find is the code CMIN when comparators change the state from “10” to “00” and the code CMAX when the comparators change the state from “00” to “01”. Optimum VCOCAP code is then the middle one between CMIN and CMAX. For LO=2.4GHz, this is illustrated in VCO Capacitor, Icp and Ioff Selection. In this case, optimum code is around 41.

The algorithm is summarised as below.
 * 1) Select correct FREQSEL.
 * 2) Set target LO frequency (NINT, NFRAC) as explained in Integer and Fractional Part of the Divider
 * 3) Sweep VCOCAP codes from 0-63. Monitor the state of Vtune comparators.
 * 4) Record the code CMIN when Vtune comparators state changes from "10" to "00" (PLL enters 'in range' state).
 * 5) Record the code CMAX when Vtune comparators state changes from "00" to "01" (PLL leaves 'in range' state).
 * 6) Select the middle code between CMIN and CMAX ( C=(CMIN+CMAX)/2 ).

Note that faster search algorithm (replacement for step 3 above) can be implemented as shown in VCO and VCOCAP Code Selection Algorithm.

Once the PLL is set, Vtune comparators can also be used as lock (in range) indication.

Auto Calibration Summary
The following is recommended auto calibration sequence.
 * 1) DC offset cancellation of the LPF tuning module.
 * 2) LPF bandwidth tuning.
 * 3) DC offset cancellation of the TXLPF.
 * 4) DC offset cancellation of the RXLPF.
 * 5) DC offset cancellation of the RXVGA2.

Please note, while executing DC calibration procedures no TX/RX inputs should be applied.

LMS6002D has on-chip DACs for TX LO leakage calibration. Those DACs have been designed to provide around -50/-60dBc LO leakage cancellation.

Applying IQ Gain Offset to Baseband Signals
Software in baseband initially applies course gain variation on the I or Q channel and measures the loopbacked signal via the LMS6002D receiver to measure the optimum value. The example block for gain correction is shown below.



This block implements the following equation:

$$ \begin{align} \mathit{Iout} = \mathit{Iin} * \mathit{G\_I} \\ \mathit{Qout} = \mathit{Qin} * \mathit{G\_Q} \end{align} $$

$$\mathit{G\_I}$$ and $$\mathit{G\_Q}$$ are programmable correction factors which are altered by the BB modem to minimise unwanted side band component.

Applying IQ Phase Band Offset Baseband Signals
The baseband S/W applies a course phase multiplier on the I or Q channel and measures the loopbacked signal via the LMS6002D receiver to measure the optimum value. The process is then repeated using a finer control step to ascertain the optimum phase and gain offset value to be applied. The example block for gain correction shown below.



IQ phase correction is in fact equivalent to vector rotation. If quadrature phase error is $$\alpha$$, then I and Q vectors are both rotated by $$\alpha/2$$ but in opposite directions hence IQ outputs of the corrector are 90&deg; phase shifted. IQ phase correction equations are given below:

$$ \begin{align} \mathit{Iout} = \mathit{Iin} + \mathit{Qin} * \tan \biggl( {\alpha \over 2} \biggr) \\ \mathit{Qout} = \mathit{Qin} + \mathit{Iin} * \tan \biggl( {\alpha \over 2} \biggr) \end{align} $$

The value of $$\tan(\alpha/2)$$ is used as a programmable correction parameter. BB modem should alter this value to minimise unwanted side band component.

Correcting RX I and Q DC Levels
Software in the receiver baseband is required to calibrate the DC level on the I and Q channel received. The process of applying DC level adjustment to the I & Q channel is an optional requirement required for fine tuning purposes only. The methodology of correcting the DC levels is shown in the diagram below.



The averaging (COMB) filter calculates the DC of the corrector input and that DC is subtracted to cancel it. The loop is running all the time so any change of the RX DC due to the signal level change, RX gain change or temperature will be tracked and cancelled automatically. The loop only programmable parameter is DCAVG which defines averaging window size.

Document Version
Based on LMS6002DR2 Programming and Calibration Guide 1_1R5, Version 1 Revision 4.

Changes since document generation:
 * Updated General DC Calibration Procedure diagram.
 * Minor formatting changes and corrections.