LimeSDR-QPCIe v1.2 hardware description

Introduction
LimeSDR-QPCIe is low-cost software defined radio board based on Lime LMS7002M Field Programmable Radio Frequency (FPRF) transceiver and Altera Cyclone V PFGA, through which apps can be programmed to support any type of wireless standard, e.g. UMTS, LTE, LoRa, GPS, WiFi, Zigbee, RFID, Digital Broadcastimng, Radar and many more.

LimeSDR-QPCIe Board Key Features
The LimeSDR-QPCIe development board provides a hardware platform for developing and prototyping high-performance and logic-intensive digital and RF designs using Altera’s Cyclone V FPGA and Lime Microsystems transceiver.



For more information on the following topics, refer to the respective documents:
 * Cyclone V device family, refer to Cyclone V Device support resources link
 * LMS7002M transceiver resources link

LimeSDR-QPCIe v1.2 board features:
 * USB Interface
 * Cypress FX3 Super Speed USB 3rd generation controller
 * FPGA Features
 * Cyclone V, 5CGXFC7D7F31C8N device in 896-pin FBGA package
 * 150’000 logic elements
 * 6860 Kbits embedded memory
 * 312 embedded 18x18 multipliers
 * 7 PLLs
 * 9 Transceivers (2.5Gbps)
 * PCIe Hard IP Blocks
 * 2 Hard Memory Controllers


 * FPGA Configuration
 * JTAG mode configuration
 * Active serial mode configuration
 * Possibility to update FPGA gateware by using FX3 (USB)
 * Possibility to update FPGA gateware by using PCIe interface.


 * RF
 * 2x LMS7002M, FPRF transceivers
 * Onboard RSSI measurement circuits
 * Onboard loopback control switches


 * DACs and ADCs
 * 2x DAC5672A, dual, 14-bit, Digital-To-Analog converters
 * 1x ADS424, Dual-Channel, 14-bit, Analog-To-Digital converter


 * Memory Devices
 * 4 x 2Gbit DDR3 SDRAM (128M x 16)
 * 4Mbit flash for FX3 firmware
 * 128Mbit flash for FPGA gateware
 * 2 x 128Kbit and 2 x 512Kbit EEPROMs for LMS MCU firmware, LMS MCU data
 * 1 x 128K EEPROM for FX3 or FPGA data


 * Connections
 * microUSB3.0 (type B) connector
 * PCIe x4 edge connector (Gen1)
 * Coaxial RF (U.FL) connectors
 * 2x PMOD header (0.1” pitch)
 * FPGA (0.1” pitch) and FX3 (0.05” pitch) JTAG connectors
 * 12V DC power jack and pinheader
 * LVDS connector (0.05” pitch)
 * Fan connector (12V/5V)
 * PCIe 6-pin power connector
 * Holder for coin cell CR1220 battery


 * Clock System
 * 30.72MHz VCTCXO (precision: ±1 ppm initial, ±4 ppm stable).
 * Possibility to lock VCTCXO to external clock using ADF4002 or tune VCTCXO by onboard DAC (AD5662)
 * Programmable clock generator for the FPGA reference clock input or LMS PLLs
 * VCTCXO clock output for external device synchronization.
 * 1x 100 MHz, 4 x 125MHz crystal oscillators for FPGA


 * Miscellaneous devices
 * LM75 Digital temperature sensor with 2-Wire Interface.
 * DS3231 real-time clock.
 * M0578-A3 GPS/GNSS module receiver


 * Board Size 190mm x 106.7mm (7.48” x 4.20”)

LimeSDR-QPCIe Board Overview
LimeSDR-QPCIe board version 1.2 picture with highlighted major connectors presented in Figure 2. There are three connector types – data and debugging (PCIe, USB3.0, PMOD, LVDS and JTAG), power (DC jack and external supply pinheaders) and high frequency (RF and reference clock).

Board components description listed in the Table 1.

LimeSDR-QPCIe board version 1.2 picture with highlighted top components are presented in Figure 3.

LimeSDR-QPCIe board version 1.2 picture with highlighted bottom components is presented in Figure 4.



LimeSDR-QPCIe Board Architecture
The heart of the LimeSDR-QPCIe board is Altera Cyclone V GX FPGA. Its main function is to transfer digital data between the PC through an edge PCIE and a USB3.0 connector. The block diagram for LimeSDR-QPCIe board is presented in the Figure 5.

FPGA configuration
FPGA is set to use x1 Active Serial (AS) configuration scheme. In this scheme if valid configuration file exists in FLASH memory (IC30 or IC32) it is automatically loaded after power is applied to the board. In Table 2 it is listed resistor setup for Active Serial (AS) configuration mode select.

There are two options which allows to change configuration file in FLASH memory:
 * USB 3.0 controller – CYUSB3013 (IC42) has access to configuration memory. With valid firmware and software, gateware for FPGA can be uploaded into FLASH memory (IC30 or IC32) by using USB3.0 cable. IC42 can initiate FPGA reconfiguration. For signal interconnect details see chapter 2.2.2.3 USB 3.0 Controller.
 * JTAG Header – 10pin connector (J26) provides access to FPGA JTAG chain. By using external download cable such as USB-Blaster and Quartus II Programmer software FLASH memory (IC30 or IC32) can be reprogrammed. JTAG connections are listed in Table 3.

Main components
This chapter describes main components mounted on LimeSDR-QPCIe v1.2 board.

LMS7002M RF transceiver
There are two LMS7002M field programmable RF transceiver ICs (LMS7002M#1 - IC1 and LMS7002M#1 - IC2), interface signals can be acknowledged by corresponding names LMSx_*, where x can be 1 or 2. For example LMS1_* signals belongs to IC1 and LMS2_* belongs to IC2.

In the following manner interface and control signals are described below:


 * Digital Interface Signals: LMS7002 is using data bus LMSx_DIQ1_D[11:0] and LMSx_DIQ2_D[11:0], LMSx_ENABLE_IQSEL1 and LMSx_ENABLE_IQSEL2, LMSx_FCLK1 and LMSx_FCLK2, LMSx_MCLK1 and LMSx_MCLK2 signals to transfer data to/from FPGA. Indexes 1 and 2 indicate transceiver digital data PORT-1 or PORT-2. Any of these ports can be used to transmit or receive data. By default, PORT-1 is selected as receive port and PORT-2 is selected as transmit port. The FCLK# is input clock and MCLK# is output clock for LMS7002M transceiver. TXNRX signals sets ports directions. For LMS7002M interface timing details refer to LMS7002M transceiver datasheet page 12-13.


 * LMS Control Signals: these signals are used for optional functionality:
 * LMSx_RXEN, LMSx_TXEN – receiver and transmitter enable/disable signals.
 * LMS_RESET – LMS7002M reset signal.


 * SPI Interface: LMS7002M transceiver is configured via 4-wire SPI interface; FPGA_SPI0_SCLK, FPGA_SPI0_MOSI, FPGA_SPI0_MISO_LMSx, FPGA_SPI0_LMSx_SS. The SPI interface controlled from FPGA.


 * LMS I2C Interface: LMS EEPROM are connected to this interface. The signals LMSx_I2C_SCL, LMSx_I2C_DATA is not connected to FPGA

The Table 4 and Table 5below lists RF transceiver respectively LMS7002#1 and LMS7002#2 pins, schematic signal names, FPGA interconnections and I/O standard.

SDRAM
LimeSDR-QPCIe board has four 2Gb DDR3 SDRAM memory ICs (AS4C128M16D3B-12BCN [link]) which are connected to Cyclone V GX FPGA. The memory can be used for data manipulation at high data rates between transceiver and FPGA. There are two independent DDR3 SDRAM interfaces:
 * DDR3 TOP – this is 32bit data interface which consist of two x16 memory devices (IC33 AND IC34) with a single address and command bus. Interface is connected to FPGA Bank 7A and 8A and uses hard memory controller. Error! Reference source not found. lists DDR3 TOP interface pins.
 * DDR3 BOT – this is 32bit data interface which consist of two x16 memory devices (IC35 AND IC36) with a single address and command bus. Interface is connected to FPGA Bank 3B and 4A and uses hard memory controller. lists DDR3 BOT interface pins.

Following Table 6 lists signal and pin information for DDR3 TOP interface and Table 7 for the DDR3 BOT interface.

USB 3.0 Controller
Software can control LimeSDR-QPCIe board via the USB3 microcontroller (CYUSB3013 (FX3) [link]). The data transfer to/from the board, SPI communication, FPGA configuration is done via the USB3 controller. The controller signals description showed below:


 * FX3_DQ[15:0] - FX3 16-bit GPIF data interface is connected FPGA.
 * FX3_CTL[12:0] - FX3 GPIF interface control signals.
 * FX3_PCLK - GPIF interface clock, connected to FPGA.
 * FX3_SPI - interface is used to program FX3 firmware flash or FPGA configuration flash memory.
 * FX3 I2C - bus is connected to the main I2C bus.
 * PMODE[2:0] – boot options, by default boot from SPI and USB boot is enabled. If J28 jumper is present or R313 is soldered FX3 will boot from IC43 flash memory if correct firmware exists.
 * SW1 – resets FX3
 * J29 – FX3 JTAG programming/debugging pin header.

In the Table 8 are listed USB3.0 controller (FX3) pins, schematic signal name, FPGA interconnections and I/O standard.

ADC
There is one Dual-Channel 14-Bit, analog-to-digital converter (ADS4246 – IC37) mounted on board. ADC analog input is connected to RX BB outputs of LMS7002M#1 IC. Digital output pins are connected to FPGA.

The Table 9 lists 14-bit analog to digital converter ADC (IC37) pins, schematic signal name, FPGA interconnections and I/O standard.

DACs
LimeSDR-QPCIe board has two 14-Bit Dual Transmit Digital-To-Analog Converters. By default, analog output pins are connected to TX BB input pads of LMS70002M#1 IC. By changing on-board resistors it can be connected to LMS70002M#2 instead. To connect DACs to LMS70002M#2 TX BB input pads R268, R271, R275, R279, R270, R274, R278, R282 resistors has to be removed and R269, R273, R277, R281, R272, R276, R280, R283 resistors has to be fitted.

The tables below list 14-bit digital to analog converter DAC#1 (IC40 - Table 10) and DAC#2 (IC41 - Table 11) pins, schematic signal name, FPGA interconnections and I/O standard.

GNSS receiver
LimeSDR-QPCIe board has GNSS receiver module GPS/GNSS M0578 (IC48). External active antenna for this module can be connected to J34 connector. Module is connected to FPGA (IC29), pin connections can be found on Table 12.

RTC
For applications which requires accurate time LimeSDR-QPCIe has mounted Real-Time-Clock DS3231 (IC50). Pin connections can be found in Table 13. For I2C interface see chapter 2.2.4.2 I2C interfaces.

Temperature sensor
Board temperature can be measured with LM75 (IC47) temperature sensor using its I2C interface. Pin connections can be found in Table 13. For I2C interface of this sensor see chapter 2.2.4.2 I2C interfaces.

Connectors
This chapter describes connectors that exists on LimeSDR-QPCIe v1.2 board.

PCI Express connector
For data transfer LimeSDR – QPCIe board has PCI express connector with four lanes. PCI express interface is implemented in FPGA. Pin connection and corresponding signal names are listed in Table 15.

LVDS connector
J30 is dedicated connector for FPGA transceiver (LVDS) applications.

PMOD connectors
Two 10 pin 0.1” right angle PMOD connectors (J31, J32) are connected to the FPGA. A complete pinout description, dedicated FPGA pins and their I/O standard is presented in the tables below.

Low Speed Interfaces
This chapter describes low speed interfaces on LimeSDR-QPCIe v1.2 board which are dedicated to communicate between various board components.

LimeSDR-QPCIe board low speed interface is divided into FPGA-RF and FPGA-FX3 groups and are presented in Figure 6 and Figure 7. The latter block diagrams depict the main ICs, corresponding IC pin numbers, data buses and serial protocol addresses.



LimeSDR-QPCIe board peripherals can be controlled via USB interface. All commands that comes from USB are firstly processed by FX3 controller. I2C and multiple SPI interfaces provide connection to various on-board ICs, such as temperature sensor, port expander, clock generator, memory and real-time clock (RTC).



SPI interfaces
There are several SPI interfaces with their slave devices:
 * FX3_SPI - Master of this bus is CYUSB3013 (IC42) and this bus has these slave devices:
 * Flash memory M25P40 (IC43) dedicated for FX3 firmware;
 * Flash memory W25Q128 (IC30) or S25FL128 (IC32) dedicated for FPGA configuration file. Using switch (IC31) flash memory is switched from FPGA to FX3_SPI BUS. Then flash content is updated and flash memory is switched back to FPGA. This is done when it is needed to update FPGA gateware in flash memory.
 * FPGA (IC29) - If SPI slave is implemented in FPGA logic it can be accessed through FX3_SPI interface.


 * FPGA_SPI0 – master of this interface is FPGA (IC29), slave devices of this interface:
 * RFIC LMS7002M (IC1)
 * RFIC LMS7002M (IC2)
 * 14-bit ADC ADS4246 (IC37)
 * XO VC DAC AD5662 (IC54)
 * Phase detector ADF4002 (IC53)


 * FPGA_SPI1: master of this interface is FPGA (IC29), slave devices of this interface:
 * Flash memory M25P40 (IC46)


 * FPGA_SPI2: master of this interface is FPGA (IC29), slave devices of this interface:
 * 6x ADC (IC18, IC20, IC23, IC25, IC26, IC28) dedicated for onboard RSSI use.

I2C interfaces
Board has three independent I2C interfaces: I2C, LMS1_I2C and LMS2_I2C. I2C – master of this interface can be either FX3 (IC42) or either FPGA (IC29). Master selection is done through R287 and R288 resistors. By default, master is FX3 (resistors fitted). To select FPGA as master, remove R287 and R288 resistors. This interface has several slave devices which are listed in Table 23.
 * RTC DS3231 (IC50);
 * EEPROM M24128 (IC51);
 * Temperature sensor LM75 (IC47), EEPROM and clock generator. Information for slave devices are provided in Table 23, signal connectivity information is in Table 24.


 * LMS1_I2C: this interface has two EEPROMs. This interface is only accessible from LMS7002M (IC1). In Table 25 are listed all LMS1_I2C slave devices and their information. In Table 26 listed pin connections.


 * LMS2_I2C: this interface has two EEPROMs. This interface is only accessible from LMS7002M (IC2). In Table 27 are listed all LMS1_I2C slave devices and their information. In Table 28 listed pin connections.

UART
UART interface is dedicated for communication between FPGA and GNSS receiver GPS/GNSS M0578 (IC48).

User I/O
This chapter describes available inputs and outputs of LimeSDR-QPCIe v1.2 board which can be used for user applications.

FPGA switch
4 poles slide switch SW2 is connected to FPGA and can be used to implement additional functionality which requires input control. Each switch line has external pull up resistors. When switch is in position “On”, it pulls down the line to logic ‘0’ level.



In Table 30 are listed each switch line and correspond FPGA pins.

Indication LEDs
LimeSDR-QPCIe board comes with four single colour (green) general purpose LEDs, one general purpose dual colour (red-green) LED, one green LED informing about successful FPGA configuration and one for power indication.



All LEDs are connected to FPGA and their function can be changed except for LED1. Default LEDs functions and other information are listed in the table below.

RF Loopback Control
There is RF loopback circuit for RF transceivers which can be controlled from FPGA through shift registers 74HC595 (IC7 and IC8). Pin connection can be found in Table 32.

Note 1: 	Schematic signals corresponds to IC7 pins as below: Q0 – LMS1_TX2_2_LB_SH	Q1 – LMS1_TX2_2_LB_AT	Q2 – LMS1_TX1_2_LB_SH	Q3 – LMS1_TX1_2_LB_AT Q4 – LMS1_TX1_2_LB_H	Q5 – LMS1_TX1_2_LB_L	Q6 – LMS1_TX2_2_LB_H	Q7 – LMS1_TX2_2_LB_L

Note 1: Q0 – LMS2_TX2_2_LB_L	Q1 – LMS2_TX2_2_LB_H	Q2 – LMS2_TX1_2_LB_L	Q3 – LMS2_TX1_2_LB_H Q4 – LMS2_TX2_2_LB_AT	Q5 – LMS2_TX1_2_LB_SH	Q6 – LMS2_TX1_2_LB_AT	Q7 – LMS2_TX2_2_LB_SH

The table below describes RF transceiver LMS7002#1 and LMS7002#2 external loopback configuration, pins, schematic signal name, FPGA interconnections and I/O standard.

Board Temperature Control
LimeSDR-QPCIe has integrated temperature sensor (IC47) which controls FAN to keep board in operating temperature range. FAN has dedicated holes for mounting over the main digital ICs (FPGA, DDRs, DACs and ADC) and must be connected to J33 (0.1” pitch) connector. Fan will be turned on when board heats up to 55°C and will be turned off when the temperature reduces to 45°C.



Measured temperature value can read by using LimeSuiteGUI as described in chapter “3.13 Reading Board Temperature”. LimeSDR-QPCIe board comes with a dedicated 60mm DC FAN mounting space. Three M3 exposed copper holes (connected to board GND plane) and a space for a standoff are provided and are shown in Figure 11. The hole centre to hole centre distance is 50mm.The FAN is controlled via J33 (0.1” pitch) connector which can provide either 12V (default) or a 5V supply rail. The gate of the FAN driving MOSFET is connected to IC29 (FPGA) pin J22 (2.5V/3.3V bank).



Clock Distribution
LimeSDR-QPCIe board clock distribution block diagram is presented in Figure 12.



Main clock sources
There are various crystal oscillators with various frequencies mounted on LimeSDR-QPCIe board. The programmable clock generator IC37 (Si5351C [link]) can generate any reference clock frequency, starting from 8 kHz – 160 MHz, for FPGA and LMS PLLs. A real-time clock (RTC) chip (IC50) is also included on the LimeSDR-QPCIe board. The output of IC50 is connected to the FPGA pin H17. Main clock sources and destinations are listed in Table 36.

Clock buffer source selection
Clock buffer (IC52) presented in Figure 12 provides clock signals for following components:
 * LMS7002 transceivers (IC1, IC2);
 * FPGA (IC29) pin AB17;
 * Phase detector (IC53);
 * Clock generator (IC57);
 * U.FL connector J35 (REF CLK OUT label on board). To use this output 0R resistor R378 has to be fitted.

CLKin0 – to select this input as a source for Clock buffer (IC52) R375 resistor has to be removed (removed by default). As a source for this input one of the following high-precision crystal oscillators can be selected:
 * 1) XO1 – 30.72 MHz VCOCXO (precision: ±20 ppb stable);
 * 2) XO2 or XO3 – 30.72 MHz VCTCXO (precision: ±1 ppm initial, ±4 ppm stable);
 * 3) XO4 – 40 MHz VCTCXO (precision: ±1 ppm initial).

IC52 buffer CLKin0 clock source is selected by one of the 0402 size 0R resistor combinations, required modifications can be found in Table 37.

CLKin1 – to select this input as a source for Clock buffer (IC52) R375 resistor has to be fitted (removed by default). As a source for this input one of the following sources can be selected:
 * 1) Clock generator (IC57)
 * 2) U.FL Connector (J36)
 * 3) FPGA (IC29) output pin N21

VCTCXO clock tuning
VCTCXO can be tuned by on-board phase detector (IC53, ADF4002 []) or by 16-bit DAC (IC54). The on-board phase detector is used to synchronize on-board VCTCXO with external equipment (via J36 U.FL connector) to calibrate frequency error. At the same time only ADF or DAC can control VCTCXO. Both ADF and DAC are connected to FPGA_SPI0 interface. For details see chapter SPI interfaces. With valid configuration selection between ADF and DAC is done automatically. When board is powered, by default VCTCXO is controlled by DAC.

Power Distribution
LimeSDR-QPCIe board can be powered from several sources. The first power supply source option is 12V DC through a 2.5mm centre positive barrel connector. The second one is through a standard 6-pin PCIe power connector J38 (0.165” pitch). The last supply source option is the board edge PCIe connector.

LimeSDR-QPCIe board has complex power delivery network consisting of many different power rails with different voltages, filters, power sequences. LimeSDR-QPCIe board power distribution block diagram is presented in Figure 13 in two parts.



Power network power circuit ICs are presented in Figure 14 and Figure 15.