LimeSDR-PCIe v1.2 hardware description

Draft

=	Introduction =

LimeSDR-PCIe is low-cost software defined radio board based on Lime LMS7002M Field Programmable Radio Frequency (FPRF) transceiver and Altera Cyclone IV GX PFGA, through which apps can be programmed to support any type of wireless standard, e.g. UMTS, LTE, LoRa, GPS, WiFi, Zigbee, RFID, Digital Broadcasting, Radar and many more.

= Complete Development Kit Package =

The LimeSDR-PCIe v1.2 board from full package showed in Figure 1.



Development kit content:
 * LimeSDR-PCIe v1.2 board
 * USB stick containing following files:
 * Doc/ 		- Documentation files for LimeSDR-PCIe
 * Drivers/	- Windows drivers for LimeSDR-PCIe
 * Gateware/	- FPGA gateware related files for LimeSDR-PCIe v1.2
 * Gui/		- LimeSuiteGUI software and related files

= LimeSDR-PCIe Board Key Features =

The LimeSDR-PCIe development board provides a hardware platform for developing and prototyping high-performance and logic-intensive digital and RF designs using Altera’s Cyclone IV GX FPGA and Lime Microsystems transceiver.

LimeSDR-PCIe board features:
 * RF transceiver:
 * Lime Microsystems LMS7002M
 * FPGA Features
 * Cyclone IV GX (EP4CGX30CF23C7N) device in 484-pin FBGA
 * 29’440 logic elements
 * 1080 Kbits embedded memory
 * 80 embedded 18x18 multipliers
 * 4 general and 2 multipurpose PLLs
 * 4 high-speed transceivers
 * PCIe (PIPE) hard IP block
 * FPGA Configuration
 * JTAG mode configuration
 * Active serial mode configuration
 * Possibility to update FPGA gateware by using PCIe interface
 * Memory Devices
 * 2x 1Gbit (64M x 16) dual channel DDR2 SDRAM
 * 4Mbit flash for FPGA data
 * 64Mbit flash for FPGA gateware
 * 128Kb (16K x 8) EEPROM for LMS MCU firmware and 512Kb (64K x 8) LMS MCU data
 * Connections
 * PCI Express x4 (4 lanes)
 * Coaxial RF (U.FL) connectors
 * FPGA GPIO 2x8 (3.3V) headers
 * FPGA and JTAG connector
 * DC (12V) power jack and pinheader
 * FAN (12V) connector
 * Clock System
 * 30.72MHz ±250 ppb onboard VCTCXO
 * Possibility to lock VCTCXO to external clock or tune VCTCXO by onboard DAC
 * Programmable clock generator for the FPGA reference clock input or LMS PLLs
 * 100 MHz and 2x 50MHz crystal oscillators for FPGA
 * Board Size 68,9mm x 136,85mm

For more information on the following topics, refer to the respective documents:
 * Cyclone IV device family, refer to Cyclone IV Device Handbook [link]
 * LMS7002M transceiver resources [link