STREAM OpenRISC

About
The Stream OpenRISC SoC is a complete System on Chip running on the FPGA on the STREAM board. Its main usage is to control all the on-board peripheral devices and to provide a standalone platform for software defined radio applications. With the supplied Linux image, the SoC is capable of: For special purpose applications, the Linux image can be replaced with a light-weight real-time operating system (RTOS) or a custom bare-metal application to increase performance and real-time capabilities.
 * Generating I/Q data in software to send to a MyriadRF board
 * Receiving I/Q samples that can be processed with the on-chip OpenRISC CPU or forwaded to the USB3 interface
 * Connect to a network with Ethernet
 * Handle user I/O with a UART

Specification
The Stream OpenRISC SoC consists of an OpenRISC CPU connected to various peripheral devices.

Boot ROM
The boot ROM contains the first instructions that the OpenRISC CPU will read after reset. The default behaviour is to clear register r3 and jump to address 0x100 and continue to load an application from there.

CPU
The OpenRISC Stream SoC uses mor1kx as main CPU.

Ethernet MAC
The 10/100 Mbps Ethernet MAC is used for Ethernet communication.

FX3
The FX3 interface is used for streaming received I/Q data to the on-board FX3 USB3 controller. The FX3 core implements a simple interface for writing to a synchronous slave interface of a Cypress FX3. Most parameters are fixed except for a input flag to signal flow control from the FX3 and data and write enable outputs to the FX3. The internal user interface consists of a 16-bit stream port. The FX3 interface should be connected directly to pins interfacing the FX3. The Stream interface provides a port for providing data to the FX3 core. A successful transaction of a word occurs when both the valid and ready signals are asserted. This interface is synchronous to clk.

GPIO
The GPIO block is connected to the remaining FPGA_GPIO pins not used by UART. All pins can be programmed as either input or output separately. More documentation is available on the GitHub page.

Main Memory
The Main Memory controller is connected to 64MB DDR2 SDRAM. This memory is used for instructions and data for applications and operating systems.

TX/RX Memory
The TX/RX Memory controller is connected to 64MB DDR2 SDRAM. This memory is used for storing I/Q samples that are received, or to be transmitted from/to the LMS controller.

Myriad-RF Interface
The Myriad-RF Interface, also known as the LMS6002D IF, is responsible for communication with a Myriad-RF 1 board. The external interface consists of an RX interface and a TX interface and the internal interfaces consist of two Wishbone master interfaces for streaming I/Q data to and from RAM, a Wishbone slave interface for control of Myriad-RF IF and a stream port for accessing the received data stream directly.

Interfaces
The TX interface should be connected directly to pins interfacing the MyriadRF, except for tx_rst which should be synchronized internally. The RX interface should be connected directly to pins interfacing the Myriad-RF 1, except for rx_rst which should be synchronized internally. The RX Stream interface provides a port for directly reading out the data stream from Myriad-RF 1. A successful transaction of a word occurs when both the valid and ready signals are asserted. This interface is synchronous to wb_clk. The Wishbone slave interface is used for control and status of the MyriadRF core. The memory map is detailed below.

UART
The UART is used for standard input/output for software running on the SoC. The following pins are connected to the UART: More documentation is available from OpenCores.org.

SoC Project Structure

 * stream.system
 * FuseSoC System configuration file


 * stream.core
 * FuseSoC core configuration file


 * doc
 * Documentation
 * Makefile - Makefile to regenerate HTML docs
 * \*.txt - AsciiDoc sources
 * \*.html - HTML Documentation


 * data
 * Miscellaneous files
 * stream.dts - Device Tree Source file
 * stream.sdc - Timing constraints
 * stream_defconfig - Linux default configuration
 * pinmap.tcl - Pin mapping and I/O configuration
 * wb_intercon_dbg.conf - Interconnect configuration file for mor1kx_dbg_wrapper
 * options.tcl - Additional options for Quartus II
 * winbond_w9751g6kb25.xml - Memory preset file for on-board DDR2 memories
 * wb_intercon.conf - Configuration file for main Wishbone interconnect


 * rtl/verilog
 * SoC-specific verilog source code
 * mor1kx_dbg_wrapper.v - Wrapper file for CPU, debug system and boot ROM
 * rst_sync.v - Reset synchroniser
 * include/timescale.v - Default verilog timescale setting
 * include/uart_defines.v - UART default settings
 * include/ethmac_defines.v - Ethernet MAC default settings
 * stream_top.v - Stream SoC top-level
 * wb_intercon.v - Main Wishbone Interconnect
 * wb_intercon.vh - Main Wishbone Interconnect include file
 * wb_intercon_dbg.v - mor1kx_dbg Wishbone Interconnect
 * wb_intercon_dbg.vh - mor1kx_dbg Wishbone Interconnect include file
 * altmemphy_wrapper.v - Wrapper for memory controller and arbiter
 * clkgen.v - Clock generation


 * bench
 * Testbench
 * stream_tb.v - Stream SoC testbench wrapper
 * test-defines.v - Test defines file


 * ip
 * Proprietary IP cores
 * pll - Main PLL
 * ddr2_ctrl - Altera Altmemphy DDR2 Controller