LimeSDR-QPCIe v1.2 hardware description

Introduction
LimeSDR-QPCIe is low-cost software defined radio board based on Lime LMS7002M Field Programmable Radio Frequency (FPRF) transceiver and Altera Cyclone V PFGA, through which apps can be programmed to support any type of wireless standard, e.g. UMTS, LTE, LoRa, GPS, WiFi, Zigbee, RFID, Digital Broadcastimng, Radar and many more.

LimeSDR-QPCIe Board Key Features
The LimeSDR-QPCIe development board provides a hardware platform for developing and prototyping high-performance and logic-intensive digital and RF designs using Altera’s Cyclone V FPGA and Lime Microsystems transceiver.



For more information on the following topics, refer to the respective documents:
 * Cyclone V device family, refer to Cyclone V Device support resources link
 * LMS7002M transceiver resources link

LimeSDR-QPCIe v1.2 board features:
 * USB Interface
 * Cypress FX3 Super Speed USB 3rd generation controller
 * FPGA Features
 * Cyclone V, 5CGXFC7D7F31C8N device in 896-pin FBGA package
 * 150’000 logic elements
 * 6860 Kbits embedded memory
 * 312 embedded 18x18 multipliers
 * 7 PLLs
 * 9 Transceivers (2.5Gbps)
 * PCIe Hard IP Blocks
 * 2 Hard Memory Controllers


 * FPGA Configuration
 * JTAG mode configuration
 * Active serial mode configuration
 * Possibility to update FPGA gateware by using FX3 (USB)
 * Possibility to update FPGA gateware by using PCIe interface.


 * RF
 * 2x LMS7002M, FPRF transceivers
 * Onboard RSSI measurement circuits
 * Onboard loopback control switches


 * DACs and ADCs
 * 2x DAC5672A, dual, 14-bit, Digital-To-Analog converters
 * 1x ADS424, Dual-Channel, 14-bit, Analog-To-Digital converter


 * Memory Devices
 * 4 x 2Gbit DDR3 SDRAM (128M x 16)
 * 4Mbit flash for FX3 firmware
 * 128Mbit flash for FPGA gateware
 * 2 x 128Kbit and 2 x 512Kbit EEPROMs for LMS MCU firmware, LMS MCU data
 * 1 x 128K EEPROM for FX3 or FPGA data


 * Connections
 * microUSB3.0 (type B) connector
 * PCIe x4 edge connector (Gen1)
 * Coaxial RF (U.FL) connectors
 * 2x PMOD header (0.1” pitch)
 * FPGA (0.1” pitch) and FX3 (0.05” pitch) JTAG connectors
 * 12V DC power jack and pinheader
 * LVDS connector (0.05” pitch)
 * Fan connector (12V/5V)
 * PCIe 6-pin power connector
 * Holder for coin cell CR1220 battery


 * Clock System
 * 30.72MHz VCTCXO (precision: ±1 ppm initial, ±4 ppm stable).
 * Possibility to lock VCTCXO to external clock using ADF4002 or tune VCTCXO by onboard DAC (AD5662)
 * Programmable clock generator for the FPGA reference clock input or LMS PLLs
 * VCTCXO clock output for external device synchronization.
 * 1x 100 MHz, 4 x 125MHz crystal oscillators for FPGA


 * Miscellaneous devices
 * LM75 Digital temperature sensor with 2-Wire Interface.
 * DS3231 real-time clock.
 * M0578-A3 GPS/GNSS module receiver


 * Board Size 190mm x 106.7mm (7.48” x 4.20”)

LimeSDR-QPCIe Board Overview
LimeSDR-QPCIe board version 1.2 picture with highlighted major connectors presented in Figure 2. There are three connector types – data and debugging (PCIe, USB3.0, PMOD, LVDS and JTAG), power (DC jack and external supply pinheaders) and high frequency (RF and reference clock).

Board components description listed in the Table 1.

LimeSDR-QPCIe board version 1.2 picture with highlighted top components are presented in Figure 3.

LimeSDR-QPCIe board version 1.2 picture with highlighted bottom components is presented in Figure 4.



LimeSDR-QPCIe Board Architecture
The heart of the LimeSDR-QPCIe board is Altera Cyclone V GX FPGA. Its main function is to transfer digital data between the PC through an edge PCIE and a USB3.0 connector. The block diagram for LimeSDR-QPCIe board is presented in the Figure 5.

FPGA configuration
FPGA is set to use x1 Active Serial (AS) configuration scheme. In this scheme if valid configuration file exists in FLASH memory (IC30 or IC32) it is automatically loaded after power is applied to the board. In Table 2 it is listed resistor setup for Active Serial (AS) configuration mode select.

There are two options which allows to change configuration file in FLASH memory: •	USB 3.0 controller – CYUSB3013 (IC42) has access to configuration memory. With valid firmware and software, gateware for FPGA can be uploaded into FLASH memory (IC30 or IC32) by using USB3.0 cable. IC42 can initiate FPGA reconfiguration. For signal interconnect details see chapter 2.2.2.3 USB 3.0 Controller. •	JTAG Header – 10pin connector (J26) provides access to FPGA JTAG chain. By using external download cable such as USB-Blaster and Quartus II Programmer software FLASH memory (IC30 or IC32) can be reprogrammed. JTAG connections are listed in Table 3.