DE0-Nano Interface Board Connections

DE0-Nano Interface Board Connections
The following table describes the pin assignment for each connector on the digital interface board:

J1 and J3 - +5 V Power Connectors
These pin header type connectors used as jumpers to supply +5 V for the Myriad-RF 1 board and DE0-Nano FPGA module. The options are used as shown below:
 * Use jumper on J1 if Myriad-RF 1 is to receive power from the interface board.
 * Use jumper on J3 if DE0-Nano power is supplied from the interface board.

J2 - Digital I/O Connector
The Myriad-RF board is directly plugged into the J2 connector. The digital I/O connector is a digital transmit (TX) and receive (RX) interface to the ADC/DAC of the LMS6002D. The SPI interface for LMS6002DFN can also be established via J2 connector.

J4 - Mini-USB Connector
The interface with USB microcontroller and PC is established via mini USB connector. This connector also powers the microcontroller.

J5 - EEPROM Boot Memory Connector
This connector enables the USB microcontroller to load the firmware at startup.

J6 - CLK Output Connector
J6 is an SMA type connector, used to synchronise measurement equipment with the development kit.

J7 - Frequency Synthesiser Enable Connector
J7 is a pin-header type connector. Pin 3 and Pin 4 have to be shorted in normal operation, thus enabling frequency synthesiser outputs.

J8 and J9 - Main Power Supply Connectors
The main power supply connector is on the interace board, providing power to both the interface as well as the Myriad-RF 1 board.

JA1 - FPGA Module Connectors Array
JA1 is a connection array for the DEO-Nano FPGA Development System. Physically, there are two separate connectors on the board. This connector establishes the interface between the Myriad-RF 1 board's digital interface and FPGA module with the PC.

Hardware Options
The board is shipped in a default mode for basic operation. Various options are available depending on the system configuration required for testing or development work. The options are summarised below and the following sections describe the board modifications required to achieve these configurations.

Reference Frequency and Data Clocks Distribution
The LMS6002D device provides a flexible clocking scheme which enables the PLL clock, RX clock and TX clock to be independently set. The development kit is shipped with a default mode using the on board 30.72 MHz clock for PLL clock only. The board can be reconfigured to allow users to provide clock frequency for digital interface and PLL clock using programmable clock generator from Silicon Labs (Si5356) which is capable of synthesising four independent frequencies. The device has four outputs connected to the LMS6002DFN PLL clock, RX data interface clock, TX data interface clock and to the J6 connector. In order to reprogram the frequency from the default setting of 30.72 MHz, please use component change as given in the table below. Please note that NF denotes that component is not fitted:

SPI Options
The Myriad-RF 1 board offers two options for SPI communications: SPI communication is established via the FPGA and USB microcontroller located on the interface board; or SPI communication is established via the Myriad-RF 1's own USB microcontroller. In order to ensure stable SPI communication for your chosen option, the interface board may require a component change. Please note that NF denotes that component is not fitted:

GPIO Control Truth Table
The RF switches on the RF board are controlled via the GPIO0-2 logic signals, provided by the FPGA module on the interface board. This enables the user to choose RF input/output depending on the operation frequency. The truth table of the GPIO0-2 settings is shown below: