LimeSDR-USB User Guide

About
The LimeSDR-USB development board provides a hardware platform for developing and prototyping high-performance and logic-intensive digital and RF designs using Altera’s Cyclone IV FPGA and Lime Microsystems LMS7002M transceiver.

For more information on the following topics, refer to the respective documents: Cyclone IV Device Handbook LMS7002M transceiver resources

USB interface

 * Cypress FX3 Super Speed USB 3rd generation controller

FPGA features

 * Cyclone IV EP4CE40F23C8N device in 484-pin FPGA
 * 39,600 logic elements
 * 1,134Kbits embedded memory
 * 116 embedded 18x18 multipliers
 * 4 PLLs

FPGA configuration

 * JTAG mode configuration
 * Active serial mode configuration
 * Possibility to update FPGA gateware by using FX3 (USB)

Memory devices

 * 2x 1Gbit (64M x 16) DDR2 SDRAM
 * 4Mbit flash for FX3 firmware
 * 16Mbit flash for FPGA gateware
 * 3x 64K (8K x 8) EEPROMs for LMS MCU firmware, LMS MCU data, and FX3 data

Connections

 * 6-12V DC power jack
 * FPGA GPIO headers
 * Micro-USB 3.0 (Type B) connector or USB 3.0 (Type A) plug
 * Coaxial RF (U.FL) connectors

Clock system

 * 30.72MHz ±250 ppb on-board VCTCXO
 * Possibility to lock VCTCXO to external clock or tune VCTCXO by onboard DAC
 * Programmable clock generator for the FPGA reference clock input or LMS PLLs

Board size

 * Board Size 60mm x 100mm (2.36” x 3.94”)

Board overview
LimeSDR-USB board version 1.2 with highlighted major connections. There are three connector types: data and debugging (USB 3.0, FPGA GPIO, and JTAG), power (DC jack and external supply pin header), and high frequency (RF and reference clock).

Board components, top side
LimeSDR-USB board version 1.2 pictured with highlighted components on the top side.

Board components, bottom side
LimeSDR-USB board version 1.2 pictured with highlighted components on the bottom side.

LimeSDR-USB board architecture
The heart of the LimeSDR-USB board is an Altera Cyclone IV FPGA. It’s main function is to transfer digital data between the PC and the radio through a USB 3.0 connector.

Digital interface signals
LMS7002 is using data bus LMS_DIQ1_D[11:0] and LMS_DIQ2_D[11:0], LMS_ENABLE_IQSEL1 and LMS_ENABLE_IQSEL2, LMS_FCLK1 and LMS_FCLK2, LMS_MCLK1 and LMS_MCLK2 signals to transfer data to/from FPGA. Indexes 1 and 2 indicate transceiver digital data PORT-1 or PORT-2. Any of these ports can be used to transmit or receive data. By default PORT-1 is selected as transmit port and PORT-2 is selected as receiver port. The FCLK# is input clock and MCLK# is output clock for LMS7002M transceiver. TXNRX signals sets ports directions. For LMS7002M interface timing details refer to LMS7002M transceiver datasheet pages 12-13.

SPI interface
LMS7002M transceiver is configured via 4-wire SPI interface: FPGA_SPI0_SCLK, FPGA_SPI0_MOSI, FPGA_SPI0_MISO, FPGA_SPI0_LMS_SS. The SPI interface is controlled from FPGA Bank 8 (VDIO_LMS_FPGA, 3.3V).

I²C interface
The I²C interface is used to control external clock synthesiser on UNITE7002 board. The signals LMS_I2C_CLK and LMS_I2C_DATA are connected to FPGA Bank 8 (VDIO_LMS_FPGA, 3.3V).

Control signals
These signals are used for optional functionality.
 * LMS_RXEN, LMS_TXEN – receiver and transmitter enable/disable signals connected to FPGA Bank 8 (VDIO_LMS_FPGA, 3.3V).
 * LMS_RESET – LMS7002M reset connected to FPGA Bank 7 (VDIO_LMS_FPGA, 3.3V).

SDRAM
The LimeSDR-USB board has two 128 MB (16-bit bus) DDR2 SDRAM ICs (AS4C64M16D2-25BCN) connected to double data rate pins onCyclone IV 1.8V Bank 2, Bank 3 and Bank 4. RAM chips are connected to separate memory controllers to operate in dual channel mode. The memory can be used for data manipulation between transceiver and FPGA at high date rates.

USB 3.0 controller
Software controls the LimeSDR-USB board via the USB 3.0 microcontroller (CYUSB3014). The data transfer to/from the board, SPI communication, and FPGA configuration are all done via the USB 3.0 controller.
 * FX3_DQ[31:0] – FX3 32-bit GPIF data interface is connected to Cyclone IV 1.8V Bank 5.
 * FX3_CTL[8:0], [12:11] – FX3 GPIF interface control signals.
 * FX3_PCLK – GPIF interface clock
 * GPIO[26:25] – FX3 (USB) status LED (LED5).
 * FX3 SPI interface – program IC8 flash memory, boot from IC8 flash memory.
 * FX3 I²C bus – connected to the I2C to SPI bridge IC12, I2C port expander IC10, temperature sensor IC9 and EEPROM memory IC11.
 * PMODE[2:0] – boot options, by default boot from SPI and USB boot is enabled. If J13 jumper is present FX3 will boot from IC8 flash memory if correct firmware exists.
 * SW1 – resets FX3
 * J12 – FX3 JTAG programming/debugging pin header.

Indication LEDs
The LimeSDR-USB board comes with four indication LEDs: LEDS1 (LED1, LED4) and LEDS2 (LED5, LED8). LED1, LED4 and LED5 are user defined and connected to the FPGA and USB 3.0 controller as shown. LED8 is hardwired to VCC3P3 power rail and is lit up whenever the board is powered on. By default, dual-colour SMD LEDs are populated and through-hole LEDs are unpopulated. If required, the user can fit dual-colour 3mm diameter through-hole LEDs with a dedicated right-angle plastic holder.

Low-speed interfaces
The LimeSDR-USB board's low speed interfaces are divided into FX3 and FPGA groups. The following block diagrams depict the main ICs, corresponding IC pin numbers, data buses, and serial protocol addresses.

FX3 low-speed interfaces
LimeSDR-USB board peripherals are controlled via the USB interface. All commands that comes from USB are firstly processed by the FX3 controller. If an I²C peripheral (temperature sensor, port expander, clock generator) on FX3_I2C bus must be controlled this can be done directly. FX3_I2C is also connected to the FPGA.

FPGA low-speed interfaces
FX3 hardware SPI cannot be used if the 32-bit GPIF interface is configured. If SPI (RFIC, frequency synthesiser, clock generator) devices must be controlled by FX3, firstly it transfers data to I²C-SPI bridge. Depending on required SPI slave device, there could several possibilities: If FX3 firmware flash memory content must be updated, then FX3 switches to 16-bit GPIF mode to directly accesses flash content.
 * Flash for FPGA gateware: using SPDT switch (IC32) flash memory is switched from FPGA to I²C-SPI bridge. Then flash content is updated and flash memory is switched back to FPGA. This is done to update the FPGA gateware in flash memory.
 * FPGA: FPGA has its own SPI module and can be controlled as regular SPI device. By using FPGA SPI it is possible to control FPGA modes, etc. The FPGA can also act as bridge between BRDG_SPI and FPGA_SPI0 or FPGA_SPI1.
 * RFIC, clock synthesiser, clock generator: to control a device on FPGA_SPI0 or FPGA_SPI1 from BRDG_SPI, the FPGA must be configured to select the corresponding slave device and then it operates as bridge. When the transaction with the slave is completed, the slave must be deselected.

Clock distribution
The LimeSDR-USB board has an on-board 30.72 MHz ±250 ppb VCTCXO that acts as a reference clock for LMS_PLLs. The on-board frequency synthesiser (ADF4002) is used to synchronise the on-board VCTCXO with external equipment (via the J14 U.FL connector) to calibrate frequency error. On-board DAC also can be used to tune VCTCXO. At the same time only ADF or DAC can control VCTCXO. DAC and ADF is controlled by FX3 (SUB) and selection between ADF and DAC is done automatically. The J14 connector can also be used to supply external reference clock (by fitting R106 and removing R96, C212). The programmable clock generator (Si5351C) can generate any reference clock frequency, starting from 8 kHz – 160 MHz, for FPGA and LMS PLLs

Power distribution
The LimeSDR-USB board can be powered from its USB port. In applications where USB power is insufficient, the board can be powered from an external 6 – 12 V power supply. External power can be fed to the J18 barrel power connector using power plug (1.35mm ID, 3.5mm OD) or pin header J19 (GND and VCC_EXT). The LimeSDR-USB board has automatic source selection between USB and external source, with polarity protection.

Driver installation
The communication between the LimeSDR-USB board and a host PC running the lms7suite software is done via the USB 3.0 interface.

Windows driver installation
See the Lime Suite hardware notes.

Linux driver installation
The USB 3.0 drivers for the LimeSDR-USB are included in the libusb library, which is installed by default in most Linux distributions. Manual installation of specific drivers is not required.

Flashing FX3 and FPGA images
See Lime Suite hardware notes.

Uploading firmware to empty FX3 flash
If the external flash connected to the FX3 USB 3.0 microcontroller is empty, short jumper J13 then connect the LimeSDR-USB board to the host PC. Start the "CyControl.exe" application and click "Cypress USB BootLoader" Click the menu command "Program FX3 SPI FLASH". The status bar of the USB Control Cneter application will indicate "Waiting for Cypress Boot Programmer device to enumerate", then after some time a pop-up window will appear. Select your new firmware image file (file extension "*.img") and press "Open". The status bar will indicate "Programming of SPI FLASH in Progress". This message will change to "Programming succeeded" after flash programming is complete.

NOTE: The USB 3.0 microcontroller will boot from firmware uploaded to flash at every power-on if jumper J3 is shorted.

Document Version
Based on LimeSDR-USB v1.2 User Manual, Version 00.06.

Changes since document generation:


 * Removed most of the flashing documentation and linked to it on the Lime Suite page.
 * Minor typographical and grammatical changes.
 * Extended instructions in Windows driver installation.