User contributions for Ghalfacree
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21 March 2018
- 17:0817:08, 21 March 2018 diff hist +5,327 N LimeSDR Firmware Management Initial Page Creation
- 17:0617:06, 21 March 2018 diff hist +3,108 N LimeSDR Windows Driver Installation Initial Page Creation
- 17:0617:06, 21 March 2018 diff hist +5,983 N LimeSDR Hardware Installation Initial Page Creation
- 17:0517:05, 21 March 2018 diff hist +2,024 N Getting Started with the LimeSDR Initial Page Creation current
- 17:0317:03, 21 March 2018 diff hist +3,963 N Installing Lime Suite on Windows Initial Page Creation current
- 17:0217:02, 21 March 2018 diff hist +1,460 N Installing Lime Suite on macOS Initial Page Creation
- 17:0117:01, 21 March 2018 diff hist +5,084 N Installing Lime Suite on Linux Initial Page Creation
- 16:5916:59, 21 March 2018 diff hist +1,852 N Getting Started with Lime Suite Initial Page Creation current
- 16:5616:56, 21 March 2018 diff hist +746 N Getting Started with Myriad-RF Initial Page Creation
21 February 2018
- 15:3815:38, 21 February 2018 diff hist −4 m LimeSDR-USB Quick Test Changed 'Packets MIMO' to 'LMS MIMO' to match latest Lime Suite GUI. current
- 14:5014:50, 21 February 2018 diff hist +1,821 LimeSDR Quick Start Update for physical cabling, firmware update, and other additional details. current
3 June 2017
- 23:1623:16, 3 June 2017 diff hist 0 m LimeADPD Capitalisation correction.
- 23:1623:16, 3 June 2017 diff hist 0 m LimeADPD Changed comma to full stop.
- 23:0523:05, 3 June 2017 diff hist +13,754 N LimeADPD Initial page creation.
- 22:5522:55, 3 June 2017 diff hist +33 N File:Adpd-test-case-2-acpr-with-adpd.png ADPD test case 2, ACRP with ADPD. current
- 22:5522:55, 3 June 2017 diff hist +36 N File:Adpd-test-case-2-acpr-without-adpd.png ADPD test case 2, ACPR without ADPD. current
- 22:5222:52, 3 June 2017 diff hist +32 N File:Adpd-test-case-1-evm-with-adpd.png ADPD test case 1, EVM with ADPD. current
- 22:5122:51, 3 June 2017 diff hist +35 N File:Adpd-test-case-1-evm-without-adpd.png ADPD test case 1, EVM without ADPD. current
- 22:5022:50, 3 June 2017 diff hist +33 N File:Adpd-test-case-1-acpr-with-adpd.png ADPD test case 1, ACPR with ADPD. current
- 22:4822:48, 3 June 2017 diff hist +36 N File:Adpd-test-case-1-acpr-without-adpd.png ADPD test case 1, ACPR without ADPD. current
- 22:4622:46, 3 June 2017 diff hist +37 N File:Adpd-test-case-1-pa-output-spectrum.png ADPD test case 1, PA output spectrum. current
- 22:4422:44, 3 June 2017 diff hist +41 N File:Adpd-test-case-1-signals-after-training.png ADPD test case 1, signals after training. current
- 22:4222:42, 3 June 2017 diff hist +42 N File:Adpd-test-case-1-signals-before-training.png ADPD test case 1, signals before training. current
- 22:1722:17, 3 June 2017 diff hist +71 N File:Adpd-implementation-on-limesdr-qpcie-board-block-diagram.png An ADPD implementation block diagram, based on the LimeSDR-QPCIe board. current
- 15:3015:30, 3 June 2017 diff hist +51 N File:Adpd-indirect-learning-architecture-block-diagram.png ADPD indirect learning architecture, block diagram. current
3 June 2016
- 15:4315:43, 3 June 2016 diff hist 0 m LimeMicro:LMS7002M Datasheet →MCU boot-up and EEPROM programming current
- 15:1815:18, 3 June 2016 diff hist +92,762 N LimeMicro:LMS7002M Datasheet Initial page creation and content transfer.
2 June 2016
- 21:5221:52, 2 June 2016 diff hist +53 N File:Lms7002m-typical-digital-interface-configuration.png LMS7002M in a typical digital interface configuration current
- 21:4721:47, 2 June 2016 diff hist +44 N File:Lms7002m-typical-rf-application-circuit.png LMS7002M in a typical RF application circuit current
- 21:2421:24, 2 June 2016 diff hist +39 N File:Lms7002m-261l-aqfn-package-top.png LMS7002M in 261L aQFN package, top view current
- 21:1421:14, 2 June 2016 diff hist +48 N File:Lms7002m-calibration-digital-filtering-step-c.png LMS7002M calibration, digital filtering step (c) current
- 21:1021:10, 2 June 2016 diff hist +48 N File:Lms7002m-calibration-digital-filtering-step-b.png LMS7002M calibration, digital filtering step (b) current
- 21:1021:10, 2 June 2016 diff hist +48 N File:Lms7002m-calibration-digital-filtering-step-a.png LMS7002M calibration, digital filtering step (a) current
- 21:0321:03, 2 June 2016 diff hist +57 N File:Lms7002m-calibration-iq-imbalance-spectral-tones.png LMS7002M calibration, IQ imbalance spectral tones example current
- 20:4820:48, 2 June 2016 diff hist +38 N File:Lms7002m-calibration-pass-band.png LMS7002M calibration, pass-band tuning current
- 20:4020:40, 2 June 2016 diff hist +28 N File:Lms7002m-calibration-vcocap.png LMS7002M calibration, VCOCAP current
- 20:3020:30, 2 June 2016 diff hist +33 N File:Lms7002m-clock-generation.png LMS7002M clock generation diagram current
- 20:2320:23, 2 June 2016 diff hist +51 N File:Lms7002m-mcu-connections.png LMS7002M on-chip microcontroller connection diagram current
- 20:2120:21, 2 June 2016 diff hist +29 N File:Lms7002m-spi-supplies.png LMS7002M SPI supplies diagram current
- 20:0720:07, 2 June 2016 diff hist +46 N File:Lms7002m-spi-read-cycle-3-wire-timing.png LMS7002M SPI read cycle, 3-wire timing diagram current
- 20:0720:07, 2 June 2016 diff hist +48 N File:Lms7002m-spi-read-cycle-4-wire-timing.png LMS7002M SPI read cycle, 4-wire (default) timing current
- 20:0620:06, 2 June 2016 diff hist +39 N File:Lms7002m-spi-write-cycle-timing.png LMS7002M SPI write cycle timing diagram current
- 17:2717:27, 2 June 2016 diff hist +47 N File:Lms7002m-digital-iq-interface-supplies.png LMS7002M digital IQ interface supplies diagram. current
- 17:2317:23, 2 June 2016 diff hist +68 N File:Lms7002m-limelight-trxiq-sdr-transmit-data-path.png LMS7002M LimeLight TRXIQ SDR mode transmit data path timing diagram. current
- 17:2217:22, 2 June 2016 diff hist +67 N File:Lms7002m-limelight-trxiq-sdr-receive-data-path.png LMS7002M LimeLight TRXIQ SDR mode receive data path timing diagram. current
- 17:2217:22, 2 June 2016 diff hist +68 N File:Lms7002m-limelight-trxiq-ddr-transmit-data-path.png LMS7002M LimeLight TRXIQ DDR mode transmit data path timing diagram. current
- 17:2117:21, 2 June 2016 diff hist +67 N File:Lms7002m-limelight-trxiq-ddr-receive-data-path.png LMS7002M LimeLight TRXIQ DDR mode receive data path timing diagram. current
- 17:2017:20, 2 June 2016 diff hist +68 N File:Lms7002m-limelight-jesd207-receive-burst-finish.png LMS7002M LimeLight JESD207 mode receive burst finish timing diagram. current
- 17:1917:19, 2 June 2016 diff hist +67 N File:Lms7002m-limelight-jesd207-receive-burst-start.png LMS7002M LimeLight JESD207 mode receive burst start timing diagram. current
- 17:1817:18, 2 June 2016 diff hist +69 N File:Lms7002m-limelight-jesd207-transmit-burst-finish.png LMS7002M LimeLight JESD207 mode transmit burst finish timing diagram. current