LimeSDR GPIO Board
An expansion board for the LimeSDR family that provides individually settable, bi-directional level-shifted I/O for FPGA GPIO 0-7. Each I/O has a high-voltage and power Darlington drive stage suitable for inductive loads, such as coaxial relays.
1 Key features
- Provides bi-directional level shifted IO for GPIO 0-7
- 1.2-5.5V IO on J2
- Each IO has a high voltage and power Darlington drive stage
- Acceptable rating 30V 300mA (0-4) 200mA (5-7)
- Suitable for inductive loads
- Input/Output are individually switch-able
- LimeSDR form factor
- Individually pluggable relay connections
- Data direction switches and data indication
- J2 Level shifted interface (1.2-5.5V)
- J1 (cable) and J23 (direct connection)
- LimeSDR interface (3v3 only)
- Power input
- Relay out 0 to 3
- Relay out 4 to 7
2.2 Relay outputs and power in
All 8 relay outputs are designed with inductive load switching in mind.
Channels 0-4 have 3 stages of the ULN2003A connected so are suitable for high power applications, It is recommended to keep below 300mA to avoid excessive heating.
Power is connected from J6, Use caution when connecting high voltage supplies not to in correctly connect them as they can cause permanent damage to your LimeSDR.
2.3 J3 Power bypass
The GPIO board requires power for the level shifting circuity, J2’s VCC must be connected to your interface logic level (i.e. 5V).
If this the level shifting feature is not being used then connect a jumper on J3 to set the whole board to 3v3.
NOTE: DO NOT PROVIDE POWER TO J2 WHEN J3 IS CONNECTED!
Connect as normal with LimeSuiteGUI within the board controls tab there is a GPIO control section. “Dir” Ticked is an output un-ticked an input.
These control examples use Python, this comes as part of Soapy SDR please see https://github.com/pothosware/SoapySDR/wiki/PythonSupport for install instructions.