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LimeMicro:LMS6002D FAQ

Revision as of 18:04, 13 October 2015 by AndrewBack (Talk | contribs)

LMS6002D and evaluation board FAQ.


1 Latest documentation

1.1 Where can I find the latest datasheet for LMS6002DFN and other related documentation?

Please also see the GitHub repository, as this contains documentation that has not made it onto the wiki yet.

2 Graphical User Interface (GUI)

See the LMS Suite FAQ.

3 EVB testing

3.1 How can a 3GGP waveform be transmitted via the LMS6002DFN chip?

3.2 What settings are required for operation with Analog IQ signals?

3.3 Do I need to use the ADF4002 option?

3.4 How should I synchronize measurement equipment with the evaluation/interface board?

3.5 How do I select VCOCAP code for the desired frequency?

3.6 Which clock buffers have to be enabled for the normal operation of LMS6002DFN?

3.7 How should I connect the Lime evaluation board to the HSMC connector?

3.8 Does LMS6002DFN require a specific order for setting up the internal registers on power on? Should there be a time delay between every register set?

3.9 Where are the spurs coming from around the carrier signal at +/-200 kHz?

3.10 What is the common mode voltage and voltage swing setting to drive Tx Analog (baseband) input ports?

4 Calibration procedures

4.1 What is the LO leakage calibration procedure for transmitter?

4.2 What is the LO leakage calibration procedure for receiver?

4.3 Is LO leakage calibration required when frequency has been changed?

4.4 TX LO leakage is specified as -50 dBc. Can it be maintained over entire TX dynamic range?

4.5 How many clock cycles are required for DC offset calibration?

4.6 Can I use look-up table of LO leakage calibration over multiple frequencies?

4.7 Why TXLPF, RXLPF, and RXVGA2 calibration routines return with DC_LOCK values of 0?

4.8 How to execute calibration routines if there is no read back function in my baseband?

4.9 Can RX calibration be maintained over the entire Rx dynamic range?

5 RF system questions

5.1 What is total power consumption of LMS6002DFN

5.2 What are the maximum transmitter and receiver gain values?

5.3 What is the receiver and transmitter PLL lock time?

5.4 How to design a new PLL Loop Filter?

5.5 What is the PLL Loop Filter bandwidth?

5.6 What is RF bandwidth of the Tx1 and Tx2 outputs?

5.7 What are the baseband filter bandwidths implemented in LMS6002DFN?

5.8 What is the group delay for 5 MHz and 2.5 MHz filters in LMS6002DFN?

5.9 Does the LNA need to be power down when the RF LOOPBACK is in operation?

5.10 What is the maximum CW signal input level for the receiver?

5.11 What is the IIP3 for the receiver?

5.12 What is the RX Mixer P1dB?

5.13 What is the TX OIP3 (or OIP1) at maximum and minimum gain settings?

5.14 What is RF bandwidth of the receiver inputs?

5.15 What is the TX Noise Figure at maximum gain settings?

5.16 What is transmitter to receiver noise isolation on LMS6002DFN?

5.17 What is the settling time of TX/RX gain blocks after they are set via SPI control?

5.18 What is recommended gain table for the receiver?

5.19 How can RSSI be used in LMS6002DFN?

5.20 How can the VGA1 code be converted into dB’s?

5.21 Can the envelop detectors within the LMS6002DFN be used for calibration?

5.22 Can the internal LPFs be bypassed?

5.23 What is heat thermal resistance and junction temperature of the LMS6002DFN?

5.24 What is VCO’s frequency range?

5.25 How to set LMS6002DFN for TDD operation?

5.26 How to improve receiver linearity?

5.27 What register have to be changed from default values?

5.28 What is the difference between hardware TXEN and STXEN, similarly for hardware RXEN and SRXEN?

5.29 What is the environmental rating for LMS6002DFN?

5.30 What is the KVCO for the VCO frequencies from 4GHz to 8 GHz?

6 LMS6002DFN digital interface

6.1 Does the LMS6002DFN supports JESD207 interface?

6.2 What are recommended CLK_jitter characteristics for Rx_CLK, Tx_CLK and PLL_CLK?

6.3 Is it possible to use 2.5 V data signal and clock signal with the LMS6002DFN internal DACs and ADCs?

6.4 Is RX_CLK_OUT required for RXD sampling?

6.5 Can the sampling clock/rate for internal DAC and ADC be changed on the evaluation board?

6.6 What is the latency of the data converters within the LMS6002DFN?

6.7 What is the maximum sampling rate for DAC’s and ADC’s?

6.8 What is the recommended signal level of reference clock to drive the internal PLLs?

6.9 What type of coupling should be applied for reference clock to the internal PLLs?

6.10 How to improve ADC’s spectrum?

7 Implementation questions

7.1 What is the recommended footprint for the LMS6002DFN?

7.2 What is the power up, down and the reset sequence for LMS6002DFN?

7.3 What are the recommended power supplies for the LMS6002DFN?

7.4 Is it necessary to connect the Pin #42 ATP (Analog Test Point)?

7.5 Can the ADC be left unconnected if it is not used in my application?

7.6 What is the purpose of the 22 Ohm resistors on pins 60 and 84?

7.7 What is recommended metal mask size and depth for solder paste?

7.8 What is the range of operating moisture condition in %?

7.9 What is package warp after reflow soldering?

7.10 According to “LMS6002Dr2 PCB Layout Recommendations-1.0r06.pdf”, page 2, Figure 5, solder paste for GND pattern (center pad) is split into grid of 13x7(0.3mmx0.7mm)rectangles. What is the reason? Is solder volume too much if this GND pattern is not split?

7.11 What is the ramp rate for the LMS6002DFN package?