ClockTamerGPSLocking
Revision as of 15:59, 15 September 2015 by AndrewBack (Talk  contribs)
Introduction
We use an algorithm without complex computations due to the limitations of AVR devices. The hardware timer is capable of counting only frequency less then 3.5Mhz, so the firmware initialize LMK01000 divider to divide 52Mhz to the maximum value below 3.5Mhz. So each 1pps tick it registers 52Mhz/devider ticks of output frequency. According to the EB230 datasheet, 1pps could have 100ns jitter and it's a big value to perform each value without filtration and, furthermore, we found that there is greater deviation. Therefore ClockTamer uses the following algorithm:
 It sums 52Mhz/divider ticks over '`divider`' one pps ticks. So this value represents the output frequency but measured over '`divider`' seconds. Moreover it does more than that. This value wouldn't be the same as if there was no divider at all. Since measuring accumulates over period '`divider`' it reduces jitter.
 It uses exponential filtration in the following equation FilteredVal = (FILTER_EXP_ALPHA1)*(FilteredVal/FILTER_EXP_ALPHA) + (1pps_count); where FILTER_EXP_ALPHA==32, "1pps_count" value of the input counter (for 52Mhz/divider in 1pps sampling)
 If 1pps_count doesn't have less than 1% margin of `FilteredVal/FILTER_EXP_ALPHA` it will not be used and this value disgarded for the first time
 If this occurs more than 3 times in row `FilteredVal` resets and syncronization starts from the beginning
 Each time `FilteredVal` gets updated from the previous state, more than 2bits in absolute the VCO get tuned (it calculates the offset from the internal 20Mhz oscillator and updates its frequency to get the precise output)
